110e730a2SDan Gohman //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
210e730a2SDan Gohman //
310e730a2SDan Gohman //                     The LLVM Compiler Infrastructure
410e730a2SDan Gohman //
510e730a2SDan Gohman // This file is distributed under the University of Illinois Open Source
610e730a2SDan Gohman // License. See LICENSE.TXT for details.
710e730a2SDan Gohman //
810e730a2SDan Gohman //===----------------------------------------------------------------------===//
910e730a2SDan Gohman ///
1010e730a2SDan Gohman /// \file
1110e730a2SDan Gohman /// \brief This file defines the WebAssembly-specific TargetTransformInfo
1210e730a2SDan Gohman /// implementation.
1310e730a2SDan Gohman ///
1410e730a2SDan Gohman //===----------------------------------------------------------------------===//
1510e730a2SDan Gohman 
1610e730a2SDan Gohman #include "WebAssemblyTargetTransformInfo.h"
1710e730a2SDan Gohman #include "llvm/Support/Debug.h"
1810e730a2SDan Gohman #include "llvm/Target/CostTable.h"
1910e730a2SDan Gohman using namespace llvm;
2010e730a2SDan Gohman 
2110e730a2SDan Gohman #define DEBUG_TYPE "wasmtti"
2210e730a2SDan Gohman 
2310e730a2SDan Gohman TargetTransformInfo::PopcntSupportKind
2401612f62SDan Gohman WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
2510e730a2SDan Gohman   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
2601612f62SDan Gohman   return TargetTransformInfo::PSK_FastHardware;
2701612f62SDan Gohman }
28*73d7a555SDan Gohman 
29*73d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
30*73d7a555SDan Gohman   unsigned Result = BaseT::getNumberOfRegisters(Vector);
31*73d7a555SDan Gohman 
32*73d7a555SDan Gohman   // For SIMD, use at least 16 registers, as a rough guess.
33*73d7a555SDan Gohman   if (Vector)
34*73d7a555SDan Gohman     Result = std::max(Result, 16u);
35*73d7a555SDan Gohman 
36*73d7a555SDan Gohman   return Result;
37*73d7a555SDan Gohman }
38*73d7a555SDan Gohman 
39*73d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) {
40*73d7a555SDan Gohman   if (Vector && getST()->hasSIMD128())
41*73d7a555SDan Gohman     return 128;
42*73d7a555SDan Gohman 
43*73d7a555SDan Gohman   return 64;
44*73d7a555SDan Gohman }
45*73d7a555SDan Gohman 
46*73d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
47*73d7a555SDan Gohman     unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
48*73d7a555SDan Gohman     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
49*73d7a555SDan Gohman     TTI::OperandValueProperties Opd2PropInfo) {
50*73d7a555SDan Gohman 
51*73d7a555SDan Gohman   unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
52*73d7a555SDan Gohman       Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
53*73d7a555SDan Gohman 
54*73d7a555SDan Gohman   if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
55*73d7a555SDan Gohman     switch (Opcode) {
56*73d7a555SDan Gohman     case Instruction::LShr:
57*73d7a555SDan Gohman     case Instruction::AShr:
58*73d7a555SDan Gohman     case Instruction::Shl:
59*73d7a555SDan Gohman       // SIMD128's shifts currently only accept a scalar shift count. For each
60*73d7a555SDan Gohman       // element, we'll need to extract, op, insert. The following is a rough
61*73d7a555SDan Gohman       // approxmation.
62*73d7a555SDan Gohman       if (Opd2Info != TTI::OK_UniformValue &&
63*73d7a555SDan Gohman           Opd2Info != TTI::OK_UniformConstantValue)
64*73d7a555SDan Gohman         Cost = VTy->getNumElements() *
65*73d7a555SDan Gohman                (TargetTransformInfo::TCC_Basic +
66*73d7a555SDan Gohman                 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
67*73d7a555SDan Gohman                 TargetTransformInfo::TCC_Basic);
68*73d7a555SDan Gohman       break;
69*73d7a555SDan Gohman     }
70*73d7a555SDan Gohman   }
71*73d7a555SDan Gohman   return Cost;
72*73d7a555SDan Gohman }
73*73d7a555SDan Gohman 
74*73d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
75*73d7a555SDan Gohman                                                 unsigned Index) {
76*73d7a555SDan Gohman   unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
77*73d7a555SDan Gohman 
78*73d7a555SDan Gohman   // SIMD128's insert/extract currently only take constant indices.
79*73d7a555SDan Gohman   if (Index == -1u)
80*73d7a555SDan Gohman     return Cost + 25 * TargetTransformInfo::TCC_Expensive;
81*73d7a555SDan Gohman 
82*73d7a555SDan Gohman   return Cost;
83*73d7a555SDan Gohman }
84