110e730a2SDan Gohman //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
210e730a2SDan Gohman //
310e730a2SDan Gohman //                     The LLVM Compiler Infrastructure
410e730a2SDan Gohman //
510e730a2SDan Gohman // This file is distributed under the University of Illinois Open Source
610e730a2SDan Gohman // License. See LICENSE.TXT for details.
710e730a2SDan Gohman //
810e730a2SDan Gohman //===----------------------------------------------------------------------===//
910e730a2SDan Gohman ///
1010e730a2SDan Gohman /// \file
1110e730a2SDan Gohman /// \brief This file defines the WebAssembly-specific TargetTransformInfo
1210e730a2SDan Gohman /// implementation.
1310e730a2SDan Gohman ///
1410e730a2SDan Gohman //===----------------------------------------------------------------------===//
1510e730a2SDan Gohman 
1610e730a2SDan Gohman #include "WebAssemblyTargetTransformInfo.h"
1710e730a2SDan Gohman #include "llvm/Support/Debug.h"
1810e730a2SDan Gohman #include "llvm/Target/CostTable.h"
1910e730a2SDan Gohman using namespace llvm;
2010e730a2SDan Gohman 
2110e730a2SDan Gohman #define DEBUG_TYPE "wasmtti"
2210e730a2SDan Gohman 
2310e730a2SDan Gohman TargetTransformInfo::PopcntSupportKind
2401612f62SDan Gohman WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
2510e730a2SDan Gohman   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
2601612f62SDan Gohman   return TargetTransformInfo::PSK_FastHardware;
2701612f62SDan Gohman }
2873d7a555SDan Gohman 
2973d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
3073d7a555SDan Gohman   unsigned Result = BaseT::getNumberOfRegisters(Vector);
3173d7a555SDan Gohman 
3273d7a555SDan Gohman   // For SIMD, use at least 16 registers, as a rough guess.
3373d7a555SDan Gohman   if (Vector)
3473d7a555SDan Gohman     Result = std::max(Result, 16u);
3573d7a555SDan Gohman 
3673d7a555SDan Gohman   return Result;
3773d7a555SDan Gohman }
3873d7a555SDan Gohman 
3973d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) {
4073d7a555SDan Gohman   if (Vector && getST()->hasSIMD128())
4173d7a555SDan Gohman     return 128;
4273d7a555SDan Gohman 
4373d7a555SDan Gohman   return 64;
4473d7a555SDan Gohman }
4573d7a555SDan Gohman 
4673d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
4773d7a555SDan Gohman     unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
4873d7a555SDan Gohman     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
49*2c96c433SMohammed Agabaria     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
5073d7a555SDan Gohman 
5173d7a555SDan Gohman   unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
5273d7a555SDan Gohman       Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
5373d7a555SDan Gohman 
5473d7a555SDan Gohman   if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
5573d7a555SDan Gohman     switch (Opcode) {
5673d7a555SDan Gohman     case Instruction::LShr:
5773d7a555SDan Gohman     case Instruction::AShr:
5873d7a555SDan Gohman     case Instruction::Shl:
5973d7a555SDan Gohman       // SIMD128's shifts currently only accept a scalar shift count. For each
6073d7a555SDan Gohman       // element, we'll need to extract, op, insert. The following is a rough
6173d7a555SDan Gohman       // approxmation.
6273d7a555SDan Gohman       if (Opd2Info != TTI::OK_UniformValue &&
6373d7a555SDan Gohman           Opd2Info != TTI::OK_UniformConstantValue)
6473d7a555SDan Gohman         Cost = VTy->getNumElements() *
6573d7a555SDan Gohman                (TargetTransformInfo::TCC_Basic +
6673d7a555SDan Gohman                 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
6773d7a555SDan Gohman                 TargetTransformInfo::TCC_Basic);
6873d7a555SDan Gohman       break;
6973d7a555SDan Gohman     }
7073d7a555SDan Gohman   }
7173d7a555SDan Gohman   return Cost;
7273d7a555SDan Gohman }
7373d7a555SDan Gohman 
7473d7a555SDan Gohman unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
7573d7a555SDan Gohman                                                 unsigned Index) {
7673d7a555SDan Gohman   unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
7773d7a555SDan Gohman 
7873d7a555SDan Gohman   // SIMD128's insert/extract currently only take constant indices.
7973d7a555SDan Gohman   if (Index == -1u)
8073d7a555SDan Gohman     return Cost + 25 * TargetTransformInfo::TCC_Expensive;
8173d7a555SDan Gohman 
8273d7a555SDan Gohman   return Cost;
8373d7a555SDan Gohman }
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