1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file defines the WebAssembly-specific subclass of TargetMachine.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyTargetMachine.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssembly.h"
18 #include "WebAssemblyTargetObjectFile.h"
19 #include "WebAssemblyTargetTransformInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "llvm/Transforms/Utils.h"
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "wasm"
32 
33 // Emscripten's asm.js-style exception handling
34 static cl::opt<bool> EnableEmException(
35     "enable-emscripten-cxx-exceptions",
36     cl::desc("WebAssembly Emscripten-style exception handling"),
37     cl::init(false));
38 
39 // Emscripten's asm.js-style setjmp/longjmp handling
40 static cl::opt<bool> EnableEmSjLj(
41     "enable-emscripten-sjlj",
42     cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
43     cl::init(false));
44 
45 extern "C" void LLVMInitializeWebAssemblyTarget() {
46   // Register the target.
47   RegisterTargetMachine<WebAssemblyTargetMachine> X(
48       getTheWebAssemblyTarget32());
49   RegisterTargetMachine<WebAssemblyTargetMachine> Y(
50       getTheWebAssemblyTarget64());
51 
52   // Register backend passes
53   auto &PR = *PassRegistry::getPassRegistry();
54   initializeWebAssemblyAddMissingPrototypesPass(PR);
55   initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR);
56   initializeLowerGlobalDtorsPass(PR);
57   initializeFixFunctionBitcastsPass(PR);
58   initializeOptimizeReturnedPass(PR);
59   initializeWebAssemblyArgumentMovePass(PR);
60   initializeWebAssemblySetP2AlignOperandsPass(PR);
61   initializeWebAssemblyReplacePhysRegsPass(PR);
62   initializeWebAssemblyPrepareForLiveIntervalsPass(PR);
63   initializeWebAssemblyOptimizeLiveIntervalsPass(PR);
64   initializeWebAssemblyStoreResultsPass(PR);
65   initializeWebAssemblyRegStackifyPass(PR);
66   initializeWebAssemblyRegColoringPass(PR);
67   initializeWebAssemblyExplicitLocalsPass(PR);
68   initializeWebAssemblyFixIrreducibleControlFlowPass(PR);
69   initializeWebAssemblyLateEHPreparePass(PR);
70   initializeWebAssemblyExceptionInfoPass(PR);
71   initializeWebAssemblyCFGSortPass(PR);
72   initializeWebAssemblyCFGStackifyPass(PR);
73   initializeWebAssemblyLowerBrUnlessPass(PR);
74   initializeWebAssemblyRegNumberingPass(PR);
75   initializeWebAssemblyPeepholePass(PR);
76   initializeWebAssemblyCallIndirectFixupPass(PR);
77 }
78 
79 //===----------------------------------------------------------------------===//
80 // WebAssembly Lowering public interface.
81 //===----------------------------------------------------------------------===//
82 
83 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
84   if (!RM.hasValue())
85     return Reloc::PIC_;
86   return *RM;
87 }
88 
89 /// Create an WebAssembly architecture model.
90 ///
91 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
92     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
93     const TargetOptions &Options, Optional<Reloc::Model> RM,
94     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
95     : LLVMTargetMachine(T,
96                         TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
97                                          : "e-m:e-p:32:32-i64:64-n32:64-S128",
98                         TT, CPU, FS, Options, getEffectiveRelocModel(RM),
99                         CM ? *CM : CodeModel::Large, OL),
100       TLOF(TT.isOSBinFormatELF() ?
101               static_cast<TargetLoweringObjectFile*>(
102                   new WebAssemblyTargetObjectFileELF()) :
103               static_cast<TargetLoweringObjectFile*>(
104                   new WebAssemblyTargetObjectFile())) {
105   // WebAssembly type-checks instructions, but a noreturn function with a return
106   // type that doesn't match the context will cause a check failure. So we lower
107   // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
108   // 'unreachable' instructions which is meant for that case.
109   this->Options.TrapUnreachable = true;
110 
111   // WebAssembly treats each function as an independent unit. Force
112   // -ffunction-sections, effectively, so that we can emit them independently.
113   if (!TT.isOSBinFormatELF()) {
114     this->Options.FunctionSections = true;
115     this->Options.DataSections = true;
116     this->Options.UniqueSectionNames = true;
117   }
118 
119   initAsmInfo();
120 
121   // Note that we don't use setRequiresStructuredCFG(true). It disables
122   // optimizations than we're ok with, and want, such as critical edge
123   // splitting and tail merging.
124 }
125 
126 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
127 
128 const WebAssemblySubtarget *
129 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
130   Attribute CPUAttr = F.getFnAttribute("target-cpu");
131   Attribute FSAttr = F.getFnAttribute("target-features");
132 
133   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
134                         ? CPUAttr.getValueAsString().str()
135                         : TargetCPU;
136   std::string FS = !FSAttr.hasAttribute(Attribute::None)
137                        ? FSAttr.getValueAsString().str()
138                        : TargetFS;
139 
140   auto &I = SubtargetMap[CPU + FS];
141   if (!I) {
142     // This needs to be done before we create a new subtarget since any
143     // creation will depend on the TM and the code generation flags on the
144     // function that reside in TargetOptions.
145     resetTargetOptions(F);
146     I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
147   }
148   return I.get();
149 }
150 
151 namespace {
152 class StripThreadLocal final : public ModulePass {
153   // The default thread model for wasm is single, where thread-local variables
154   // are identical to regular globals and should be treated the same. So this
155   // pass just converts all GlobalVariables to NotThreadLocal
156   static char ID;
157 
158  public:
159   StripThreadLocal() : ModulePass(ID) {}
160   bool runOnModule(Module &M) override {
161     for (auto &GV : M.globals())
162       GV.setThreadLocalMode(GlobalValue::ThreadLocalMode::NotThreadLocal);
163     return true;
164   }
165 };
166 char StripThreadLocal::ID = 0;
167 
168 /// WebAssembly Code Generator Pass Configuration Options.
169 class WebAssemblyPassConfig final : public TargetPassConfig {
170 public:
171   WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
172       : TargetPassConfig(TM, PM) {}
173 
174   WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
175     return getTM<WebAssemblyTargetMachine>();
176   }
177 
178   FunctionPass *createTargetRegisterAllocator(bool) override;
179 
180   void addIRPasses() override;
181   bool addInstSelector() override;
182   void addPostRegAlloc() override;
183   bool addGCPasses() override { return false; }
184   void addPreEmitPass() override;
185 };
186 } // end anonymous namespace
187 
188 TargetTransformInfo
189 WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) {
190   return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
191 }
192 
193 TargetPassConfig *
194 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
195   return new WebAssemblyPassConfig(*this, PM);
196 }
197 
198 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
199   return nullptr; // No reg alloc
200 }
201 
202 //===----------------------------------------------------------------------===//
203 // The following functions are called from lib/CodeGen/Passes.cpp to modify
204 // the CodeGen pass sequence.
205 //===----------------------------------------------------------------------===//
206 
207 void WebAssemblyPassConfig::addIRPasses() {
208   if (TM->Options.ThreadModel == ThreadModel::Single) {
209     // In "single" mode, atomics get lowered to non-atomics.
210     addPass(createLowerAtomicPass());
211     addPass(new StripThreadLocal());
212   } else {
213     // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
214     // control specifically what gets lowered.
215     addPass(createAtomicExpandPass());
216   }
217 
218   // Add signatures to prototype-less function declarations
219   addPass(createWebAssemblyAddMissingPrototypes());
220 
221   // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls.
222   addPass(createWebAssemblyLowerGlobalDtors());
223 
224   // Fix function bitcasts, as WebAssembly requires caller and callee signatures
225   // to match.
226   addPass(createWebAssemblyFixFunctionBitcasts());
227 
228   // Optimize "returned" function attributes.
229   if (getOptLevel() != CodeGenOpt::None)
230     addPass(createWebAssemblyOptimizeReturned());
231 
232   // If exception handling is not enabled and setjmp/longjmp handling is
233   // enabled, we lower invokes into calls and delete unreachable landingpad
234   // blocks. Lowering invokes when there is no EH support is done in
235   // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
236   // function and SjLj handling expects all invokes to be lowered before.
237   if (!EnableEmException &&
238       TM->Options.ExceptionModel == ExceptionHandling::None) {
239     addPass(createLowerInvokePass());
240     // The lower invoke pass may create unreachable code. Remove it in order not
241     // to process dead blocks in setjmp/longjmp handling.
242     addPass(createUnreachableBlockEliminationPass());
243   }
244 
245   // Handle exceptions and setjmp/longjmp if enabled.
246   if (EnableEmException || EnableEmSjLj)
247     addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
248                                                    EnableEmSjLj));
249 
250   TargetPassConfig::addIRPasses();
251 }
252 
253 bool WebAssemblyPassConfig::addInstSelector() {
254   (void)TargetPassConfig::addInstSelector();
255   addPass(
256       createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
257   // Run the argument-move pass immediately after the ScheduleDAG scheduler
258   // so that we can fix up the ARGUMENT instructions before anything else
259   // sees them in the wrong place.
260   addPass(createWebAssemblyArgumentMove());
261   // Set the p2align operands. This information is present during ISel, however
262   // it's inconvenient to collect. Collect it now, and update the immediate
263   // operands.
264   addPass(createWebAssemblySetP2AlignOperands());
265   return false;
266 }
267 
268 void WebAssemblyPassConfig::addPostRegAlloc() {
269   // TODO: The following CodeGen passes don't currently support code containing
270   // virtual registers. Consider removing their restrictions and re-enabling
271   // them.
272 
273   // These functions all require the NoVRegs property.
274   disablePass(&MachineCopyPropagationID);
275   disablePass(&PostRAMachineSinkingID);
276   disablePass(&PostRASchedulerID);
277   disablePass(&FuncletLayoutID);
278   disablePass(&StackMapLivenessID);
279   disablePass(&LiveDebugValuesID);
280   disablePass(&PatchableFunctionID);
281   disablePass(&ShrinkWrapID);
282 
283   TargetPassConfig::addPostRegAlloc();
284 }
285 
286 void WebAssemblyPassConfig::addPreEmitPass() {
287   TargetPassConfig::addPreEmitPass();
288 
289   // Now that we have a prologue and epilogue and all frame indices are
290   // rewritten, eliminate SP and FP. This allows them to be stackified,
291   // colored, and numbered with the rest of the registers.
292   addPass(createWebAssemblyReplacePhysRegs());
293 
294   // Rewrite pseudo call_indirect instructions as real instructions.
295   // This needs to run before register stackification, because we change the
296   // order of the arguments.
297   addPass(createWebAssemblyCallIndirectFixup());
298 
299   if (getOptLevel() != CodeGenOpt::None) {
300     // LiveIntervals isn't commonly run this late. Re-establish preconditions.
301     addPass(createWebAssemblyPrepareForLiveIntervals());
302 
303     // Depend on LiveIntervals and perform some optimizations on it.
304     addPass(createWebAssemblyOptimizeLiveIntervals());
305 
306     // Prepare store instructions for register stackifying.
307     addPass(createWebAssemblyStoreResults());
308 
309     // Mark registers as representing wasm's value stack. This is a key
310     // code-compression technique in WebAssembly. We run this pass (and
311     // StoreResults above) very late, so that it sees as much code as possible,
312     // including code emitted by PEI and expanded by late tail duplication.
313     addPass(createWebAssemblyRegStackify());
314 
315     // Run the register coloring pass to reduce the total number of registers.
316     // This runs after stackification so that it doesn't consider registers
317     // that become stackified.
318     addPass(createWebAssemblyRegColoring());
319   }
320 
321   // Eliminate multiple-entry loops. Do this before inserting explicit get_local
322   // and set_local operators because we create a new variable that we want
323   // converted into a local.
324   addPass(createWebAssemblyFixIrreducibleControlFlow());
325 
326   // Insert explicit get_local and set_local operators.
327   addPass(createWebAssemblyExplicitLocals());
328 
329   // Do various transformations for exception handling
330   addPass(createWebAssemblyLateEHPrepare());
331 
332   // Sort the blocks of the CFG into topological order, a prerequisite for
333   // BLOCK and LOOP markers.
334   addPass(createWebAssemblyCFGSort());
335 
336   // Insert BLOCK and LOOP markers.
337   addPass(createWebAssemblyCFGStackify());
338 
339   // Lower br_unless into br_if.
340   addPass(createWebAssemblyLowerBrUnless());
341 
342   // Perform the very last peephole optimizations on the code.
343   if (getOptLevel() != CodeGenOpt::None)
344     addPass(createWebAssemblyPeephole());
345 
346   // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
347   addPass(createWebAssemblyRegNumbering());
348 }
349