1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssembly.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyTargetMachine.h"
18 #include "WebAssemblyTargetObjectFile.h"
19 #include "WebAssemblyTargetTransformInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Transforms/Scalar.h"
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "wasm"
31 
32 // Emscripten's asm.js-style exception handling
33 static cl::opt<bool> EnableEmException(
34     "enable-emscripten-cxx-exceptions",
35     cl::desc("WebAssembly Emscripten-style exception handling"),
36     cl::init(false));
37 
38 // Emscripten's asm.js-style setjmp/longjmp handling
39 static cl::opt<bool> EnableEmSjLj(
40     "enable-emscripten-sjlj",
41     cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
42     cl::init(false));
43 
44 extern "C" void LLVMInitializeWebAssemblyTarget() {
45   // Register the target.
46   RegisterTargetMachine<WebAssemblyTargetMachine> X(
47       getTheWebAssemblyTarget32());
48   RegisterTargetMachine<WebAssemblyTargetMachine> Y(
49       getTheWebAssemblyTarget64());
50 
51   // Register exception handling pass to opt
52   initializeWebAssemblyLowerEmscriptenEHSjLjPass(
53       *PassRegistry::getPassRegistry());
54 }
55 
56 //===----------------------------------------------------------------------===//
57 // WebAssembly Lowering public interface.
58 //===----------------------------------------------------------------------===//
59 
60 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
61   if (!RM.hasValue())
62     return Reloc::PIC_;
63   return *RM;
64 }
65 
66 /// Create an WebAssembly architecture model.
67 ///
68 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
69     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
70     const TargetOptions &Options, Optional<Reloc::Model> RM,
71     CodeModel::Model CM, CodeGenOpt::Level OL)
72     : LLVMTargetMachine(T,
73                         TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
74                                          : "e-m:e-p:32:32-i64:64-n32:64-S128",
75                         TT, CPU, FS, Options, getEffectiveRelocModel(RM),
76                         CM, OL),
77       TLOF(TT.isOSBinFormatELF() ?
78               static_cast<TargetLoweringObjectFile*>(
79                   new WebAssemblyTargetObjectFileELF()) :
80               static_cast<TargetLoweringObjectFile*>(
81                   new WebAssemblyTargetObjectFile())) {
82   // WebAssembly type-checks instructions, but a noreturn function with a return
83   // type that doesn't match the context will cause a check failure. So we lower
84   // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
85   // 'unreachable' instructions which is meant for that case.
86   this->Options.TrapUnreachable = true;
87 
88   initAsmInfo();
89 
90   // Note that we don't use setRequiresStructuredCFG(true). It disables
91   // optimizations than we're ok with, and want, such as critical edge
92   // splitting and tail merging.
93 }
94 
95 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
96 
97 const WebAssemblySubtarget *
98 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
99   Attribute CPUAttr = F.getFnAttribute("target-cpu");
100   Attribute FSAttr = F.getFnAttribute("target-features");
101 
102   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
103                         ? CPUAttr.getValueAsString().str()
104                         : TargetCPU;
105   std::string FS = !FSAttr.hasAttribute(Attribute::None)
106                        ? FSAttr.getValueAsString().str()
107                        : TargetFS;
108 
109   auto &I = SubtargetMap[CPU + FS];
110   if (!I) {
111     // This needs to be done before we create a new subtarget since any
112     // creation will depend on the TM and the code generation flags on the
113     // function that reside in TargetOptions.
114     resetTargetOptions(F);
115     I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
116   }
117   return I.get();
118 }
119 
120 namespace {
121 /// WebAssembly Code Generator Pass Configuration Options.
122 class WebAssemblyPassConfig final : public TargetPassConfig {
123 public:
124   WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
125       : TargetPassConfig(TM, PM) {}
126 
127   WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
128     return getTM<WebAssemblyTargetMachine>();
129   }
130 
131   FunctionPass *createTargetRegisterAllocator(bool) override;
132 
133   void addIRPasses() override;
134   bool addInstSelector() override;
135   void addPostRegAlloc() override;
136   bool addGCPasses() override { return false; }
137   void addPreEmitPass() override;
138 };
139 } // end anonymous namespace
140 
141 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
142   return TargetIRAnalysis([this](const Function &F) {
143     return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
144   });
145 }
146 
147 TargetPassConfig *
148 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
149   return new WebAssemblyPassConfig(this, PM);
150 }
151 
152 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
153   return nullptr; // No reg alloc
154 }
155 
156 //===----------------------------------------------------------------------===//
157 // The following functions are called from lib/CodeGen/Passes.cpp to modify
158 // the CodeGen pass sequence.
159 //===----------------------------------------------------------------------===//
160 
161 void WebAssemblyPassConfig::addIRPasses() {
162   if (TM->Options.ThreadModel == ThreadModel::Single)
163     // In "single" mode, atomics get lowered to non-atomics.
164     addPass(createLowerAtomicPass());
165   else
166     // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
167     // control specifically what gets lowered.
168     addPass(createAtomicExpandPass(TM));
169 
170   // Fix function bitcasts, as WebAssembly requires caller and callee signatures
171   // to match.
172   addPass(createWebAssemblyFixFunctionBitcasts());
173 
174   // Optimize "returned" function attributes.
175   if (getOptLevel() != CodeGenOpt::None)
176     addPass(createWebAssemblyOptimizeReturned());
177 
178   // If exception handling is not enabled and setjmp/longjmp handling is
179   // enabled, we lower invokes into calls and delete unreachable landingpad
180   // blocks. Lowering invokes when there is no EH support is done in
181   // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
182   // function and SjLj handling expects all invokes to be lowered before.
183   if (!EnableEmException) {
184     addPass(createLowerInvokePass());
185     // The lower invoke pass may create unreachable code. Remove it in order not
186     // to process dead blocks in setjmp/longjmp handling.
187     addPass(createUnreachableBlockEliminationPass());
188   }
189 
190   // Handle exceptions and setjmp/longjmp if enabled.
191   if (EnableEmException || EnableEmSjLj)
192     addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
193                                                    EnableEmSjLj));
194 
195   TargetPassConfig::addIRPasses();
196 }
197 
198 bool WebAssemblyPassConfig::addInstSelector() {
199   (void)TargetPassConfig::addInstSelector();
200   addPass(
201       createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
202   // Run the argument-move pass immediately after the ScheduleDAG scheduler
203   // so that we can fix up the ARGUMENT instructions before anything else
204   // sees them in the wrong place.
205   addPass(createWebAssemblyArgumentMove());
206   // Set the p2align operands. This information is present during ISel, however
207   // it's inconvenient to collect. Collect it now, and update the immediate
208   // operands.
209   addPass(createWebAssemblySetP2AlignOperands());
210   return false;
211 }
212 
213 void WebAssemblyPassConfig::addPostRegAlloc() {
214   // TODO: The following CodeGen passes don't currently support code containing
215   // virtual registers. Consider removing their restrictions and re-enabling
216   // them.
217 
218   // Has no asserts of its own, but was not written to handle virtual regs.
219   disablePass(&ShrinkWrapID);
220 
221   // These functions all require the NoVRegs property.
222   disablePass(&MachineCopyPropagationID);
223   disablePass(&PostRASchedulerID);
224   disablePass(&FuncletLayoutID);
225   disablePass(&StackMapLivenessID);
226   disablePass(&LiveDebugValuesID);
227   disablePass(&PatchableFunctionID);
228 
229   TargetPassConfig::addPostRegAlloc();
230 }
231 
232 void WebAssemblyPassConfig::addPreEmitPass() {
233   TargetPassConfig::addPreEmitPass();
234 
235   // Now that we have a prologue and epilogue and all frame indices are
236   // rewritten, eliminate SP and FP. This allows them to be stackified,
237   // colored, and numbered with the rest of the registers.
238   addPass(createWebAssemblyReplacePhysRegs());
239 
240   // Rewrite pseudo call_indirect instructions as real instructions.
241   // This needs to run before register stackification, because we change the
242   // order of the arguments.
243   addPass(createWebAssemblyCallIndirectFixup());
244 
245   if (getOptLevel() != CodeGenOpt::None) {
246     // LiveIntervals isn't commonly run this late. Re-establish preconditions.
247     addPass(createWebAssemblyPrepareForLiveIntervals());
248 
249     // Depend on LiveIntervals and perform some optimizations on it.
250     addPass(createWebAssemblyOptimizeLiveIntervals());
251 
252     // Prepare store instructions for register stackifying.
253     addPass(createWebAssemblyStoreResults());
254 
255     // Mark registers as representing wasm's value stack. This is a key
256     // code-compression technique in WebAssembly. We run this pass (and
257     // StoreResults above) very late, so that it sees as much code as possible,
258     // including code emitted by PEI and expanded by late tail duplication.
259     addPass(createWebAssemblyRegStackify());
260 
261     // Run the register coloring pass to reduce the total number of registers.
262     // This runs after stackification so that it doesn't consider registers
263     // that become stackified.
264     addPass(createWebAssemblyRegColoring());
265   }
266 
267   // Insert explicit get_local and set_local operators.
268   addPass(createWebAssemblyExplicitLocals());
269 
270   // Eliminate multiple-entry loops.
271   addPass(createWebAssemblyFixIrreducibleControlFlow());
272 
273   // Put the CFG in structured form; insert BLOCK and LOOP markers.
274   addPass(createWebAssemblyCFGStackify());
275 
276   // Lower br_unless into br_if.
277   addPass(createWebAssemblyLowerBrUnless());
278 
279   // Perform the very last peephole optimizations on the code.
280   if (getOptLevel() != CodeGenOpt::None)
281     addPass(createWebAssemblyPeephole());
282 
283   // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
284   addPass(createWebAssemblyRegNumbering());
285 }
286