1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssembly.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyTargetMachine.h"
18 #include "WebAssemblyTargetObjectFile.h"
19 #include "WebAssemblyTargetTransformInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Transforms/Scalar.h"
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "wasm"
31 
32 // Emscripten's asm.js-style exception handling
33 static cl::opt<bool> EnableEmException(
34     "enable-emscripten-cxx-exceptions",
35     cl::desc("WebAssembly Emscripten-style exception handling"),
36     cl::init(false));
37 
38 // Emscripten's asm.js-style setjmp/longjmp handling
39 static cl::opt<bool> EnableEmSjLj(
40     "enable-emscripten-sjlj",
41     cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
42     cl::init(false));
43 
44 static cl::opt<bool> ExplicitLocals(
45     "wasm-explicit-locals",
46     cl::desc("WebAssembly with explicit get_local/set_local"),
47     cl::init(false));
48 
49 extern "C" void LLVMInitializeWebAssemblyTarget() {
50   // Register the target.
51   RegisterTargetMachine<WebAssemblyTargetMachine> X(
52       getTheWebAssemblyTarget32());
53   RegisterTargetMachine<WebAssemblyTargetMachine> Y(
54       getTheWebAssemblyTarget64());
55 
56   // Register exception handling pass to opt
57   initializeWebAssemblyLowerEmscriptenEHSjLjPass(
58       *PassRegistry::getPassRegistry());
59 }
60 
61 //===----------------------------------------------------------------------===//
62 // WebAssembly Lowering public interface.
63 //===----------------------------------------------------------------------===//
64 
65 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
66   if (!RM.hasValue())
67     return Reloc::PIC_;
68   return *RM;
69 }
70 
71 /// Create an WebAssembly architecture model.
72 ///
73 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
74     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
75     const TargetOptions &Options, Optional<Reloc::Model> RM,
76     CodeModel::Model CM, CodeGenOpt::Level OL)
77     : LLVMTargetMachine(T,
78                         TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
79                                          : "e-m:e-p:32:32-i64:64-n32:64-S128",
80                         TT, CPU, FS, Options, getEffectiveRelocModel(RM),
81                         CM, OL),
82       TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
83   // WebAssembly type-checks instructions, but a noreturn function with a return
84   // type that doesn't match the context will cause a check failure. So we lower
85   // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
86   // 'unreachable' instructions which is meant for that case.
87   this->Options.TrapUnreachable = true;
88 
89   initAsmInfo();
90 
91   // Note that we don't use setRequiresStructuredCFG(true). It disables
92   // optimizations than we're ok with, and want, such as critical edge
93   // splitting and tail merging.
94 }
95 
96 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
97 
98 const WebAssemblySubtarget *
99 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
100   Attribute CPUAttr = F.getFnAttribute("target-cpu");
101   Attribute FSAttr = F.getFnAttribute("target-features");
102 
103   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
104                         ? CPUAttr.getValueAsString().str()
105                         : TargetCPU;
106   std::string FS = !FSAttr.hasAttribute(Attribute::None)
107                        ? FSAttr.getValueAsString().str()
108                        : TargetFS;
109 
110   auto &I = SubtargetMap[CPU + FS];
111   if (!I) {
112     // This needs to be done before we create a new subtarget since any
113     // creation will depend on the TM and the code generation flags on the
114     // function that reside in TargetOptions.
115     resetTargetOptions(F);
116     I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
117   }
118   return I.get();
119 }
120 
121 namespace {
122 /// WebAssembly Code Generator Pass Configuration Options.
123 class WebAssemblyPassConfig final : public TargetPassConfig {
124 public:
125   WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
126       : TargetPassConfig(TM, PM) {}
127 
128   WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
129     return getTM<WebAssemblyTargetMachine>();
130   }
131 
132   FunctionPass *createTargetRegisterAllocator(bool) override;
133 
134   void addIRPasses() override;
135   bool addInstSelector() override;
136   void addPostRegAlloc() override;
137   bool addGCPasses() override { return false; }
138   void addPreEmitPass() override;
139 };
140 } // end anonymous namespace
141 
142 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
143   return TargetIRAnalysis([this](const Function &F) {
144     return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
145   });
146 }
147 
148 TargetPassConfig *
149 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
150   return new WebAssemblyPassConfig(this, PM);
151 }
152 
153 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
154   return nullptr; // No reg alloc
155 }
156 
157 //===----------------------------------------------------------------------===//
158 // The following functions are called from lib/CodeGen/Passes.cpp to modify
159 // the CodeGen pass sequence.
160 //===----------------------------------------------------------------------===//
161 
162 void WebAssemblyPassConfig::addIRPasses() {
163   if (TM->Options.ThreadModel == ThreadModel::Single)
164     // In "single" mode, atomics get lowered to non-atomics.
165     addPass(createLowerAtomicPass());
166   else
167     // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
168     // control specifically what gets lowered.
169     addPass(createAtomicExpandPass(TM));
170 
171   // Optimize "returned" function attributes.
172   if (getOptLevel() != CodeGenOpt::None)
173     addPass(createWebAssemblyOptimizeReturned());
174 
175   // If exception handling is not enabled and setjmp/longjmp handling is
176   // enabled, we lower invokes into calls and delete unreachable landingpad
177   // blocks. Lowering invokes when there is no EH support is done in
178   // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
179   // function and SjLj handling expects all invokes to be lowered before.
180   if (!EnableEmException) {
181     addPass(createLowerInvokePass());
182     // The lower invoke pass may create unreachable code. Remove it in order not
183     // to process dead blocks in setjmp/longjmp handling.
184     addPass(createUnreachableBlockEliminationPass());
185   }
186 
187   // Handle exceptions and setjmp/longjmp if enabled.
188   if (EnableEmException || EnableEmSjLj)
189     addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
190                                                    EnableEmSjLj));
191 
192   TargetPassConfig::addIRPasses();
193 }
194 
195 bool WebAssemblyPassConfig::addInstSelector() {
196   (void)TargetPassConfig::addInstSelector();
197   addPass(
198       createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
199   // Run the argument-move pass immediately after the ScheduleDAG scheduler
200   // so that we can fix up the ARGUMENT instructions before anything else
201   // sees them in the wrong place.
202   addPass(createWebAssemblyArgumentMove());
203   // Set the p2align operands. This information is present during ISel, however
204   // it's inconvenient to collect. Collect it now, and update the immediate
205   // operands.
206   addPass(createWebAssemblySetP2AlignOperands());
207   return false;
208 }
209 
210 void WebAssemblyPassConfig::addPostRegAlloc() {
211   // TODO: The following CodeGen passes don't currently support code containing
212   // virtual registers. Consider removing their restrictions and re-enabling
213   // them.
214 
215   // Has no asserts of its own, but was not written to handle virtual regs.
216   disablePass(&ShrinkWrapID);
217 
218   // These functions all require the NoVRegs property.
219   disablePass(&MachineCopyPropagationID);
220   disablePass(&PostRASchedulerID);
221   disablePass(&FuncletLayoutID);
222   disablePass(&StackMapLivenessID);
223   disablePass(&LiveDebugValuesID);
224   disablePass(&PatchableFunctionID);
225 
226   TargetPassConfig::addPostRegAlloc();
227 }
228 
229 void WebAssemblyPassConfig::addPreEmitPass() {
230   TargetPassConfig::addPreEmitPass();
231 
232   // Now that we have a prologue and epilogue and all frame indices are
233   // rewritten, eliminate SP and FP. This allows them to be stackified,
234   // colored, and numbered with the rest of the registers.
235   addPass(createWebAssemblyReplacePhysRegs());
236 
237   // Rewrite pseudo call_indirect instructions as real instructions.
238   // This needs to run before register stackification, because we change the
239   // order of the arguments.
240   addPass(createWebAssemblyCallIndirectFixup());
241 
242   if (getOptLevel() != CodeGenOpt::None) {
243     // LiveIntervals isn't commonly run this late. Re-establish preconditions.
244     addPass(createWebAssemblyPrepareForLiveIntervals());
245 
246     // Depend on LiveIntervals and perform some optimizations on it.
247     addPass(createWebAssemblyOptimizeLiveIntervals());
248 
249     // Prepare store instructions for register stackifying.
250     addPass(createWebAssemblyStoreResults());
251 
252     // Mark registers as representing wasm's value stack. This is a key
253     // code-compression technique in WebAssembly. We run this pass (and
254     // StoreResults above) very late, so that it sees as much code as possible,
255     // including code emitted by PEI and expanded by late tail duplication.
256     addPass(createWebAssemblyRegStackify());
257 
258     // Run the register coloring pass to reduce the total number of registers.
259     // This runs after stackification so that it doesn't consider registers
260     // that become stackified.
261     addPass(createWebAssemblyRegColoring());
262   }
263 
264   // Insert explicit get_local and set_local operators.
265   if (ExplicitLocals)
266     addPass(createWebAssemblyExplicitLocals());
267 
268   // Eliminate multiple-entry loops.
269   addPass(createWebAssemblyFixIrreducibleControlFlow());
270 
271   // Put the CFG in structured form; insert BLOCK and LOOP markers.
272   addPass(createWebAssemblyCFGStackify());
273 
274   // Lower br_unless into br_if.
275   addPass(createWebAssemblyLowerBrUnless());
276 
277   // Perform the very last peephole optimizations on the code.
278   if (getOptLevel() != CodeGenOpt::None)
279     addPass(createWebAssemblyPeephole());
280 
281   // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
282   addPass(createWebAssemblyRegNumbering());
283 }
284