110e730a2SDan Gohman //===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
210e730a2SDan Gohman //
32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information.
52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
610e730a2SDan Gohman //
710e730a2SDan Gohman //===----------------------------------------------------------------------===//
810e730a2SDan Gohman ///
910e730a2SDan Gohman /// \file
105f8f34e4SAdrian Prantl /// This file implements the WebAssembly-specific subclass of
1110e730a2SDan Gohman /// TargetSubtarget.
1210e730a2SDan Gohman ///
1310e730a2SDan Gohman //===----------------------------------------------------------------------===//
1410e730a2SDan Gohman
1510e730a2SDan Gohman #include "WebAssemblySubtarget.h"
16ec977b07SDan Gohman #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17ec977b07SDan Gohman #include "WebAssemblyInstrInfo.h"
1889b57061SReid Kleckner #include "llvm/MC/TargetRegistry.h"
1910e730a2SDan Gohman using namespace llvm;
2010e730a2SDan Gohman
2103855df1SJF Bastien #define DEBUG_TYPE "wasm-subtarget"
2210e730a2SDan Gohman
2310e730a2SDan Gohman #define GET_SUBTARGETINFO_CTOR
2410e730a2SDan Gohman #define GET_SUBTARGETINFO_TARGET_DESC
2510e730a2SDan Gohman #include "WebAssemblyGenSubtargetInfo.inc"
2610e730a2SDan Gohman
2710e730a2SDan Gohman WebAssemblySubtarget &
initializeSubtargetDependencies(StringRef CPU,StringRef FS)2816206ee0SSam Clegg WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
2916206ee0SSam Clegg StringRef FS) {
3010e730a2SDan Gohman // Determine default and user-specified characteristics
3116206ee0SSam Clegg LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
3210e730a2SDan Gohman
3316206ee0SSam Clegg if (CPU.empty())
3416206ee0SSam Clegg CPU = "generic";
3510e730a2SDan Gohman
36c7a0b268SCraig Topper ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
3710e730a2SDan Gohman return *this;
3810e730a2SDan Gohman }
3910e730a2SDan Gohman
WebAssemblySubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const TargetMachine & TM)4010e730a2SDan Gohman WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
4110e730a2SDan Gohman const std::string &CPU,
4210e730a2SDan Gohman const std::string &FS,
4310e730a2SDan Gohman const TargetMachine &TM)
44c7a0b268SCraig Topper : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
45*f3a344d2SKazu Hirata TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
46e5947760SKazu Hirata TLInfo(TM, *this) {}
4710e730a2SDan Gohman
enableAtomicExpand() const483f34e1b8SThomas Lively bool WebAssemblySubtarget::enableAtomicExpand() const {
493f34e1b8SThomas Lively // If atomics are disabled, atomic ops are lowered instead of expanded
503f34e1b8SThomas Lively return hasAtomics();
513f34e1b8SThomas Lively }
523f34e1b8SThomas Lively
enableMachineScheduler() const53e045f67fSDan Gohman bool WebAssemblySubtarget::enableMachineScheduler() const {
54e045f67fSDan Gohman // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
55e045f67fSDan Gohman // enableMachineSchedDefaultSched overridden, it appears to have an overall
56e045f67fSDan Gohman // negative effect for the kinds of register optimizations we're doing.
57e045f67fSDan Gohman return false;
58e045f67fSDan Gohman }
59e045f67fSDan Gohman
useAA() const607615e469SDan Gohman bool WebAssemblySubtarget::useAA() const { return true; }
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