1 //===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file contains the WebAssembly implementation of the
12 /// TargetRegisterInfo class.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #include "WebAssemblyRegisterInfo.h"
17 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18 #include "WebAssemblyFrameLowering.h"
19 #include "WebAssemblyInstrInfo.h"
20 #include "WebAssemblyMachineFunctionInfo.h"
21 #include "WebAssemblySubtarget.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetOptions.h"
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "wasm-reg-info"
32 
33 #define GET_REGINFO_TARGET_DESC
34 #include "WebAssemblyGenRegisterInfo.inc"
35 
36 WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT)
37     : WebAssemblyGenRegisterInfo(0), TT(TT) {}
38 
39 const MCPhysReg *
40 WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
41   static const MCPhysReg CalleeSavedRegs[] = {0};
42   return CalleeSavedRegs;
43 }
44 
45 BitVector
46 WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
47   BitVector Reserved(getNumRegs());
48   for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
49                    WebAssembly::FP64})
50     Reserved.set(Reg);
51   return Reserved;
52 }
53 
54 void WebAssemblyRegisterInfo::eliminateFrameIndex(
55     MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
56     RegScavenger * /*RS*/) const {
57   assert(SPAdj == 0);
58   MachineInstr &MI = *II;
59 
60   MachineBasicBlock &MBB = *MI.getParent();
61   MachineFunction &MF = *MBB.getParent();
62   MachineRegisterInfo &MRI = MF.getRegInfo();
63   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
64   const MachineFrameInfo &MFI = MF.getFrameInfo();
65   int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
66 
67   assert(MFI.getObjectSize(FrameIndex) != 0 &&
68          "We assume that variable-sized objects have already been lowered, "
69          "and don't use FrameIndex operands.");
70   unsigned FrameRegister = getFrameRegister(MF);
71 
72   // If this is the address operand of a load or store, make it relative to SP
73   // and fold the frame offset directly in.
74   if (MI.mayLoadOrStore() && FIOperandNum == WebAssembly::MemOpAddressOperandNo) {
75     assert(FrameOffset >= 0 && MI.getOperand(1).getImm() >= 0);
76     int64_t Offset = MI.getOperand(1).getImm() + FrameOffset;
77 
78     if (static_cast<uint64_t>(Offset) <= std::numeric_limits<uint32_t>::max()) {
79       MI.getOperand(FIOperandNum - 1).setImm(Offset);
80       MI.getOperand(FIOperandNum)
81           .ChangeToRegister(FrameRegister, /*IsDef=*/false);
82       return;
83     }
84   }
85 
86   // If this is an address being added to a constant, fold the frame offset
87   // into the constant.
88   if (MI.getOpcode() == WebAssembly::ADD_I32) {
89     MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
90     if (OtherMO.isReg()) {
91       unsigned OtherMOReg = OtherMO.getReg();
92       if (TargetRegisterInfo::isVirtualRegister(OtherMOReg)) {
93         MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
94         // TODO: For now we just opportunistically do this in the case where
95         // the CONST_I32 happens to have exactly one def and one use. We
96         // should generalize this to optimize in more cases.
97         if (Def && Def->getOpcode() == WebAssembly::CONST_I32 &&
98             MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
99           MachineOperand &ImmMO = Def->getOperand(1);
100           ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset));
101           MI.getOperand(FIOperandNum)
102               .ChangeToRegister(FrameRegister, /*IsDef=*/false);
103           return;
104         }
105       }
106     }
107   }
108 
109   // Otherwise create an i32.add SP, offset and make it the operand.
110   const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
111 
112   unsigned FIRegOperand = FrameRegister;
113   if (FrameOffset) {
114     // Create i32.add SP, offset and make it the operand.
115     const TargetRegisterClass *PtrRC =
116         MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
117     unsigned OffsetOp = MRI.createVirtualRegister(PtrRC);
118     BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
119             OffsetOp)
120         .addImm(FrameOffset);
121     FIRegOperand = MRI.createVirtualRegister(PtrRC);
122     BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
123             FIRegOperand)
124         .addReg(FrameRegister)
125         .addReg(OffsetOp);
126   }
127   MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*IsDef=*/false);
128 }
129 
130 unsigned
131 WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
132   static const unsigned Regs[2][2] = {
133       /*            !isArch64Bit       isArch64Bit      */
134       /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
135       /*  hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
136   const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
137   return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
138 }
139 
140 const TargetRegisterClass *
141 WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF,
142                                             unsigned Kind) const {
143   assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
144   if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
145     return &WebAssembly::I64RegClass;
146   return &WebAssembly::I32RegClass;
147 }
148