1 //===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file contains the WebAssembly implementation of the 11 /// TargetRegisterInfo class. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssemblyRegisterInfo.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyFrameLowering.h" 18 #include "WebAssemblyInstrInfo.h" 19 #include "WebAssemblyMachineFunctionInfo.h" 20 #include "WebAssemblySubtarget.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/TargetFrameLowering.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include "llvm/Target/TargetOptions.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm-reg-info" 31 32 #define GET_REGINFO_TARGET_DESC 33 #include "WebAssemblyGenRegisterInfo.inc" 34 35 WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT) 36 : WebAssemblyGenRegisterInfo(0), TT(TT) {} 37 38 const MCPhysReg * 39 WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const { 40 static const MCPhysReg CalleeSavedRegs[] = {0}; 41 return CalleeSavedRegs; 42 } 43 44 BitVector 45 WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const { 46 BitVector Reserved(getNumRegs()); 47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, 48 WebAssembly::FP64}) 49 Reserved.set(Reg); 50 return Reserved; 51 } 52 53 void WebAssemblyRegisterInfo::eliminateFrameIndex( 54 MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, 55 RegScavenger * /*RS*/) const { 56 assert(SPAdj == 0); 57 MachineInstr &MI = *II; 58 59 MachineBasicBlock &MBB = *MI.getParent(); 60 MachineFunction &MF = *MBB.getParent(); 61 MachineRegisterInfo &MRI = MF.getRegInfo(); 62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 63 const MachineFrameInfo &MFI = MF.getFrameInfo(); 64 int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex); 65 66 assert(MFI.getObjectSize(FrameIndex) != 0 && 67 "We assume that variable-sized objects have already been lowered, " 68 "and don't use FrameIndex operands."); 69 unsigned FrameRegister = getFrameRegister(MF); 70 71 // If this is the address operand of a load or store, make it relative to SP 72 // and fold the frame offset directly in. 73 if ((MI.mayLoad() && FIOperandNum == WebAssembly::LoadAddressOperandNo) || 74 (MI.mayStore() && FIOperandNum == WebAssembly::StoreAddressOperandNo)) { 75 assert(FrameOffset >= 0 && MI.getOperand(FIOperandNum - 1).getImm() >= 0); 76 int64_t Offset = MI.getOperand(FIOperandNum - 1).getImm() + FrameOffset; 77 78 if (static_cast<uint64_t>(Offset) <= std::numeric_limits<uint32_t>::max()) { 79 MI.getOperand(FIOperandNum - 1).setImm(Offset); 80 MI.getOperand(FIOperandNum) 81 .ChangeToRegister(FrameRegister, /*IsDef=*/false); 82 return; 83 } 84 } 85 86 // If this is an address being added to a constant, fold the frame offset 87 // into the constant. 88 if (MI.getOpcode() == WebAssembly::ADD_I32) { 89 MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum); 90 if (OtherMO.isReg()) { 91 unsigned OtherMOReg = OtherMO.getReg(); 92 if (TargetRegisterInfo::isVirtualRegister(OtherMOReg)) { 93 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg); 94 // TODO: For now we just opportunistically do this in the case where 95 // the CONST_I32 happens to have exactly one def and one use. We 96 // should generalize this to optimize in more cases. 97 if (Def && Def->getOpcode() == WebAssembly::CONST_I32 && 98 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) { 99 MachineOperand &ImmMO = Def->getOperand(1); 100 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset)); 101 MI.getOperand(FIOperandNum) 102 .ChangeToRegister(FrameRegister, /*IsDef=*/false); 103 return; 104 } 105 } 106 } 107 } 108 109 // Otherwise create an i32.add SP, offset and make it the operand. 110 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); 111 112 unsigned FIRegOperand = FrameRegister; 113 if (FrameOffset) { 114 // Create i32.add SP, offset and make it the operand. 115 const TargetRegisterClass *PtrRC = 116 MRI.getTargetRegisterInfo()->getPointerRegClass(MF); 117 unsigned OffsetOp = MRI.createVirtualRegister(PtrRC); 118 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32), 119 OffsetOp) 120 .addImm(FrameOffset); 121 FIRegOperand = MRI.createVirtualRegister(PtrRC); 122 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32), 123 FIRegOperand) 124 .addReg(FrameRegister) 125 .addReg(OffsetOp); 126 } 127 MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*IsDef=*/false); 128 } 129 130 unsigned 131 WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 132 static const unsigned Regs[2][2] = { 133 /* !isArch64Bit isArch64Bit */ 134 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, 135 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; 136 const WebAssemblyFrameLowering *TFI = getFrameLowering(MF); 137 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()]; 138 } 139 140 const TargetRegisterClass * 141 WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF, 142 unsigned Kind) const { 143 assert(Kind == 0 && "Only one kind of pointer on WebAssembly"); 144 if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64()) 145 return &WebAssembly::I64RegClass; 146 return &WebAssembly::I32RegClass; 147 } 148