1 //===-- WebAssemblyRegStackify.cpp - Register Stackification --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements a register stacking pass.
12 ///
13 /// This pass reorders instructions to put register uses and defs in an order
14 /// such that they form single-use expression trees. Registers fitting this form
15 /// are then marked as "stackified", meaning references to them are replaced by
16 /// "push" and "pop" from the stack.
17 ///
18 /// This is primarily a code size optimiation, since temporary values on the
19 /// expression don't need to be named.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #include "WebAssembly.h"
24 #include "WebAssemblyMachineFunctionInfo.h"
25 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "wasm-reg-stackify"
33 
34 namespace {
35 class WebAssemblyRegStackify final : public MachineFunctionPass {
36   const char *getPassName() const override {
37     return "WebAssembly Register Stackify";
38   }
39 
40   void getAnalysisUsage(AnalysisUsage &AU) const override {
41     AU.setPreservesCFG();
42     AU.addPreserved<MachineBlockFrequencyInfo>();
43     AU.addPreservedID(MachineDominatorsID);
44     MachineFunctionPass::getAnalysisUsage(AU);
45   }
46 
47   bool runOnMachineFunction(MachineFunction &MF) override;
48 
49 public:
50   static char ID; // Pass identification, replacement for typeid
51   WebAssemblyRegStackify() : MachineFunctionPass(ID) {}
52 };
53 } // end anonymous namespace
54 
55 char WebAssemblyRegStackify::ID = 0;
56 FunctionPass *llvm::createWebAssemblyRegStackify() {
57   return new WebAssemblyRegStackify();
58 }
59 
60 bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
61   DEBUG(dbgs() << "********** Register Stackifying **********\n"
62                   "********** Function: "
63                << MF.getName() << '\n');
64 
65   bool Changed = false;
66   MachineRegisterInfo &MRI = MF.getRegInfo();
67   WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
68 
69   // Walk the instructions from the bottom up. Currently we don't look past
70   // block boundaries, and the blocks aren't ordered so the block visitation
71   // order isn't significant, but we may want to change this in the future.
72   for (MachineBasicBlock &MBB : MF) {
73     for (MachineInstr &MI : reverse(MBB)) {
74       MachineInstr *Insert = &MI;
75 
76       // Don't nest anything inside a phi.
77       if (Insert->getOpcode() == TargetOpcode::PHI)
78         break;
79 
80       // Iterate through the inputs in reverse order, since we'll be pulling
81       // operands off the stack in FIFO order.
82       for (MachineOperand &Op : reverse(Insert->uses())) {
83         // We're only interested in explicit virtual register operands.
84         if (!Op.isReg() || Op.isImplicit())
85           continue;
86 
87         unsigned Reg = Op.getReg();
88         if (!TargetRegisterInfo::isVirtualRegister(Reg))
89           continue;
90 
91         // Only consider registers with a single definition.
92         // TODO: Eventually we may relax this, to stackify phi transfers.
93         MachineInstr *Def = MRI.getVRegDef(Reg);
94         if (!Def)
95           continue;
96 
97         // There's no use in nesting implicit defs inside anything.
98         if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF)
99           continue;
100 
101         // Single-use expression trees require defs that have one use, or that
102         // they be trivially clonable.
103         // TODO: Eventually we'll relax this, to take advantage of set_local
104         // returning its result.
105         bool OneUse = MRI.hasOneUse(Reg);
106         if (!OneUse && !Def->isMoveImmediate())
107           continue;
108 
109         // For now, be conservative and don't look across block boundaries,
110         // unless we have something trivially clonable.
111         // TODO: Be more aggressive.
112         if (Def->getParent() != &MBB && !Def->isMoveImmediate())
113           continue;
114 
115         // For now, be simple and don't reorder loads, stores, or side effects.
116         // TODO: Be more aggressive.
117         if ((Def->mayLoad() || Def->mayStore() ||
118              Def->hasUnmodeledSideEffects()))
119           continue;
120 
121         Changed = true;
122         if (OneUse) {
123           // Move the def down and nest it in the current instruction.
124           MBB.insert(MachineBasicBlock::instr_iterator(Insert),
125                      Def->removeFromParent());
126           MFI.stackifyVReg(Reg);
127           Insert = Def;
128         } else {
129           // Clone the def down and nest it in the current instruction.
130           MachineInstr *Clone = MF.CloneMachineInstr(Def);
131           unsigned OldReg = Def->getOperand(0).getReg();
132           unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
133           assert(Op.getReg() == OldReg);
134           assert(Clone->getOperand(0).getReg() == OldReg);
135           Op.setReg(NewReg);
136           Clone->getOperand(0).setReg(NewReg);
137           MBB.insert(MachineBasicBlock::instr_iterator(Insert), Clone);
138           MFI.stackifyVReg(Reg);
139           Insert = Clone;
140         }
141       }
142     }
143   }
144 
145   return Changed;
146 }
147