1 //===-- WebAssemblyRegStackify.cpp - Register Stackification --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements a register stacking pass.
12 ///
13 /// This pass reorders instructions to put register uses and defs in an order
14 /// such that they form single-use expression trees. Registers fitting this form
15 /// are then marked as "stackified", meaning references to them are replaced by
16 /// "push" and "pop" from the stack.
17 ///
18 /// This is primarily a code size optimiation, since temporary values on the
19 /// expression don't need to be named.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #include "WebAssembly.h"
24 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" // for WebAssembly::ARGUMENT_*
25 #include "WebAssemblyMachineFunctionInfo.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "wasm-reg-stackify"
35 
36 namespace {
37 class WebAssemblyRegStackify final : public MachineFunctionPass {
38   const char *getPassName() const override {
39     return "WebAssembly Register Stackify";
40   }
41 
42   void getAnalysisUsage(AnalysisUsage &AU) const override {
43     AU.setPreservesCFG();
44     AU.addRequired<AAResultsWrapperPass>();
45     AU.addPreserved<MachineBlockFrequencyInfo>();
46     AU.addPreservedID(MachineDominatorsID);
47     MachineFunctionPass::getAnalysisUsage(AU);
48   }
49 
50   bool runOnMachineFunction(MachineFunction &MF) override;
51 
52 public:
53   static char ID; // Pass identification, replacement for typeid
54   WebAssemblyRegStackify() : MachineFunctionPass(ID) {}
55 };
56 } // end anonymous namespace
57 
58 char WebAssemblyRegStackify::ID = 0;
59 FunctionPass *llvm::createWebAssemblyRegStackify() {
60   return new WebAssemblyRegStackify();
61 }
62 
63 // Decorate the given instruction with implicit operands that enforce the
64 // expression stack ordering constraints.
65 static void ImposeStackOrdering(MachineInstr *MI) {
66   // Read and write the opaque EXPR_STACK register.
67   MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
68                                            /*isDef=*/true,
69                                            /*isImp=*/true));
70   MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
71                                            /*isDef=*/false,
72                                            /*isImp=*/true));
73 }
74 
75 // Test whether it's safe to move Def to just before Insert. Note that this
76 // doesn't account for physical register dependencies, because WebAssembly
77 // doesn't have any (other than special ones like EXPR_STACK).
78 // TODO: Compute memory dependencies in a way that doesn't require always
79 // walking the block.
80 // TODO: Compute memory dependencies in a way that uses AliasAnalysis to be
81 // more precise.
82 static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert,
83                          AliasAnalysis &AA) {
84   bool SawStore = false, SawSideEffects = false;
85   MachineBasicBlock::const_iterator D(Def), I(Insert);
86   for (--I; I != D; --I)
87     SawSideEffects |= I->isSafeToMove(&AA, SawStore);
88 
89   return !(SawStore && Def->mayLoad() && !Def->isInvariantLoad(&AA)) &&
90          !(SawSideEffects && !Def->isSafeToMove(&AA, SawStore));
91 }
92 
93 bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
94   DEBUG(dbgs() << "********** Register Stackifying **********\n"
95                   "********** Function: "
96                << MF.getName() << '\n');
97 
98   bool Changed = false;
99   MachineRegisterInfo &MRI = MF.getRegInfo();
100   WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
101   AliasAnalysis &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
102 
103   // Walk the instructions from the bottom up. Currently we don't look past
104   // block boundaries, and the blocks aren't ordered so the block visitation
105   // order isn't significant, but we may want to change this in the future.
106   for (MachineBasicBlock &MBB : MF) {
107     for (MachineInstr &MI : reverse(MBB)) {
108       MachineInstr *Insert = &MI;
109 
110       // Don't nest anything inside a phi.
111       if (Insert->getOpcode() == TargetOpcode::PHI)
112         break;
113 
114       // Don't nest anything inside an inline asm, because we don't have
115       // constraints for $push inputs.
116       if (Insert->getOpcode() == TargetOpcode::INLINEASM)
117         break;
118 
119       // Iterate through the inputs in reverse order, since we'll be pulling
120       // operands off the stack in LIFO order.
121       bool AnyStackified = false;
122       for (MachineOperand &Op : reverse(Insert->uses())) {
123         // We're only interested in explicit virtual register operands.
124         if (!Op.isReg() || Op.isImplicit() || !Op.isUse())
125           continue;
126 
127         unsigned Reg = Op.getReg();
128         if (!TargetRegisterInfo::isVirtualRegister(Reg))
129           continue;
130 
131         // Only consider registers with a single definition.
132         // TODO: Eventually we may relax this, to stackify phi transfers.
133         MachineInstr *Def = MRI.getVRegDef(Reg);
134         if (!Def)
135           continue;
136 
137         // There's no use in nesting implicit defs inside anything.
138         if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF)
139           continue;
140 
141         // Don't nest an INLINE_ASM def into anything, because we don't have
142         // constraints for $pop outputs.
143         if (Def->getOpcode() == TargetOpcode::INLINEASM)
144           continue;
145 
146         // Don't nest PHIs inside of anything.
147         if (Def->getOpcode() == TargetOpcode::PHI)
148           continue;
149 
150         // Argument instructions represent live-in registers and not real
151         // instructions.
152         if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 ||
153             Def->getOpcode() == WebAssembly::ARGUMENT_I64 ||
154             Def->getOpcode() == WebAssembly::ARGUMENT_F32 ||
155             Def->getOpcode() == WebAssembly::ARGUMENT_F64)
156           continue;
157 
158         // Single-use expression trees require defs that have one use, or that
159         // they be trivially clonable.
160         // TODO: Eventually we'll relax this, to take advantage of set_local
161         // returning its result.
162         if (!MRI.hasOneUse(Reg))
163           continue;
164 
165         // For now, be conservative and don't look across block boundaries,
166         // unless we have something trivially clonable.
167         // TODO: Be more aggressive.
168         if (Def->getParent() != &MBB && !Def->isMoveImmediate())
169           continue;
170 
171         // Don't move instructions that have side effects or memory dependencies
172         // or other complications.
173         if (!IsSafeToMove(Def, Insert, AA))
174           continue;
175 
176         Changed = true;
177         AnyStackified = true;
178         // Move the def down and nest it in the current instruction.
179         MBB.insert(MachineBasicBlock::instr_iterator(Insert),
180                    Def->removeFromParent());
181         MFI.stackifyVReg(Reg);
182         ImposeStackOrdering(Def);
183         Insert = Def;
184       }
185       if (AnyStackified)
186         ImposeStackOrdering(&MI);
187     }
188   }
189 
190   // If we used EXPR_STACK anywhere, add it to the live-in sets everywhere
191   // so that it never looks like a use-before-def.
192   if (Changed) {
193     MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK);
194     for (MachineBasicBlock &MBB : MF)
195       MBB.addLiveIn(WebAssembly::EXPR_STACK);
196   }
197 
198 #ifndef NDEBUG
199   // Verify that pushes and pops are performed in FIFO order.
200   SmallVector<unsigned, 0> Stack;
201   for (MachineBasicBlock &MBB : MF) {
202     for (MachineInstr &MI : MBB) {
203       for (MachineOperand &MO : reverse(MI.explicit_operands())) {
204         if (!MO.isReg())
205           continue;
206         unsigned VReg = MO.getReg();
207 
208         if (MFI.isVRegStackified(VReg)) {
209           if (MO.isDef())
210             Stack.push_back(VReg);
211           else
212             assert(Stack.pop_back_val() == VReg);
213         }
214       }
215     }
216     // TODO: Generalize this code to support keeping values on the stack across
217     // basic block boundaries.
218     assert(Stack.empty());
219   }
220 #endif
221 
222   return Changed;
223 }
224