1 // WebAssemblyMachineFunctionInfo.h-WebAssembly machine function info-*- C++ -*-
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file declares WebAssembly-specific per-machine-function
12 /// information.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
17 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
18 
19 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 
22 namespace llvm {
23 
24 /// This class is derived from MachineFunctionInfo and contains private
25 /// WebAssembly-specific information for each MachineFunction.
26 class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
27   MachineFunction &MF;
28 
29   std::vector<MVT> Params;
30   std::vector<MVT> Results;
31   std::vector<MVT> Locals;
32 
33   /// A mapping from CodeGen vreg index to WebAssembly register number.
34   std::vector<unsigned> WARegs;
35 
36   /// A mapping from CodeGen vreg index to a boolean value indicating whether
37   /// the given register is considered to be "stackified", meaning it has been
38   /// determined or made to meet the stack requirements:
39   ///   - single use (per path)
40   ///   - single def (per path)
41   ///   - defined and used in LIFO order with other stack registers
42   BitVector VRegStackified;
43 
44   // A virtual register holding the pointer to the vararg buffer for vararg
45   // functions. It is created and set in TLI::LowerFormalArguments and read by
46   // TLI::LowerVASTART
47   unsigned VarargVreg = -1U;
48 
49  public:
50   explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {}
51   ~WebAssemblyFunctionInfo() override;
52 
53   void addParam(MVT VT) { Params.push_back(VT); }
54   const std::vector<MVT> &getParams() const { return Params; }
55 
56   void addResult(MVT VT) { Results.push_back(VT); }
57   const std::vector<MVT> &getResults() const { return Results; }
58 
59   void addLocal(MVT VT) { Locals.push_back(VT); }
60   const std::vector<MVT> &getLocals() const { return Locals; }
61 
62   unsigned getVarargBufferVreg() const {
63     assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
64     return VarargVreg;
65   }
66   void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
67 
68   static const unsigned UnusedReg = -1u;
69 
70   void stackifyVReg(unsigned VReg) {
71     assert(MF.getRegInfo().getUniqueVRegDef(VReg));
72     if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
73       VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
74     VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
75   }
76   bool isVRegStackified(unsigned VReg) const {
77     if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
78       return false;
79     return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
80   }
81 
82   void initWARegs();
83   void setWAReg(unsigned VReg, unsigned WAReg) {
84     assert(WAReg != UnusedReg);
85     assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
86     WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg;
87   }
88   unsigned getWAReg(unsigned Reg) const {
89     assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size());
90     return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
91   }
92 
93   // For a given stackified WAReg, return the id number to print with push/pop.
94   static unsigned getWARegStackId(unsigned Reg) {
95     assert(Reg & INT32_MIN);
96     return Reg & INT32_MAX;
97   }
98 };
99 
100 void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
101                           Type *Ty, SmallVectorImpl<MVT> &ValueVTs);
102 
103 void ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
104                          SmallVectorImpl<MVT> &Params,
105                          SmallVectorImpl<MVT> &Results);
106 
107 } // end namespace llvm
108 
109 #endif
110