1 // WebAssemblyMachineFunctionInfo.h-WebAssembly machine function info-*- C++ -*-
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file declares WebAssembly-specific per-machine-function
12 /// information.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
17 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
18 
19 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 
22 namespace llvm {
23 
24 /// This class is derived from MachineFunctionInfo and contains private
25 /// WebAssembly-specific information for each MachineFunction.
26 class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
27   MachineFunction &MF;
28 
29   std::vector<MVT> Params;
30   std::vector<MVT> Results;
31 
32   /// A mapping from CodeGen vreg index to WebAssembly register number.
33   std::vector<unsigned> WARegs;
34 
35   /// A mapping from CodeGen vreg index to a boolean value indicating whether
36   /// the given register is considered to be "stackified", meaning it has been
37   /// determined or made to meet the stack requirements:
38   ///   - single use (per path)
39   ///   - single def (per path)
40   ///   - defined and used in LIFO order with other stack registers
41   BitVector VRegStackified;
42 
43   // A virtual register holding the pointer to the vararg buffer for vararg
44   // functions. It is created and set in TLI::LowerFormalArguments and read by
45   // TLI::LowerVASTART
46   unsigned VarargVreg = -1U;
47 
48  public:
49   explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {}
50   ~WebAssemblyFunctionInfo() override;
51 
52   void addParam(MVT VT) { Params.push_back(VT); }
53   const std::vector<MVT> &getParams() const { return Params; }
54 
55   void addResult(MVT VT) { Results.push_back(VT); }
56   const std::vector<MVT> &getResults() const { return Results; }
57 
58   unsigned getVarargBufferVreg() const {
59     assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
60     return VarargVreg;
61   }
62   void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
63 
64   static const unsigned UnusedReg = -1u;
65 
66   void stackifyVReg(unsigned VReg) {
67     if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
68       VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
69     VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
70   }
71   bool isVRegStackified(unsigned VReg) const {
72     if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
73       return false;
74     return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
75   }
76 
77   void initWARegs();
78   void setWAReg(unsigned VReg, unsigned WAReg) {
79     assert(WAReg != UnusedReg);
80     assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
81     WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg;
82   }
83   unsigned getWAReg(unsigned Reg) const {
84     assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size());
85     return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
86   }
87 
88   // For a given stackified WAReg, return the id number to print with push/pop.
89   static unsigned getWARegStackId(unsigned Reg) {
90     assert(Reg & INT32_MIN);
91     return Reg & INT32_MAX;
92   }
93 };
94 
95 void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
96                           Type *Ty, SmallVectorImpl<MVT> &ValueVTs);
97 
98 void ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
99                          SmallVectorImpl<MVT> &Params,
100                          SmallVectorImpl<MVT> &Results);
101 
102 } // end namespace llvm
103 
104 #endif
105