1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly SIMD operand code-gen constructs. 11/// 12//===----------------------------------------------------------------------===// 13 14// Instructions requiring HasSIMD128 and the simd128 prefix byte 15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 16 list<dag> pattern_r, string asmstr_r = "", 17 string asmstr_s = "", bits<32> simdop = -1> { 18 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 19 !or(0xfd00, !and(0xff, simdop))>, 20 Requires<[HasSIMD128]>; 21} 22 23defm "" : ARGUMENT<V128, v16i8>; 24defm "" : ARGUMENT<V128, v8i16>; 25defm "" : ARGUMENT<V128, v4i32>; 26defm "" : ARGUMENT<V128, v2i64>; 27defm "" : ARGUMENT<V128, v4f32>; 28defm "" : ARGUMENT<V128, v2f64>; 29 30// Constrained immediate argument types 31foreach SIZE = [8, 16] in 32def ImmI#SIZE : ImmLeaf<i32, 33 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));" 34>; 35foreach SIZE = [2, 4, 8, 16, 32] in 36def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; 37 38//===----------------------------------------------------------------------===// 39// Load and store 40//===----------------------------------------------------------------------===// 41 42// Load: v128.load 43let mayLoad = 1, UseNamedOperandTable = 1 in 44defm LOAD_V128 : 45 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 46 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 47 "v128.load\t$dst, ${off}(${addr})$p2align", 48 "v128.load\t$off$p2align", 0>; 49 50// Def load and store patterns from WebAssemblyInstrMemory.td for vector types 51foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 52def : LoadPatNoOffset<vec_t, load, LOAD_V128>; 53def : LoadPatImmOff<vec_t, load, regPlusImm, LOAD_V128>; 54def : LoadPatImmOff<vec_t, load, or_is_add, LOAD_V128>; 55def : LoadPatOffsetOnly<vec_t, load, LOAD_V128>; 56def : LoadPatGlobalAddrOffOnly<vec_t, load, LOAD_V128>; 57} 58 59// vNxM.load_splat 60multiclass SIMDLoadSplat<string vec, bits<32> simdop> { 61 let mayLoad = 1, UseNamedOperandTable = 1 in 62 defm LOAD_SPLAT_#vec : 63 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 64 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 65 vec#".load_splat\t$dst, ${off}(${addr})$p2align", 66 vec#".load_splat\t$off$p2align", simdop>; 67} 68 69defm "" : SIMDLoadSplat<"v8x16", 7>; 70defm "" : SIMDLoadSplat<"v16x8", 8>; 71defm "" : SIMDLoadSplat<"v32x4", 9>; 72defm "" : SIMDLoadSplat<"v64x2", 10>; 73 74def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>; 75def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t, 76 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 77def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>; 78 79foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"], 80 ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in { 81def : LoadPatNoOffset<!cast<ValueType>(args[0]), 82 load_splat, 83 !cast<NI>("LOAD_SPLAT_"#args[1])>; 84def : LoadPatImmOff<!cast<ValueType>(args[0]), 85 load_splat, 86 regPlusImm, 87 !cast<NI>("LOAD_SPLAT_"#args[1])>; 88def : LoadPatImmOff<!cast<ValueType>(args[0]), 89 load_splat, 90 or_is_add, 91 !cast<NI>("LOAD_SPLAT_"#args[1])>; 92def : LoadPatOffsetOnly<!cast<ValueType>(args[0]), 93 load_splat, 94 !cast<NI>("LOAD_SPLAT_"#args[1])>; 95def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]), 96 load_splat, 97 !cast<NI>("LOAD_SPLAT_"#args[1])>; 98} 99 100// Load and extend 101multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> { 102 let mayLoad = 1, UseNamedOperandTable = 1 in { 103 defm LOAD_EXTEND_S_#vec_t : 104 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 105 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 106 name#"_s\t$dst, ${off}(${addr})$p2align", 107 name#"_s\t$off$p2align", simdop>; 108 defm LOAD_EXTEND_U_#vec_t : 109 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 110 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 111 name#"_u\t$dst, ${off}(${addr})$p2align", 112 name#"_u\t$off$p2align", !add(simdop, 1)>; 113 } 114} 115 116defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 1>; 117defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 3>; 118defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 5>; 119 120foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in 121foreach exts = [["sextloadv", "_S"], 122 ["zextloadv", "_U"], 123 ["extloadv", "_U"]] in { 124def : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]), 125 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 126def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm, 127 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 128def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add, 129 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 130def : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]), 131 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 132def : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]), 133 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 134} 135 136 137// Store: v128.store 138let mayStore = 1, UseNamedOperandTable = 1 in 139defm STORE_V128 : 140 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec), 141 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 142 "v128.store\t${off}(${addr})$p2align, $vec", 143 "v128.store\t$off$p2align", 11>; 144 145foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 146// Def load and store patterns from WebAssemblyInstrMemory.td for vector types 147def : StorePatNoOffset<vec_t, store, STORE_V128>; 148def : StorePatImmOff<vec_t, store, regPlusImm, STORE_V128>; 149def : StorePatImmOff<vec_t, store, or_is_add, STORE_V128>; 150def : StorePatOffsetOnly<vec_t, store, STORE_V128>; 151def : StorePatGlobalAddrOffOnly<vec_t, store, STORE_V128>; 152} 153 154//===----------------------------------------------------------------------===// 155// Constructing SIMD values 156//===----------------------------------------------------------------------===// 157 158// Constant: v128.const 159multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { 160 let isMoveImm = 1, isReMaterializable = 1, 161 Predicates = [HasUnimplementedSIMD128] in 162 defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, 163 [(set V128:$dst, (vec_t pat))], 164 "v128.const\t$dst, "#args, 165 "v128.const\t"#args, 12>; 166} 167 168defm "" : ConstVec<v16i8, 169 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, 170 vec_i8imm_op:$i2, vec_i8imm_op:$i3, 171 vec_i8imm_op:$i4, vec_i8imm_op:$i5, 172 vec_i8imm_op:$i6, vec_i8imm_op:$i7, 173 vec_i8imm_op:$i8, vec_i8imm_op:$i9, 174 vec_i8imm_op:$iA, vec_i8imm_op:$iB, 175 vec_i8imm_op:$iC, vec_i8imm_op:$iD, 176 vec_i8imm_op:$iE, vec_i8imm_op:$iF), 177 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, 178 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, 179 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, 180 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), 181 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", 182 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; 183defm "" : ConstVec<v8i16, 184 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, 185 vec_i16imm_op:$i2, vec_i16imm_op:$i3, 186 vec_i16imm_op:$i4, vec_i16imm_op:$i5, 187 vec_i16imm_op:$i6, vec_i16imm_op:$i7), 188 (build_vector 189 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, 190 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), 191 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; 192let IsCanonical = 1 in 193defm "" : ConstVec<v4i32, 194 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, 195 vec_i32imm_op:$i2, vec_i32imm_op:$i3), 196 (build_vector (i32 imm:$i0), (i32 imm:$i1), 197 (i32 imm:$i2), (i32 imm:$i3)), 198 "$i0, $i1, $i2, $i3">; 199defm "" : ConstVec<v2i64, 200 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), 201 (build_vector (i64 imm:$i0), (i64 imm:$i1)), 202 "$i0, $i1">; 203defm "" : ConstVec<v4f32, 204 (ins f32imm_op:$i0, f32imm_op:$i1, 205 f32imm_op:$i2, f32imm_op:$i3), 206 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), 207 (f32 fpimm:$i2), (f32 fpimm:$i3)), 208 "$i0, $i1, $i2, $i3">; 209defm "" : ConstVec<v2f64, 210 (ins f64imm_op:$i0, f64imm_op:$i1), 211 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), 212 "$i0, $i1">; 213 214// Shuffle lanes: shuffle 215defm SHUFFLE : 216 SIMD_I<(outs V128:$dst), 217 (ins V128:$x, V128:$y, 218 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 219 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 220 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 221 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 222 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 223 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 224 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 225 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 226 (outs), 227 (ins 228 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 229 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 230 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 231 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 232 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 233 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 234 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 235 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 236 [], 237 "v8x16.shuffle\t$dst, $x, $y, "# 238 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 239 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 240 "v8x16.shuffle\t"# 241 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 242 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 243 13>; 244 245// Shuffles after custom lowering 246def wasm_shuffle_t : SDTypeProfile<1, 18, []>; 247def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; 248foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 249def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y), 250 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 251 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 252 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 253 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 254 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 255 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 256 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 257 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))), 258 (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y), 259 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 260 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 261 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 262 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 263 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 264 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 265 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 266 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>; 267} 268 269// Swizzle lanes: v8x16.swizzle 270def wasm_swizzle_t : SDTypeProfile<1, 2, []>; 271def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>; 272defm SWIZZLE : 273 SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 274 [(set (v16i8 V128:$dst), 275 (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 276 "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 14>; 277 278def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)), 279 (SWIZZLE V128:$src, V128:$mask)>; 280 281// Create vector with identical lanes: splat 282def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>; 283def splat4 : PatFrag<(ops node:$x), (build_vector 284 node:$x, node:$x, node:$x, node:$x)>; 285def splat8 : PatFrag<(ops node:$x), (build_vector 286 node:$x, node:$x, node:$x, node:$x, 287 node:$x, node:$x, node:$x, node:$x)>; 288def splat16 : PatFrag<(ops node:$x), (build_vector 289 node:$x, node:$x, node:$x, node:$x, 290 node:$x, node:$x, node:$x, node:$x, 291 node:$x, node:$x, node:$x, node:$x, 292 node:$x, node:$x, node:$x, node:$x)>; 293 294multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t, 295 PatFrag splat_pat, bits<32> simdop> { 296 // Prefer splats over v128.const for const splats (65 is lowest that works) 297 let AddedComplexity = 65 in 298 defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins), 299 [(set (vec_t V128:$dst), (splat_pat reg_t:$x))], 300 vec#".splat\t$dst, $x", vec#".splat", simdop>; 301} 302 303defm "" : Splat<v16i8, "i8x16", I32, splat16, 15>; 304defm "" : Splat<v8i16, "i16x8", I32, splat8, 16>; 305defm "" : Splat<v4i32, "i32x4", I32, splat4, 17>; 306defm "" : Splat<v2i64, "i64x2", I64, splat2, 18>; 307defm "" : Splat<v4f32, "f32x4", F32, splat4, 19>; 308defm "" : Splat<v2f64, "f64x2", F64, splat2, 20>; 309 310// scalar_to_vector leaves high lanes undefined, so can be a splat 311class ScalarSplatPat<ValueType vec_t, ValueType lane_t, 312 WebAssemblyRegClass reg_t> : 313 Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))), 314 (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>; 315 316def : ScalarSplatPat<v16i8, i32, I32>; 317def : ScalarSplatPat<v8i16, i32, I32>; 318def : ScalarSplatPat<v4i32, i32, I32>; 319def : ScalarSplatPat<v2i64, i64, I64>; 320def : ScalarSplatPat<v4f32, f32, F32>; 321def : ScalarSplatPat<v2f64, f64, F64>; 322 323//===----------------------------------------------------------------------===// 324// Accessing lanes 325//===----------------------------------------------------------------------===// 326 327// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u 328multiclass ExtractLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t, 329 bits<32> simdop, string suffix = ""> { 330 defm EXTRACT_LANE_#vec_t#suffix : 331 SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx), 332 (outs), (ins vec_i8imm_op:$idx), [], 333 vec#".extract_lane"#suffix#"\t$dst, $vec, $idx", 334 vec#".extract_lane"#suffix#"\t$idx", simdop>; 335} 336 337defm "" : ExtractLane<v16i8, "i8x16", I32, 21, "_s">; 338defm "" : ExtractLane<v16i8, "i8x16", I32, 22, "_u">; 339defm "" : ExtractLane<v8i16, "i16x8", I32, 24, "_s">; 340defm "" : ExtractLane<v8i16, "i16x8", I32, 25, "_u">; 341defm "" : ExtractLane<v4i32, "i32x4", I32, 27>; 342defm "" : ExtractLane<v2i64, "i64x2", I64, 29>; 343defm "" : ExtractLane<v4f32, "f32x4", F32, 31>; 344defm "" : ExtractLane<v2f64, "f64x2", F64, 33>; 345 346def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), 347 (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>; 348def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), 349 (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>; 350def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)), 351 (EXTRACT_LANE_v4i32 V128:$vec, imm:$idx)>; 352def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)), 353 (EXTRACT_LANE_v4f32 V128:$vec, imm:$idx)>; 354def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)), 355 (EXTRACT_LANE_v2i64 V128:$vec, imm:$idx)>; 356def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)), 357 (EXTRACT_LANE_v2f64 V128:$vec, imm:$idx)>; 358 359def : Pat< 360 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8), 361 (EXTRACT_LANE_v16i8_s V128:$vec, imm:$idx)>; 362def : Pat< 363 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)), 364 (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>; 365def : Pat< 366 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16), 367 (EXTRACT_LANE_v8i16_s V128:$vec, imm:$idx)>; 368def : Pat< 369 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)), 370 (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>; 371 372// Replace lane value: replace_lane 373multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t, 374 WebAssemblyRegClass reg_t, ValueType lane_t, 375 bits<32> simdop> { 376 defm REPLACE_LANE_#vec_t : 377 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x), 378 (outs), (ins vec_i8imm_op:$idx), 379 [(set V128:$dst, (vector_insert 380 (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))], 381 vec#".replace_lane\t$dst, $vec, $idx, $x", 382 vec#".replace_lane\t$idx", simdop>; 383} 384 385defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 23>; 386defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 26>; 387defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 28>; 388defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 30>; 389defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 32>; 390defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 34>; 391 392// Lower undef lane indices to zero 393def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef), 394 (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>; 395def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef), 396 (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>; 397def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef), 398 (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>; 399def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef), 400 (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>; 401def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef), 402 (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>; 403def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), 404 (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>; 405 406//===----------------------------------------------------------------------===// 407// Comparisons 408//===----------------------------------------------------------------------===// 409 410multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec, 411 string name, CondCode cond, bits<32> simdop> { 412 defm _#vec_t : 413 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 414 [(set (out_t V128:$dst), 415 (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond) 416 )], 417 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>; 418} 419 420multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { 421 defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>; 422 defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond, 423 !add(baseInst, 10)>; 424 defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond, 425 !add(baseInst, 20)>; 426} 427 428multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { 429 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>; 430 defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond, 431 !add(baseInst, 6)>; 432} 433 434// Equality: eq 435let isCommutable = 1 in { 436defm EQ : SIMDConditionInt<"eq", SETEQ, 35>; 437defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>; 438} // isCommutable = 1 439 440// Non-equality: ne 441let isCommutable = 1 in { 442defm NE : SIMDConditionInt<"ne", SETNE, 36>; 443defm NE : SIMDConditionFP<"ne", SETUNE, 66>; 444} // isCommutable = 1 445 446// Less than: lt_s / lt_u / lt 447defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>; 448defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>; 449defm LT : SIMDConditionFP<"lt", SETOLT, 67>; 450 451// Greater than: gt_s / gt_u / gt 452defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>; 453defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>; 454defm GT : SIMDConditionFP<"gt", SETOGT, 68>; 455 456// Less than or equal: le_s / le_u / le 457defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>; 458defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>; 459defm LE : SIMDConditionFP<"le", SETOLE, 69>; 460 461// Greater than or equal: ge_s / ge_u / ge 462defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>; 463defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>; 464defm GE : SIMDConditionFP<"ge", SETOGE, 70>; 465 466// Lower float comparisons that don't care about NaN to standard WebAssembly 467// float comparisons. These instructions are generated with nnan and in the 468// target-independent expansion of unordered comparisons and ordered ne. 469foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32], 470 [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in 471def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 472 (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>; 473 474foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64], 475 [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in 476def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 477 (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>; 478 479 480//===----------------------------------------------------------------------===// 481// Bitwise operations 482//===----------------------------------------------------------------------===// 483 484multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name, 485 bits<32> simdop> { 486 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 487 (outs), (ins), 488 [(set (vec_t V128:$dst), 489 (node (vec_t V128:$lhs), (vec_t V128:$rhs)) 490 )], 491 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, 492 simdop>; 493} 494 495multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> { 496 defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>; 497 defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>; 498 defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>; 499 defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>; 500} 501 502multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name, 503 bits<32> simdop> { 504 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 505 [(set (vec_t V128:$dst), 506 (vec_t (node (vec_t V128:$vec))) 507 )], 508 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>; 509} 510 511// Bitwise logic: v128.not 512foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in 513defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 77>; 514 515// Bitwise logic: v128.and / v128.or / v128.xor 516let isCommutable = 1 in { 517defm AND : SIMDBitwise<and, "and", 78>; 518defm OR : SIMDBitwise<or, "or", 80>; 519defm XOR : SIMDBitwise<xor, "xor", 81>; 520} // isCommutable = 1 521 522// Bitwise logic: v128.andnot 523def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>; 524defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>; 525 526// Bitwise select: v128.bitselect 527foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 528 defm BITSELECT_#vec_t : 529 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), 530 [(set (vec_t V128:$dst), 531 (vec_t (int_wasm_bitselect 532 (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c) 533 )) 534 )], 535 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>; 536 537// Bitselect is equivalent to (c & v1) | (~c & v2) 538foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in 539 def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)), 540 (and (vnot V128:$c), (vec_t V128:$v2)))), 541 (!cast<Instruction>("BITSELECT_"#vec_t) 542 V128:$v1, V128:$v2, V128:$c)>; 543 544//===----------------------------------------------------------------------===// 545// Integer unary arithmetic 546//===----------------------------------------------------------------------===// 547 548multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> { 549 defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>; 550 defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 551 defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 552 defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 553} 554 555multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name, 556 bits<32> simdop> { 557 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 558 [(set I32:$dst, (i32 (op (vec_t V128:$vec))))], 559 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>; 560} 561 562multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> { 563 defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>; 564 defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 32)>; 565 defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 64)>; 566 defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 96)>; 567} 568 569// Integer vector negation 570def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; 571 572// Integer absolute value: abs 573defm ABS : SIMDUnaryInt<abs, "abs", 96>; 574 575// Integer negation: neg 576defm NEG : SIMDUnaryInt<ivneg, "neg", 97>; 577 578// Any lane true: any_true 579defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>; 580 581// All lanes true: all_true 582defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>; 583 584// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1 585// can be folded out 586foreach reduction = 587 [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in 588foreach ty = [v16i8, v8i16, v4i32, v2i64] in { 589def : Pat<(i32 (and 590 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 591 (i32 1) 592 )), 593 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 594def : Pat<(i32 (setne 595 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 596 (i32 0) 597 )), 598 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 599def : Pat<(i32 (seteq 600 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 601 (i32 1) 602 )), 603 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 604} 605 606multiclass SIMDBitmask<ValueType vec_t, string vec, bits<32> simdop> { 607 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 608 [(set I32:$dst, 609 (i32 (int_wasm_bitmask (vec_t V128:$vec))) 610 )], 611 vec#".bitmask\t$dst, $vec", vec#".bitmask", simdop>; 612} 613 614defm BITMASK : SIMDBitmask<v16i8, "i8x16", 100>; 615defm BITMASK : SIMDBitmask<v8i16, "i16x8", 132>; 616defm BITMASK : SIMDBitmask<v4i32, "i32x4", 164>; 617 618//===----------------------------------------------------------------------===// 619// Bit shifts 620//===----------------------------------------------------------------------===// 621 622multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec, 623 string name, bits<32> simdop> { 624 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), 625 (outs), (ins), 626 [(set (vec_t V128:$dst), 627 (node V128:$vec, (vec_t shift_vec)))], 628 vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>; 629} 630 631multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> { 632 defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>; 633 defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name, 634 !add(baseInst, 32)>; 635 defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name, 636 !add(baseInst, 64)>; 637 defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))), 638 name, !add(baseInst, 96)>; 639} 640 641// Left shift by scalar: shl 642defm SHL : SIMDShiftInt<shl, "shl", 107>; 643 644// Right shift by scalar: shr_s / shr_u 645defm SHR_S : SIMDShiftInt<sra, "shr_s", 108>; 646defm SHR_U : SIMDShiftInt<srl, "shr_u", 109>; 647 648// Truncate i64 shift operands to i32s, except if they are already i32s 649foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in { 650def : Pat<(v2i64 (shifts[0] 651 (v2i64 V128:$vec), 652 (v2i64 (splat2 (i64 (sext I32:$x)))) 653 )), 654 (v2i64 (shifts[1] (v2i64 V128:$vec), (i32 I32:$x)))>; 655def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))), 656 (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>; 657} 658 659// 2xi64 shifts with constant shift amounts are custom lowered to avoid wrapping 660def wasm_shift_t : SDTypeProfile<1, 2, 661 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>] 662>; 663def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>; 664def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>; 665def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>; 666foreach shifts = [[wasm_shl, SHL_v2i64], 667 [wasm_shr_s, SHR_S_v2i64], 668 [wasm_shr_u, SHR_U_v2i64]] in 669def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)), 670 (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>; 671 672//===----------------------------------------------------------------------===// 673// Integer binary arithmetic 674//===----------------------------------------------------------------------===// 675 676multiclass SIMDBinaryIntNoI8x16<SDNode node, string name, bits<32> baseInst> { 677 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 678 defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 679 defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 680} 681 682multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> { 683 defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>; 684 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 685} 686 687multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> { 688 defm "" : SIMDBinaryIntSmall<node, name, baseInst>; 689 defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 690} 691 692multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> { 693 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>; 694 defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 695} 696 697// Integer addition: add / add_saturate_s / add_saturate_u 698let isCommutable = 1 in { 699defm ADD : SIMDBinaryInt<add, "add", 110>; 700defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>; 701defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 112>; 702} // isCommutable = 1 703 704// Integer subtraction: sub / sub_saturate_s / sub_saturate_u 705defm SUB : SIMDBinaryInt<sub, "sub", 113>; 706defm SUB_SAT_S : 707 SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 114>; 708defm SUB_SAT_U : 709 SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 115>; 710 711// Integer multiplication: mul 712let isCommutable = 1 in 713defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>; 714 715// Integer min_s / min_u / max_s / max_u 716let isCommutable = 1 in { 717defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>; 718defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>; 719defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>; 720defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>; 721} // isCommutable = 1 722 723// Integer unsigned rounding average: avgr_u 724let isCommutable = 1 in { 725defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 123>; 726defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 155>; 727} 728 729def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), 730 (add node:$lhs, node:$rhs), 731 "return N->getFlags().hasNoUnsignedWrap();">; 732 733foreach nodes = [[v16i8, splat16], [v8i16, splat8]] in 734def : Pat<(srl 735 (add_nuw 736 (add_nuw (nodes[0] V128:$lhs), (nodes[0] V128:$rhs)), 737 (nodes[1] (i32 1)) 738 ), 739 (nodes[0] (nodes[1] (i32 1))) 740 ), 741 (!cast<NI>("AVGR_U_"#nodes[0]) V128:$lhs, V128:$rhs)>; 742 743// Widening dot product: i32x4.dot_i16x8_s 744let isCommutable = 1 in 745defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 746 [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))], 747 "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s", 748 180>; 749 750//===----------------------------------------------------------------------===// 751// Floating-point unary arithmetic 752//===----------------------------------------------------------------------===// 753 754multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> { 755 defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>; 756 defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 12)>; 757} 758 759// Absolute value: abs 760defm ABS : SIMDUnaryFP<fabs, "abs", 224>; 761 762// Negation: neg 763defm NEG : SIMDUnaryFP<fneg, "neg", 225>; 764 765// Square root: sqrt 766defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>; 767 768//===----------------------------------------------------------------------===// 769// Floating-point binary arithmetic 770//===----------------------------------------------------------------------===// 771 772multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> { 773 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>; 774 defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 12)>; 775} 776 777// Addition: add 778let isCommutable = 1 in 779defm ADD : SIMDBinaryFP<fadd, "add", 228>; 780 781// Subtraction: sub 782defm SUB : SIMDBinaryFP<fsub, "sub", 229>; 783 784// Multiplication: mul 785let isCommutable = 1 in 786defm MUL : SIMDBinaryFP<fmul, "mul", 230>; 787 788// Division: div 789defm DIV : SIMDBinaryFP<fdiv, "div", 231>; 790 791// NaN-propagating minimum: min 792defm MIN : SIMDBinaryFP<fminimum, "min", 232>; 793 794// NaN-propagating maximum: max 795defm MAX : SIMDBinaryFP<fmaximum, "max", 233>; 796 797// Pseudo-minimum: pmin 798defm PMIN : SIMDBinaryFP<int_wasm_pmin, "pmin", 234>; 799 800// Pseudo-maximum: pmax 801defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>; 802 803//===----------------------------------------------------------------------===// 804// Conversions 805//===----------------------------------------------------------------------===// 806 807multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op, 808 string name, bits<32> simdop> { 809 defm op#_#vec_t#_#arg_t : 810 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 811 [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))], 812 name#"\t$dst, $vec", name, simdop>; 813} 814 815// Floating point to integer with saturation: trunc_sat 816defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 248>; 817defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 249>; 818 819// Integer to floating point: convert 820defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 250>; 821defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 251>; 822 823// Widening operations 824multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg, 825 bits<32> baseInst> { 826 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed, 827 vec#".widen_low_"#arg#"_s", baseInst>; 828 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed, 829 vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>; 830 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_unsigned, 831 vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>; 832 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_unsigned, 833 vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>; 834} 835 836defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 135>; 837defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 167>; 838 839// Narrowing operations 840multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg, 841 bits<32> baseInst> { 842 defm NARROW_S_#vec_t : 843 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 844 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed 845 (arg_t V128:$low), (arg_t V128:$high))))], 846 vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s", 847 baseInst>; 848 defm NARROW_U_#vec_t : 849 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 850 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned 851 (arg_t V128:$low), (arg_t V128:$high))))], 852 vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u", 853 !add(baseInst, 1)>; 854} 855 856defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 101>; 857defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 133>; 858 859// Lower llvm.wasm.trunc.saturate.* to saturating instructions 860def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))), 861 (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>; 862def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))), 863 (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>; 864 865// Bitcasts are nops 866// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types 867foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 868foreach t2 = !foldl( 869 []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 870 acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)), 871 acc, !listconcat(acc, [cur]) 872 ) 873) in 874def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>; 875 876//===----------------------------------------------------------------------===// 877// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS) 878//===----------------------------------------------------------------------===// 879 880multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> baseInst> { 881 defm QFMA_#vec_t : 882 SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), 883 (outs), (ins), 884 [(set (vec_t V128:$dst), 885 (int_wasm_qfma (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))], 886 vec#".qfma\t$dst, $a, $b, $c", vec#".qfma", baseInst>; 887 defm QFMS_#vec_t : 888 SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), 889 (outs), (ins), 890 [(set (vec_t V128:$dst), 891 (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))], 892 vec#".qfms\t$dst, $a, $b, $c", vec#".qfms", !add(baseInst, 1)>; 893} 894 895defm "" : SIMDQFM<v4f32, "f32x4", 252>; 896defm "" : SIMDQFM<v2f64, "f64x2", 254>; 897