1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// WebAssembly SIMD operand code-gen constructs.
11///
12//===----------------------------------------------------------------------===//
13
14// Instructions requiring HasSIMD128 and the simd128 prefix byte
15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
16                  list<dag> pattern_r, string asmstr_r = "",
17                  string asmstr_s = "", bits<32> simdop = -1> {
18  defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
19              !or(0xfd00, !and(0xff, simdop))>,
20            Requires<[HasSIMD128]>;
21}
22
23defm "" : ARGUMENT<V128, v16i8>;
24defm "" : ARGUMENT<V128, v8i16>;
25defm "" : ARGUMENT<V128, v4i32>;
26defm "" : ARGUMENT<V128, v2i64>;
27defm "" : ARGUMENT<V128, v4f32>;
28defm "" : ARGUMENT<V128, v2f64>;
29
30// Constrained immediate argument types
31foreach SIZE = [8, 16] in
32def ImmI#SIZE : ImmLeaf<i32,
33  "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));"
34>;
35foreach SIZE = [2, 4, 8, 16, 32] in
36def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
37
38//===----------------------------------------------------------------------===//
39// Load and store
40//===----------------------------------------------------------------------===//
41
42// Load: v128.load
43multiclass SIMDLoad<ValueType vec_t> {
44  let mayLoad = 1 in
45  defm LOAD_#vec_t :
46    SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
47           (outs), (ins P2Align:$align, offset32_op:$off), [],
48           "v128.load\t$dst, ${off}(${addr})$align",
49           "v128.load\t$off$align", 0>;
50}
51
52foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
53defm "" : SIMDLoad<vec_t>;
54
55// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
56def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
57def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
58def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;
59def : LoadPatGlobalAddr<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
60def : LoadPatExternalSym<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
61def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
62def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
63def : LoadPatExternSymOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
64}
65
66// Store: v128.store
67multiclass SIMDStore<ValueType vec_t> {
68  let mayStore = 1 in
69  defm STORE_#vec_t :
70    SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
71           (outs), (ins P2Align:$align, offset32_op:$off), [],
72           "v128.store\t${off}(${addr})$align, $vec",
73           "v128.store\t$off$align", 1>;
74}
75
76foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
77defm "" : SIMDStore<vec_t>;
78
79// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
80def : StorePatNoOffset<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
81def : StorePatImmOff<vec_t, store, regPlusImm, !cast<NI>("STORE_"#vec_t)>;
82def : StorePatImmOff<vec_t, store, or_is_add, !cast<NI>("STORE_"#vec_t)>;
83def : StorePatGlobalAddr<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
84def : StorePatExternalSym<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
85def : StorePatOffsetOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
86def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
87def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
88}
89
90//===----------------------------------------------------------------------===//
91// Constructing SIMD values
92//===----------------------------------------------------------------------===//
93
94// Constant: v128.const
95multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
96  let isMoveImm = 1, isReMaterializable = 1,
97      Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
98  defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
99                                  [(set V128:$dst, (vec_t pat))],
100                                  "v128.const\t$dst, "#args,
101                                  "v128.const\t"#args, 2>;
102}
103
104defm "" : ConstVec<v16i8,
105                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
106                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
107                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
108                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
109                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
110                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
111                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
112                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
113                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
114                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
115                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
116                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
117                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
118                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
119defm "" : ConstVec<v8i16,
120                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
121                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
122                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
123                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
124                   (build_vector
125                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
126                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
127                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
128let IsCanonical = 1 in
129defm "" : ConstVec<v4i32,
130                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
131                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
132                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
133                                 (i32 imm:$i2), (i32 imm:$i3)),
134                   "$i0, $i1, $i2, $i3">;
135defm "" : ConstVec<v2i64,
136                   (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
137                   (build_vector (i64 imm:$i0), (i64 imm:$i1)),
138                   "$i0, $i1">;
139defm "" : ConstVec<v4f32,
140                   (ins f32imm_op:$i0, f32imm_op:$i1,
141                        f32imm_op:$i2, f32imm_op:$i3),
142                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
143                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
144                   "$i0, $i1, $i2, $i3">;
145defm "" : ConstVec<v2f64,
146                  (ins f64imm_op:$i0, f64imm_op:$i1),
147                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
148                  "$i0, $i1">;
149
150// Shuffle lanes: shuffle
151defm SHUFFLE :
152  SIMD_I<(outs V128:$dst),
153         (ins V128:$x, V128:$y,
154           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
155           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
156           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
157           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
158           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
159           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
160           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
161           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
162         (outs),
163         (ins
164           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
165           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
166           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
167           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
168           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
169           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
170           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
171           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
172         [],
173         "v8x16.shuffle\t$dst, $x, $y, "#
174           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
175           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
176         "v8x16.shuffle\t"#
177           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
178           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
179         3>;
180
181// Shuffles after custom lowering
182def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
183def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
184foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
185def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
186            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
187            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
188            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
189            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
190            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
191            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
192            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
193            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
194          (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
195            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
196            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
197            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
198            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
199            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
200            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
201            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
202            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
203}
204
205// Create vector with identical lanes: splat
206def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
207def splat4 : PatFrag<(ops node:$x), (build_vector
208                       node:$x, node:$x, node:$x, node:$x)>;
209def splat8 : PatFrag<(ops node:$x), (build_vector
210                       node:$x, node:$x, node:$x, node:$x,
211                       node:$x, node:$x, node:$x, node:$x)>;
212def splat16 : PatFrag<(ops node:$x), (build_vector
213                        node:$x, node:$x, node:$x, node:$x,
214                        node:$x, node:$x, node:$x, node:$x,
215                        node:$x, node:$x, node:$x, node:$x,
216                        node:$x, node:$x, node:$x, node:$x)>;
217
218multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
219                 PatFrag splat_pat, bits<32> simdop> {
220  // Prefer splats over v128.const for const splats (65 is lowest that works)
221  let AddedComplexity = 65 in
222  defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
223                             [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
224                             vec#".splat\t$dst, $x", vec#".splat", simdop>;
225}
226
227defm "" : Splat<v16i8, "i8x16", I32, splat16, 4>;
228defm "" : Splat<v8i16, "i16x8", I32, splat8, 8>;
229defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
230defm "" : Splat<v2i64, "i64x2", I64, splat2, 15>;
231defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
232defm "" : Splat<v2f64, "f64x2", F64, splat2, 21>;
233
234// scalar_to_vector leaves high lanes undefined, so can be a splat
235class ScalarSplatPat<ValueType vec_t, ValueType lane_t,
236                     WebAssemblyRegClass reg_t> :
237  Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
238      (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
239
240def : ScalarSplatPat<v16i8, i32, I32>;
241def : ScalarSplatPat<v8i16, i32, I32>;
242def : ScalarSplatPat<v4i32, i32, I32>;
243def : ScalarSplatPat<v2i64, i64, I64>;
244def : ScalarSplatPat<v4f32, f32, F32>;
245def : ScalarSplatPat<v2f64, f64, F64>;
246
247//===----------------------------------------------------------------------===//
248// Accessing lanes
249//===----------------------------------------------------------------------===//
250
251// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
252multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
253                       WebAssemblyRegClass reg_t, bits<32> simdop,
254                       string suffix = "", SDNode extract = vector_extract> {
255  defm EXTRACT_LANE_#vec_t#suffix :
256      SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
257             (outs), (ins vec_i8imm_op:$idx),
258             [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
259             vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
260             vec#".extract_lane"#suffix#"\t$idx", simdop>;
261}
262
263multiclass ExtractPat<ValueType lane_t, int mask> {
264  def _s : PatFrag<(ops node:$vec, node:$idx),
265                   (i32 (sext_inreg
266                     (i32 (vector_extract
267                       node:$vec,
268                       node:$idx
269                     )),
270                     lane_t
271                   ))>;
272  def _u : PatFrag<(ops node:$vec, node:$idx),
273                   (i32 (and
274                     (i32 (vector_extract
275                       node:$vec,
276                       node:$idx
277                     )),
278                     (i32 mask)
279                   ))>;
280}
281
282defm extract_i8x16 : ExtractPat<i8, 0xff>;
283defm extract_i16x8 : ExtractPat<i16, 0xffff>;
284
285multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
286  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
287                        !cast<PatFrag>("extract_i8x16"#sign)>;
288  defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 4), sign,
289                        !cast<PatFrag>("extract_i16x8"#sign)>;
290}
291
292defm "" : ExtractLaneExtended<"_s", 5>;
293let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
294defm "" : ExtractLaneExtended<"_u", 6>;
295defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
296defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
297defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
298defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>;
299
300// It would be more conventional to use unsigned extracts, but v8
301// doesn't implement them yet
302def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
303          (EXTRACT_LANE_v16i8_s V128:$vec, (i32 LaneIdx16:$idx))>;
304def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
305          (EXTRACT_LANE_v8i16_s V128:$vec, (i32 LaneIdx8:$idx))>;
306
307// Lower undef lane indices to zero
308def : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)),
309          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
310def : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)),
311          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
312def : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)),
313          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
314def : Pat<(i32 (vector_extract (v8i16 V128:$vec), undef)),
315          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
316def : Pat<(sext_inreg (i32 (vector_extract (v16i8 V128:$vec), undef)), i8),
317          (EXTRACT_LANE_v16i8_s V128:$vec, 0)>;
318def : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16),
319          (EXTRACT_LANE_v8i16_s V128:$vec, 0)>;
320def : Pat<(vector_extract (v4i32 V128:$vec), undef),
321          (EXTRACT_LANE_v4i32 V128:$vec, 0)>;
322def : Pat<(vector_extract (v2i64 V128:$vec), undef),
323          (EXTRACT_LANE_v2i64 V128:$vec, 0)>;
324def : Pat<(vector_extract (v4f32 V128:$vec), undef),
325          (EXTRACT_LANE_v4f32 V128:$vec, 0)>;
326def : Pat<(vector_extract (v2f64 V128:$vec), undef),
327          (EXTRACT_LANE_v2f64 V128:$vec, 0)>;
328
329// Replace lane value: replace_lane
330multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
331                       WebAssemblyRegClass reg_t, ValueType lane_t,
332                       bits<32> simdop> {
333  defm REPLACE_LANE_#vec_t :
334      SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
335             (outs), (ins vec_i8imm_op:$idx),
336             [(set V128:$dst, (vector_insert
337               (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
338             vec#".replace_lane\t$dst, $vec, $idx, $x",
339             vec#".replace_lane\t$idx", simdop>;
340}
341
342defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 7>;
343defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 11>;
344defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 14>;
345defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 17>;
346defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>;
347defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 23>;
348
349// Lower undef lane indices to zero
350def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
351          (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
352def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
353          (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
354def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
355          (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;
356def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
357          (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>;
358def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
359          (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>;
360def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
361          (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>;
362
363//===----------------------------------------------------------------------===//
364// Comparisons
365//===----------------------------------------------------------------------===//
366
367multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
368                         string name, CondCode cond, bits<32> simdop> {
369  defm _#vec_t :
370    SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
371           [(set (out_t V128:$dst),
372             (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
373           )],
374           vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
375}
376
377multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
378  defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
379  defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
380                          !add(baseInst, 10)>;
381  defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
382                          !add(baseInst, 20)>;
383}
384
385multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
386  defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
387  defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
388                          !add(baseInst, 6)>;
389}
390
391// Equality: eq
392let isCommutable = 1 in {
393defm EQ : SIMDConditionInt<"eq", SETEQ, 24>;
394defm EQ : SIMDConditionFP<"eq", SETOEQ, 64>;
395} // isCommutable = 1
396
397// Non-equality: ne
398let isCommutable = 1 in {
399defm NE : SIMDConditionInt<"ne", SETNE, 25>;
400defm NE : SIMDConditionFP<"ne", SETUNE, 65>;
401} // isCommutable = 1
402
403// Less than: lt_s / lt_u / lt
404defm LT_S : SIMDConditionInt<"lt_s", SETLT, 26>;
405defm LT_U : SIMDConditionInt<"lt_u", SETULT, 27>;
406defm LT : SIMDConditionFP<"lt", SETOLT, 66>;
407
408// Greater than: gt_s / gt_u / gt
409defm GT_S : SIMDConditionInt<"gt_s", SETGT, 28>;
410defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 29>;
411defm GT : SIMDConditionFP<"gt", SETOGT, 67>;
412
413// Less than or equal: le_s / le_u / le
414defm LE_S : SIMDConditionInt<"le_s", SETLE, 30>;
415defm LE_U : SIMDConditionInt<"le_u", SETULE, 31>;
416defm LE : SIMDConditionFP<"le", SETOLE, 68>;
417
418// Greater than or equal: ge_s / ge_u / ge
419defm GE_S : SIMDConditionInt<"ge_s", SETGE, 32>;
420defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>;
421defm GE : SIMDConditionFP<"ge", SETOGE, 69>;
422
423// Lower float comparisons that don't care about NaN to standard WebAssembly
424// float comparisons. These instructions are generated in the target-independent
425// expansion of unordered comparisons and ordered ne.
426def : Pat<(v4i32 (seteq (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
427          (v4i32 (EQ_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
428def : Pat<(v4i32 (setne (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
429          (v4i32 (NE_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
430def : Pat<(v2i64 (seteq (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
431          (v2i64 (EQ_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
432def : Pat<(v2i64 (setne (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
433          (v2i64 (NE_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
434
435//===----------------------------------------------------------------------===//
436// Bitwise operations
437//===----------------------------------------------------------------------===//
438
439multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
440                      bits<32> simdop> {
441  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
442                        (outs), (ins),
443                        [(set (vec_t V128:$dst),
444                          (node (vec_t V128:$lhs), (vec_t V128:$rhs))
445                        )],
446                        vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
447                        simdop>;
448}
449
450multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
451  defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
452  defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
453  defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
454  defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
455}
456
457multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name,
458                     bits<32> simdop> {
459  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
460                        [(set (vec_t V128:$dst),
461                          (vec_t (node (vec_t V128:$vec)))
462                        )],
463                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
464}
465
466// Bitwise logic: v128.not
467foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
468defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>;
469
470// Bitwise logic: v128.and / v128.or / v128.xor
471let isCommutable = 1 in {
472defm AND : SIMDBitwise<and, "and", 77>;
473defm OR : SIMDBitwise<or, "or", 78>;
474defm XOR : SIMDBitwise<xor, "xor", 79>;
475} // isCommutable = 1
476
477// Bitwise select: v128.bitselect
478foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
479  defm BITSELECT_#vec_t :
480    SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
481           [(set (vec_t V128:$dst),
482             (vec_t (int_wasm_bitselect
483               (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
484             ))
485           )],
486           "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>;
487
488// Bitselect is equivalent to (c & v1) | (~c & v2)
489foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
490  def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
491              (and (vnot V128:$c), (vec_t V128:$v2)))),
492            (!cast<Instruction>("BITSELECT_"#vec_t)
493              V128:$v1, V128:$v2, V128:$c)>;
494
495//===----------------------------------------------------------------------===//
496// Integer unary arithmetic
497//===----------------------------------------------------------------------===//
498
499multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
500  defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>;
501  defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
502  defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
503  defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
504}
505
506multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
507                         bits<32> simdop> {
508  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
509                        [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
510                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
511}
512
513multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
514  defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>;
515  defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>;
516  defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>;
517  defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>;
518}
519
520// Integer vector negation
521def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
522
523// Integer negation: neg
524defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
525
526// Any lane true: any_true
527defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>;
528
529// All lanes true: all_true
530defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>;
531
532//===----------------------------------------------------------------------===//
533// Bit shifts
534//===----------------------------------------------------------------------===//
535
536multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec,
537                     string name, bits<32> simdop> {
538  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
539                        (outs), (ins),
540                        [(set (vec_t V128:$dst),
541                          (node V128:$vec, (vec_t shift_vec)))],
542                        vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
543}
544
545multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
546  defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>;
547  defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name,
548                      !add(baseInst, 17)>;
549  defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name,
550                      !add(baseInst, 34)>;
551  defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
552                      name, !add(baseInst, 51)>;
553}
554
555// Left shift by scalar: shl
556defm SHL : SIMDShiftInt<shl, "shl", 84>;
557
558// Right shift by scalar: shr_s / shr_u
559defm SHR_S : SIMDShiftInt<sra, "shr_s", 85>;
560defm SHR_U : SIMDShiftInt<srl, "shr_u", 86>;
561
562// Truncate i64 shift operands to i32s
563foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in
564def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))),
565          (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
566
567// 2xi64 shifts with constant shift amounts are custom lowered to avoid wrapping
568def wasm_shift_t : SDTypeProfile<1, 2,
569  [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]
570>;
571def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>;
572def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>;
573def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>;
574foreach shifts = [[wasm_shl, SHL_v2i64],
575                  [wasm_shr_s, SHR_S_v2i64],
576                  [wasm_shr_u, SHR_U_v2i64]] in
577def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)),
578          (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>;
579
580//===----------------------------------------------------------------------===//
581// Integer binary arithmetic
582//===----------------------------------------------------------------------===//
583
584multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
585  defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
586  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
587}
588
589multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
590  defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
591  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
592}
593
594multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
595  defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
596  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
597}
598
599// Integer addition: add / add_saturate_s / add_saturate_u
600let isCommutable = 1 in {
601defm ADD : SIMDBinaryInt<add, "add", 87>;
602defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 88>;
603defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 89>;
604} // isCommutable = 1
605
606// Integer subtraction: sub / sub_saturate_s / sub_saturate_u
607defm SUB : SIMDBinaryInt<sub, "sub", 90>;
608defm SUB_SAT_S :
609  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 91>;
610defm SUB_SAT_U :
611  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>;
612
613// Integer multiplication: mul
614defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>;
615
616//===----------------------------------------------------------------------===//
617// Floating-point unary arithmetic
618//===----------------------------------------------------------------------===//
619
620multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
621  defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
622  defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
623}
624
625// Absolute value: abs
626defm ABS : SIMDUnaryFP<fabs, "abs", 149>;
627
628// Negation: neg
629defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
630
631// Square root: sqrt
632let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
633defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
634
635//===----------------------------------------------------------------------===//
636// Floating-point binary arithmetic
637//===----------------------------------------------------------------------===//
638
639multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
640  defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
641  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
642}
643
644// Addition: add
645let isCommutable = 1 in
646defm ADD : SIMDBinaryFP<fadd, "add", 154>;
647
648// Subtraction: sub
649defm SUB : SIMDBinaryFP<fsub, "sub", 155>;
650
651// Multiplication: mul
652let isCommutable = 1 in
653defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
654
655// Division: div
656let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
657defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
658
659// NaN-propagating minimum: min
660defm MIN : SIMDBinaryFP<fminimum, "min", 158>;
661
662// NaN-propagating maximum: max
663defm MAX : SIMDBinaryFP<fmaximum, "max", 159>;
664
665//===----------------------------------------------------------------------===//
666// Conversions
667//===----------------------------------------------------------------------===//
668
669multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
670                       string name, bits<32> simdop> {
671  defm op#_#vec_t#_#arg_t :
672    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
673           [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
674           name#"\t$dst, $vec", name, simdop>;
675}
676
677// Integer to floating point: convert
678defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
679defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
680defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
681defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
682
683// Floating point to integer with saturation: trunc_sat
684defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
685defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
686defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
687defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
688
689// Lower llvm.wasm.trunc.saturate.* to saturating instructions
690def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
691          (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
692def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
693          (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>;
694def : Pat<(v2i64 (int_wasm_trunc_saturate_signed (v2f64 V128:$src))),
695          (fp_to_sint_v2i64_v2f64 (v2f64 V128:$src))>;
696def : Pat<(v2i64 (int_wasm_trunc_saturate_unsigned (v2f64 V128:$src))),
697          (fp_to_uint_v2i64_v2f64 (v2f64 V128:$src))>;
698
699// Bitcasts are nops
700// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
701foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
702foreach t2 = !foldl(
703  []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
704  acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
705    acc, !listconcat(acc, [cur])
706  )
707) in
708def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
709