1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly SIMD operand code-gen constructs. 11/// 12//===----------------------------------------------------------------------===// 13 14// Instructions requiring HasSIMD128 and the simd128 prefix byte 15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 16 list<dag> pattern_r, string asmstr_r = "", 17 string asmstr_s = "", bits<32> simdop = -1> { 18 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 19 !if(!ge(simdop, 0x100), 20 !or(0xfd0000, !and(0xffff, simdop)), 21 !or(0xfd00, !and(0xff, simdop)))>, 22 Requires<[HasSIMD128]>; 23} 24 25defm "" : ARGUMENT<V128, v16i8>; 26defm "" : ARGUMENT<V128, v8i16>; 27defm "" : ARGUMENT<V128, v4i32>; 28defm "" : ARGUMENT<V128, v2i64>; 29defm "" : ARGUMENT<V128, v4f32>; 30defm "" : ARGUMENT<V128, v2f64>; 31 32// Constrained immediate argument types 33foreach SIZE = [8, 16] in 34def ImmI#SIZE : ImmLeaf<i32, 35 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));" 36>; 37foreach SIZE = [2, 4, 8, 16, 32] in 38def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; 39 40// Create vector with identical lanes: splat 41def splat2 : PatFrag<(ops node:$x), (build_vector $x, $x)>; 42def splat4 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x)>; 43def splat8 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x, 44 $x, $x, $x, $x)>; 45def splat16 : PatFrag<(ops node:$x), 46 (build_vector $x, $x, $x, $x, $x, $x, $x, $x, 47 $x, $x, $x, $x, $x, $x, $x, $x)>; 48 49class Vec { 50 ValueType vt; 51 ValueType int_vt; 52 ValueType lane_vt; 53 WebAssemblyRegClass lane_rc; 54 int lane_bits; 55 ImmLeaf lane_idx; 56 PatFrag splat; 57 string prefix; 58 Vec split; 59} 60 61def I8x16 : Vec { 62 let vt = v16i8; 63 let int_vt = vt; 64 let lane_vt = i32; 65 let lane_rc = I32; 66 let lane_bits = 8; 67 let lane_idx = LaneIdx16; 68 let splat = splat16; 69 let prefix = "i8x16"; 70} 71 72def I16x8 : Vec { 73 let vt = v8i16; 74 let int_vt = vt; 75 let lane_vt = i32; 76 let lane_rc = I32; 77 let lane_bits = 16; 78 let lane_idx = LaneIdx8; 79 let splat = splat8; 80 let prefix = "i16x8"; 81 let split = I8x16; 82} 83 84def I32x4 : Vec { 85 let vt = v4i32; 86 let int_vt = vt; 87 let lane_vt = i32; 88 let lane_rc = I32; 89 let lane_bits = 32; 90 let lane_idx = LaneIdx4; 91 let splat = splat4; 92 let prefix = "i32x4"; 93 let split = I16x8; 94} 95 96def I64x2 : Vec { 97 let vt = v2i64; 98 let int_vt = vt; 99 let lane_vt = i64; 100 let lane_rc = I64; 101 let lane_bits = 64; 102 let lane_idx = LaneIdx2; 103 let splat = splat2; 104 let prefix = "i64x2"; 105 let split = I32x4; 106} 107 108def F32x4 : Vec { 109 let vt = v4f32; 110 let int_vt = v4i32; 111 let lane_vt = f32; 112 let lane_rc = F32; 113 let lane_bits = 32; 114 let lane_idx = LaneIdx4; 115 let splat = splat4; 116 let prefix = "f32x4"; 117} 118 119def F64x2 : Vec { 120 let vt = v2f64; 121 let int_vt = v2i64; 122 let lane_vt = f64; 123 let lane_rc = F64; 124 let lane_bits = 64; 125 let lane_idx = LaneIdx2; 126 let splat = splat2; 127 let prefix = "f64x2"; 128} 129 130defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2]; 131defvar IntVecs = [I8x16, I16x8, I32x4, I64x2]; 132 133//===----------------------------------------------------------------------===// 134// Load and store 135//===----------------------------------------------------------------------===// 136 137// Load: v128.load 138let mayLoad = 1, UseNamedOperandTable = 1 in { 139defm LOAD_V128_A32 : 140 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 141 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 142 "v128.load\t$dst, ${off}(${addr})$p2align", 143 "v128.load\t$off$p2align", 0>; 144defm LOAD_V128_A64 : 145 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 146 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 147 "v128.load\t$dst, ${off}(${addr})$p2align", 148 "v128.load\t$off$p2align", 0>; 149} 150 151// Def load patterns from WebAssemblyInstrMemory.td for vector types 152foreach vec = AllVecs in { 153defm : LoadPatNoOffset<vec.vt, load, "LOAD_V128">; 154defm : LoadPatImmOff<vec.vt, load, regPlusImm, "LOAD_V128">; 155defm : LoadPatImmOff<vec.vt, load, or_is_add, "LOAD_V128">; 156defm : LoadPatOffsetOnly<vec.vt, load, "LOAD_V128">; 157defm : LoadPatGlobalAddrOffOnly<vec.vt, load, "LOAD_V128">; 158} 159 160// v128.loadX_splat 161multiclass SIMDLoadSplat<int size, bits<32> simdop> { 162 let mayLoad = 1, UseNamedOperandTable = 1 in { 163 defm LOAD#size#_SPLAT_A32 : 164 SIMD_I<(outs V128:$dst), 165 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 166 (outs), 167 (ins P2Align:$p2align, offset32_op:$off), [], 168 "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align", 169 "v128.load"#size#"_splat\t$off$p2align", simdop>; 170 defm LOAD#size#_SPLAT_A64 : 171 SIMD_I<(outs V128:$dst), 172 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 173 (outs), 174 (ins P2Align:$p2align, offset64_op:$off), [], 175 "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align", 176 "v128.load"#size#"_splat\t$off$p2align", simdop>; 177 } 178} 179 180defm "" : SIMDLoadSplat<8, 7>; 181defm "" : SIMDLoadSplat<16, 8>; 182defm "" : SIMDLoadSplat<32, 9>; 183defm "" : SIMDLoadSplat<64, 10>; 184 185def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>; 186def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t, 187 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 188def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>; 189 190foreach vec = AllVecs in { 191defvar inst = "LOAD"#vec.lane_bits#"_SPLAT"; 192defm : LoadPatNoOffset<vec.vt, load_splat, inst>; 193defm : LoadPatImmOff<vec.vt, load_splat, regPlusImm, inst>; 194defm : LoadPatImmOff<vec.vt, load_splat, or_is_add, inst>; 195defm : LoadPatOffsetOnly<vec.vt, load_splat, inst>; 196defm : LoadPatGlobalAddrOffOnly<vec.vt, load_splat, inst>; 197} 198 199// Load and extend 200multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> { 201 defvar signed = vec.prefix#".load"#loadPat#"_s"; 202 defvar unsigned = vec.prefix#".load"#loadPat#"_u"; 203 let mayLoad = 1, UseNamedOperandTable = 1 in { 204 defm LOAD_EXTEND_S_#vec#_A32 : 205 SIMD_I<(outs V128:$dst), 206 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 207 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 208 signed#"\t$dst, ${off}(${addr})$p2align", 209 signed#"\t$off$p2align", simdop>; 210 defm LOAD_EXTEND_U_#vec#_A32 : 211 SIMD_I<(outs V128:$dst), 212 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 213 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 214 unsigned#"\t$dst, ${off}(${addr})$p2align", 215 unsigned#"\t$off$p2align", !add(simdop, 1)>; 216 defm LOAD_EXTEND_S_#vec#_A64 : 217 SIMD_I<(outs V128:$dst), 218 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 219 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 220 signed#"\t$dst, ${off}(${addr})$p2align", 221 signed#"\t$off$p2align", simdop>; 222 defm LOAD_EXTEND_U_#vec#_A64 : 223 SIMD_I<(outs V128:$dst), 224 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 225 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 226 unsigned#"\t$dst, ${off}(${addr})$p2align", 227 unsigned#"\t$off$p2align", !add(simdop, 1)>; 228 } 229} 230 231defm "" : SIMDLoadExtend<I16x8, "8x8", 1>; 232defm "" : SIMDLoadExtend<I32x4, "16x4", 3>; 233defm "" : SIMDLoadExtend<I64x2, "32x2", 5>; 234 235foreach vec = [I16x8, I32x4, I64x2] in 236foreach exts = [["sextloadvi", "_S"], 237 ["zextloadvi", "_U"], 238 ["extloadvi", "_U"]] in { 239defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits); 240defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec; 241defm : LoadPatNoOffset<vec.vt, loadpat, inst>; 242defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>; 243defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>; 244defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>; 245defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>; 246} 247 248// Load lane into zero vector 249multiclass SIMDLoadZero<Vec vec, bits<32> simdop> { 250 defvar name = "v128.load"#vec.lane_bits#"_zero"; 251 let mayLoad = 1, UseNamedOperandTable = 1 in { 252 defm LOAD_ZERO_#vec#_A32 : 253 SIMD_I<(outs V128:$dst), 254 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 255 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 256 name#"\t$dst, ${off}(${addr})$p2align", 257 name#"\t$off$p2align", simdop>; 258 defm LOAD_ZERO_#vec#_A64 : 259 SIMD_I<(outs V128:$dst), 260 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 261 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 262 name#"\t$dst, ${off}(${addr})$p2align", 263 name#"\t$off$p2align", simdop>; 264 } // mayLoad = 1, UseNamedOperandTable = 1 265} 266 267// TODO: Also support v4f32 and v2f64 once the instructions are merged 268// to the proposal 269defm "" : SIMDLoadZero<I32x4, 0x5c>; 270defm "" : SIMDLoadZero<I64x2, 0x5d>; 271 272foreach vec = [I32x4, I64x2] in { 273defvar loadpat = !cast<Intrinsic>("int_wasm_load"#vec.lane_bits#"_zero"); 274defvar inst = "LOAD_ZERO_"#vec; 275defm : LoadPatNoOffset<vec.vt, loadpat, inst>; 276defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>; 277defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>; 278defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>; 279defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>; 280} 281 282// Load lane 283multiclass SIMDLoadLane<Vec vec, bits<32> simdop> { 284 defvar name = "v128.load"#vec.lane_bits#"_lane"; 285 let mayLoad = 1, UseNamedOperandTable = 1 in { 286 defm LOAD_LANE_#vec#_A32 : 287 SIMD_I<(outs V128:$dst), 288 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 289 I32:$addr, V128:$vec), 290 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 291 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 292 name#"\t$off$p2align, $idx", simdop>; 293 defm LOAD_LANE_#vec#_A64 : 294 SIMD_I<(outs V128:$dst), 295 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 296 I64:$addr, V128:$vec), 297 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 298 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 299 name#"\t$off$p2align, $idx", simdop>; 300 } // mayLoad = 1, UseNamedOperandTable = 1 301} 302 303// TODO: Also support v4f32 and v2f64 once the instructions are merged 304// to the proposal 305defm "" : SIMDLoadLane<I8x16, 0x54>; 306defm "" : SIMDLoadLane<I16x8, 0x55>; 307defm "" : SIMDLoadLane<I32x4, 0x56>; 308defm "" : SIMDLoadLane<I64x2, 0x57>; 309 310// Select loads with no constant offset. 311multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> { 312 defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32"); 313 defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64"); 314 def : Pat<(vec.vt (kind (i32 I32:$addr), 315 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))), 316 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>, 317 Requires<[HasAddr32]>; 318 def : Pat<(vec.vt (kind (i64 I64:$addr), 319 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))), 320 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>, 321 Requires<[HasAddr64]>; 322} 323 324defm : LoadLanePatNoOffset<I8x16, int_wasm_load8_lane>; 325defm : LoadLanePatNoOffset<I16x8, int_wasm_load16_lane>; 326defm : LoadLanePatNoOffset<I32x4, int_wasm_load32_lane>; 327defm : LoadLanePatNoOffset<I64x2, int_wasm_load64_lane>; 328 329// TODO: Also support the other load patterns for load_lane once the instructions 330// are merged to the proposal. 331 332// Store: v128.store 333let mayStore = 1, UseNamedOperandTable = 1 in { 334defm STORE_V128_A32 : 335 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec), 336 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 337 "v128.store\t${off}(${addr})$p2align, $vec", 338 "v128.store\t$off$p2align", 11>; 339defm STORE_V128_A64 : 340 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec), 341 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 342 "v128.store\t${off}(${addr})$p2align, $vec", 343 "v128.store\t$off$p2align", 11>; 344} 345 346// Def store patterns from WebAssemblyInstrMemory.td for vector types 347foreach vec = AllVecs in { 348defm : StorePatNoOffset<vec.vt, store, "STORE_V128">; 349defm : StorePatImmOff<vec.vt, store, regPlusImm, "STORE_V128">; 350defm : StorePatImmOff<vec.vt, store, or_is_add, "STORE_V128">; 351defm : StorePatOffsetOnly<vec.vt, store, "STORE_V128">; 352defm : StorePatGlobalAddrOffOnly<vec.vt, store, "STORE_V128">; 353} 354 355// Store lane 356multiclass SIMDStoreLane<Vec vec, bits<32> simdop> { 357 defvar name = "v128.store"#vec.lane_bits#"_lane"; 358 let mayStore = 1, UseNamedOperandTable = 1 in { 359 defm STORE_LANE_#vec#_A32 : 360 SIMD_I<(outs), 361 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 362 I32:$addr, V128:$vec), 363 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 364 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 365 name#"\t$off$p2align, $idx", simdop>; 366 defm STORE_LANE_#vec#_A64 : 367 SIMD_I<(outs V128:$dst), 368 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 369 I64:$addr, V128:$vec), 370 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 371 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 372 name#"\t$off$p2align, $idx", simdop>; 373 } // mayStore = 1, UseNamedOperandTable = 1 374} 375 376// TODO: Also support v4f32 and v2f64 once the instructions are merged 377// to the proposal 378defm "" : SIMDStoreLane<I8x16, 0x58>; 379defm "" : SIMDStoreLane<I16x8, 0x59>; 380defm "" : SIMDStoreLane<I32x4, 0x5a>; 381defm "" : SIMDStoreLane<I64x2, 0x5b>; 382 383// Select stores with no constant offset. 384multiclass StoreLanePatNoOffset<Vec vec, Intrinsic kind> { 385 def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)), 386 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>, 387 Requires<[HasAddr32]>; 388 def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)), 389 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>, 390 Requires<[HasAddr64]>; 391} 392 393defm : StoreLanePatNoOffset<I8x16, int_wasm_store8_lane>; 394defm : StoreLanePatNoOffset<I16x8, int_wasm_store16_lane>; 395defm : StoreLanePatNoOffset<I32x4, int_wasm_store32_lane>; 396defm : StoreLanePatNoOffset<I64x2, int_wasm_store64_lane>; 397 398// TODO: Also support the other store patterns for store_lane once the 399// instructions are merged to the proposal. 400 401//===----------------------------------------------------------------------===// 402// Constructing SIMD values 403//===----------------------------------------------------------------------===// 404 405// Constant: v128.const 406multiclass ConstVec<Vec vec, dag ops, dag pat, string args> { 407 let isMoveImm = 1, isReMaterializable = 1 in 408 defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops, 409 [(set V128:$dst, (vec.vt pat))], 410 "v128.const\t$dst, "#args, 411 "v128.const\t"#args, 12>; 412} 413 414defm "" : ConstVec<I8x16, 415 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, 416 vec_i8imm_op:$i2, vec_i8imm_op:$i3, 417 vec_i8imm_op:$i4, vec_i8imm_op:$i5, 418 vec_i8imm_op:$i6, vec_i8imm_op:$i7, 419 vec_i8imm_op:$i8, vec_i8imm_op:$i9, 420 vec_i8imm_op:$iA, vec_i8imm_op:$iB, 421 vec_i8imm_op:$iC, vec_i8imm_op:$iD, 422 vec_i8imm_op:$iE, vec_i8imm_op:$iF), 423 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, 424 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, 425 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, 426 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), 427 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", 428 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; 429defm "" : ConstVec<I16x8, 430 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, 431 vec_i16imm_op:$i2, vec_i16imm_op:$i3, 432 vec_i16imm_op:$i4, vec_i16imm_op:$i5, 433 vec_i16imm_op:$i6, vec_i16imm_op:$i7), 434 (build_vector 435 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, 436 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), 437 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; 438let IsCanonical = 1 in 439defm "" : ConstVec<I32x4, 440 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, 441 vec_i32imm_op:$i2, vec_i32imm_op:$i3), 442 (build_vector (i32 imm:$i0), (i32 imm:$i1), 443 (i32 imm:$i2), (i32 imm:$i3)), 444 "$i0, $i1, $i2, $i3">; 445defm "" : ConstVec<I64x2, 446 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), 447 (build_vector (i64 imm:$i0), (i64 imm:$i1)), 448 "$i0, $i1">; 449defm "" : ConstVec<F32x4, 450 (ins f32imm_op:$i0, f32imm_op:$i1, 451 f32imm_op:$i2, f32imm_op:$i3), 452 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), 453 (f32 fpimm:$i2), (f32 fpimm:$i3)), 454 "$i0, $i1, $i2, $i3">; 455defm "" : ConstVec<F64x2, 456 (ins f64imm_op:$i0, f64imm_op:$i1), 457 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), 458 "$i0, $i1">; 459 460// Shuffle lanes: shuffle 461defm SHUFFLE : 462 SIMD_I<(outs V128:$dst), 463 (ins V128:$x, V128:$y, 464 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 465 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 466 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 467 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 468 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 469 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 470 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 471 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 472 (outs), 473 (ins 474 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 475 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 476 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 477 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 478 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 479 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 480 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 481 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 482 [], 483 "i8x16.shuffle\t$dst, $x, $y, "# 484 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 485 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 486 "i8x16.shuffle\t"# 487 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 488 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 489 13>; 490 491// Shuffles after custom lowering 492def wasm_shuffle_t : SDTypeProfile<1, 18, []>; 493def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; 494foreach vec = AllVecs in { 495def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y), 496 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 497 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 498 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 499 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 500 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 501 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 502 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 503 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))), 504 (SHUFFLE $x, $y, 505 imm:$m0, imm:$m1, imm:$m2, imm:$m3, 506 imm:$m4, imm:$m5, imm:$m6, imm:$m7, 507 imm:$m8, imm:$m9, imm:$mA, imm:$mB, 508 imm:$mC, imm:$mD, imm:$mE, imm:$mF)>; 509} 510 511// Swizzle lanes: i8x16.swizzle 512def wasm_swizzle_t : SDTypeProfile<1, 2, []>; 513def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>; 514defm SWIZZLE : 515 SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 516 [(set (v16i8 V128:$dst), 517 (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 518 "i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>; 519 520def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)), 521 (SWIZZLE $src, $mask)>; 522 523multiclass Splat<Vec vec, bits<32> simdop> { 524 defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x), 525 (outs), (ins), 526 [(set (vec.vt V128:$dst), 527 (vec.splat vec.lane_rc:$x))], 528 vec.prefix#".splat\t$dst, $x", vec.prefix#".splat", 529 simdop>; 530} 531 532defm "" : Splat<I8x16, 15>; 533defm "" : Splat<I16x8, 16>; 534defm "" : Splat<I32x4, 17>; 535defm "" : Splat<I64x2, 18>; 536defm "" : Splat<F32x4, 19>; 537defm "" : Splat<F64x2, 20>; 538 539// scalar_to_vector leaves high lanes undefined, so can be a splat 540foreach vec = AllVecs in 541def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))), 542 (!cast<Instruction>("SPLAT_"#vec) $x)>; 543 544//===----------------------------------------------------------------------===// 545// Accessing lanes 546//===----------------------------------------------------------------------===// 547 548// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u 549multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> { 550 defm EXTRACT_LANE_#vec#suffix : 551 SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx), 552 (outs), (ins vec_i8imm_op:$idx), [], 553 vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx", 554 vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>; 555} 556 557defm "" : ExtractLane<I8x16, 21, "_s">; 558defm "" : ExtractLane<I8x16, 22, "_u">; 559defm "" : ExtractLane<I16x8, 24, "_s">; 560defm "" : ExtractLane<I16x8, 25, "_u">; 561defm "" : ExtractLane<I32x4, 27>; 562defm "" : ExtractLane<I64x2, 29>; 563defm "" : ExtractLane<F32x4, 31>; 564defm "" : ExtractLane<F64x2, 33>; 565 566def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), 567 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>; 568def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), 569 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; 570def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)), 571 (EXTRACT_LANE_I32x4 $vec, imm:$idx)>; 572def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)), 573 (EXTRACT_LANE_F32x4 $vec, imm:$idx)>; 574def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)), 575 (EXTRACT_LANE_I64x2 $vec, imm:$idx)>; 576def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)), 577 (EXTRACT_LANE_F64x2 $vec, imm:$idx)>; 578 579def : Pat< 580 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8), 581 (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>; 582def : Pat< 583 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)), 584 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>; 585def : Pat< 586 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16), 587 (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>; 588def : Pat< 589 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)), 590 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; 591 592// Replace lane value: replace_lane 593multiclass ReplaceLane<Vec vec, bits<32> simdop> { 594 defm REPLACE_LANE_#vec : 595 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x), 596 (outs), (ins vec_i8imm_op:$idx), 597 [(set V128:$dst, (vector_insert 598 (vec.vt V128:$vec), 599 (vec.lane_vt vec.lane_rc:$x), 600 (i32 vec.lane_idx:$idx)))], 601 vec.prefix#".replace_lane\t$dst, $vec, $idx, $x", 602 vec.prefix#".replace_lane\t$idx", simdop>; 603} 604 605defm "" : ReplaceLane<I8x16, 23>; 606defm "" : ReplaceLane<I16x8, 26>; 607defm "" : ReplaceLane<I32x4, 28>; 608defm "" : ReplaceLane<I64x2, 30>; 609defm "" : ReplaceLane<F32x4, 32>; 610defm "" : ReplaceLane<F64x2, 34>; 611 612// Lower undef lane indices to zero 613def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef), 614 (REPLACE_LANE_I8x16 $vec, 0, $x)>; 615def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef), 616 (REPLACE_LANE_I16x8 $vec, 0, $x)>; 617def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef), 618 (REPLACE_LANE_I32x4 $vec, 0, $x)>; 619def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef), 620 (REPLACE_LANE_I64x2 $vec, 0, $x)>; 621def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef), 622 (REPLACE_LANE_F32x4 $vec, 0, $x)>; 623def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), 624 (REPLACE_LANE_F64x2 $vec, 0, $x)>; 625 626//===----------------------------------------------------------------------===// 627// Comparisons 628//===----------------------------------------------------------------------===// 629 630multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> { 631 defm _#vec : 632 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 633 [(set (vec.int_vt V128:$dst), 634 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))], 635 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 636 vec.prefix#"."#name, simdop>; 637} 638 639multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { 640 defm "" : SIMDCondition<I8x16, name, cond, baseInst>; 641 defm "" : SIMDCondition<I16x8, name, cond, !add(baseInst, 10)>; 642 defm "" : SIMDCondition<I32x4, name, cond, !add(baseInst, 20)>; 643} 644 645multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { 646 defm "" : SIMDCondition<F32x4, name, cond, baseInst>; 647 defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>; 648} 649 650// Equality: eq 651let isCommutable = 1 in { 652defm EQ : SIMDConditionInt<"eq", SETEQ, 35>; 653defm EQ : SIMDCondition<I64x2, "eq", SETEQ, 214>; 654defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>; 655} // isCommutable = 1 656 657// Non-equality: ne 658let isCommutable = 1 in { 659defm NE : SIMDConditionInt<"ne", SETNE, 36>; 660defm NE : SIMDCondition<I64x2, "ne", SETNE, 215>; 661defm NE : SIMDConditionFP<"ne", SETUNE, 66>; 662} // isCommutable = 1 663 664// Less than: lt_s / lt_u / lt 665defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>; 666defm LT_S : SIMDCondition<I64x2, "lt_s", SETLT, 216>; 667defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>; 668defm LT : SIMDConditionFP<"lt", SETOLT, 67>; 669 670// Greater than: gt_s / gt_u / gt 671defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>; 672defm GT_S : SIMDCondition<I64x2, "gt_s", SETGT, 217>; 673defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>; 674defm GT : SIMDConditionFP<"gt", SETOGT, 68>; 675 676// Less than or equal: le_s / le_u / le 677defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>; 678defm LE_S : SIMDCondition<I64x2, "le_s", SETLE, 218>; 679defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>; 680defm LE : SIMDConditionFP<"le", SETOLE, 69>; 681 682// Greater than or equal: ge_s / ge_u / ge 683defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>; 684defm GE_S : SIMDCondition<I64x2, "ge_s", SETGE, 219>; 685defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>; 686defm GE : SIMDConditionFP<"ge", SETOGE, 70>; 687 688// Lower float comparisons that don't care about NaN to standard WebAssembly 689// float comparisons. These instructions are generated with nnan and in the 690// target-independent expansion of unordered comparisons and ordered ne. 691foreach nodes = [[seteq, EQ_F32x4], [setne, NE_F32x4], [setlt, LT_F32x4], 692 [setgt, GT_F32x4], [setle, LE_F32x4], [setge, GE_F32x4]] in 693def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 694 (nodes[1] $lhs, $rhs)>; 695 696foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2], 697 [setgt, GT_F64x2], [setle, LE_F64x2], [setge, GE_F64x2]] in 698def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 699 (nodes[1] $lhs, $rhs)>; 700 701//===----------------------------------------------------------------------===// 702// Bitwise operations 703//===----------------------------------------------------------------------===// 704 705multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> { 706 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 707 (outs), (ins), 708 [(set (vec.vt V128:$dst), 709 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))], 710 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 711 vec.prefix#"."#name, simdop>; 712} 713 714multiclass SIMDBitwise<SDPatternOperator node, string name, bits<32> simdop, 715 bit commutable = false> { 716 let isCommutable = commutable in 717 defm "" : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 718 (outs), (ins), [], 719 "v128."#name#"\t$dst, $lhs, $rhs", "v128."#name, simdop>; 720 foreach vec = IntVecs in 721 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 722 (!cast<NI>(NAME) $lhs, $rhs)>; 723} 724 725multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> { 726 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), 727 [(set (vec.vt V128:$dst), 728 (vec.vt (node (vec.vt V128:$v))))], 729 vec.prefix#"."#name#"\t$dst, $v", 730 vec.prefix#"."#name, simdop>; 731} 732 733// Bitwise logic: v128.not 734defm NOT : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), [], 735 "v128.not\t$dst, $v", "v128.not", 77>; 736foreach vec = IntVecs in 737def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>; 738 739// Bitwise logic: v128.and / v128.or / v128.xor 740defm AND : SIMDBitwise<and, "and", 78, true>; 741defm OR : SIMDBitwise<or, "or", 80, true>; 742defm XOR : SIMDBitwise<xor, "xor", 81, true>; 743 744// Bitwise logic: v128.andnot 745def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>; 746defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>; 747 748// Bitwise select: v128.bitselect 749defm BITSELECT : 750 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), [], 751 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>; 752 753foreach vec = AllVecs in 754def : Pat<(vec.vt (int_wasm_bitselect 755 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))), 756 (BITSELECT $v1, $v2, $c)>; 757 758// Bitselect is equivalent to (c & v1) | (~c & v2) 759foreach vec = IntVecs in 760def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)), 761 (and (vnot V128:$c), (vec.vt V128:$v2)))), 762 (BITSELECT $v1, $v2, $c)>; 763 764// Also implement vselect in terms of bitselect 765foreach vec = AllVecs in 766def : Pat<(vec.vt (vselect 767 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))), 768 (BITSELECT $v1, $v2, $c)>; 769 770// MVP select on v128 values 771defm SELECT_V128 : 772 I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), (outs), (ins), [], 773 "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>; 774 775foreach vec = AllVecs in { 776def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 777 (SELECT_V128 $lhs, $rhs, $cond)>; 778 779// ISD::SELECT requires its operand to conform to getBooleanContents, but 780// WebAssembly's select interprets any non-zero value as true, so we can fold 781// a setne with 0 into a select. 782def : Pat<(select 783 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 784 (SELECT_V128 $lhs, $rhs, $cond)>; 785 786// And again, this time with seteq instead of setne and the arms reversed. 787def : Pat<(select 788 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 789 (SELECT_V128 $rhs, $lhs, $cond)>; 790} // foreach vec 791 792//===----------------------------------------------------------------------===// 793// Integer unary arithmetic 794//===----------------------------------------------------------------------===// 795 796multiclass SIMDUnaryInt<SDPatternOperator node, string name, bits<32> baseInst> { 797 defm "" : SIMDUnary<I8x16, node, name, baseInst>; 798 defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>; 799 defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>; 800 defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>; 801} 802 803// Integer vector negation 804def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>; 805 806// Integer absolute value: abs 807defm ABS : SIMDUnaryInt<abs, "abs", 96>; 808 809// Integer negation: neg 810defm NEG : SIMDUnaryInt<ivneg, "neg", 97>; 811 812// Population count: popcnt 813defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 0x62>; 814 815// Any lane true: any_true 816defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [], 817 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>; 818 819foreach vec = IntVecs in 820def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>; 821 822// All lanes true: all_true 823multiclass SIMDAllTrue<Vec vec, bits<32> simdop> { 824 defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 825 [(set I32:$dst, 826 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))], 827 vec.prefix#".all_true\t$dst, $vec", 828 vec.prefix#".all_true", simdop>; 829} 830 831defm "" : SIMDAllTrue<I8x16, 0x63>; 832defm "" : SIMDAllTrue<I16x8, 0x83>; 833defm "" : SIMDAllTrue<I32x4, 0xa3>; 834defm "" : SIMDAllTrue<I64x2, 0xc3>; 835 836// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1 837// can be folded out 838foreach reduction = 839 [["int_wasm_anytrue", "ANYTRUE", "I8x16"], 840 ["int_wasm_anytrue", "ANYTRUE", "I16x8"], 841 ["int_wasm_anytrue", "ANYTRUE", "I32x4"], 842 ["int_wasm_anytrue", "ANYTRUE", "I64x2"], 843 ["int_wasm_alltrue", "ALLTRUE_I8x16", "I8x16"], 844 ["int_wasm_alltrue", "ALLTRUE_I16x8", "I16x8"], 845 ["int_wasm_alltrue", "ALLTRUE_I32x4", "I32x4"], 846 ["int_wasm_alltrue", "ALLTRUE_I64x2", "I64x2"]] in { 847defvar intrinsic = !cast<Intrinsic>(reduction[0]); 848defvar inst = !cast<NI>(reduction[1]); 849defvar vec = !cast<Vec>(reduction[2]); 850def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>; 851def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>; 852def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>; 853} 854 855multiclass SIMDBitmask<Vec vec, bits<32> simdop> { 856 defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 857 [(set I32:$dst, 858 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))], 859 vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask", 860 simdop>; 861} 862 863defm BITMASK : SIMDBitmask<I8x16, 100>; 864defm BITMASK : SIMDBitmask<I16x8, 132>; 865defm BITMASK : SIMDBitmask<I32x4, 164>; 866defm BITMASK : SIMDBitmask<I64x2, 196>; 867 868//===----------------------------------------------------------------------===// 869// Bit shifts 870//===----------------------------------------------------------------------===// 871 872multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> { 873 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins), 874 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))], 875 vec.prefix#"."#name#"\t$dst, $vec, $x", 876 vec.prefix#"."#name, simdop>; 877} 878 879multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> { 880 defm "" : SIMDShift<I8x16, node, name, baseInst>; 881 defm "" : SIMDShift<I16x8, node, name, !add(baseInst, 32)>; 882 defm "" : SIMDShift<I32x4, node, name, !add(baseInst, 64)>; 883 defm "" : SIMDShift<I64x2, node, name, !add(baseInst, 96)>; 884} 885 886// WebAssembly SIMD shifts are nonstandard in that the shift amount is 887// an i32 rather than a vector, so they need custom nodes. 888def wasm_shift_t : 889 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; 890def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>; 891def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>; 892def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>; 893 894// Left shift by scalar: shl 895defm SHL : SIMDShiftInt<wasm_shl, "shl", 107>; 896 897// Right shift by scalar: shr_s / shr_u 898defm SHR_S : SIMDShiftInt<wasm_shr_s, "shr_s", 108>; 899defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>; 900 901// Optimize away an explicit mask on a shift count. 902def : Pat<(wasm_shl (v16i8 V128:$lhs), (and I32:$rhs, 7)), 903 (SHL_I8x16 V128:$lhs, I32:$rhs)>; 904def : Pat<(wasm_shr_s (v16i8 V128:$lhs), (and I32:$rhs, 7)), 905 (SHR_S_I8x16 V128:$lhs, I32:$rhs)>; 906def : Pat<(wasm_shr_u (v16i8 V128:$lhs), (and I32:$rhs, 7)), 907 (SHR_U_I8x16 V128:$lhs, I32:$rhs)>; 908 909def : Pat<(wasm_shl (v8i16 V128:$lhs), (and I32:$rhs, 15)), 910 (SHL_I16x8 V128:$lhs, I32:$rhs)>; 911def : Pat<(wasm_shr_s (v8i16 V128:$lhs), (and I32:$rhs, 15)), 912 (SHR_S_I16x8 V128:$lhs, I32:$rhs)>; 913def : Pat<(wasm_shr_u (v8i16 V128:$lhs), (and I32:$rhs, 15)), 914 (SHR_U_I16x8 V128:$lhs, I32:$rhs)>; 915 916def : Pat<(wasm_shl (v4i32 V128:$lhs), (and I32:$rhs, 31)), 917 (SHL_I32x4 V128:$lhs, I32:$rhs)>; 918def : Pat<(wasm_shr_s (v4i32 V128:$lhs), (and I32:$rhs, 31)), 919 (SHR_S_I32x4 V128:$lhs, I32:$rhs)>; 920def : Pat<(wasm_shr_u (v4i32 V128:$lhs), (and I32:$rhs, 31)), 921 (SHR_U_I32x4 V128:$lhs, I32:$rhs)>; 922 923def : Pat<(wasm_shl (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 924 (SHL_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 925def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 926 (SHR_S_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 927def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 928 (SHR_U_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 929 930//===----------------------------------------------------------------------===// 931// Integer binary arithmetic 932//===----------------------------------------------------------------------===// 933 934multiclass SIMDBinaryIntNoI8x16<SDPatternOperator node, string name, bits<32> baseInst> { 935 defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>; 936 defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>; 937 defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>; 938} 939 940multiclass SIMDBinaryIntSmall<SDPatternOperator node, string name, bits<32> baseInst> { 941 defm "" : SIMDBinary<I8x16, node, name, baseInst>; 942 defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>; 943} 944 945multiclass SIMDBinaryIntNoI64x2<SDPatternOperator node, string name, bits<32> baseInst> { 946 defm "" : SIMDBinaryIntSmall<node, name, baseInst>; 947 defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>; 948} 949 950multiclass SIMDBinaryInt<SDPatternOperator node, string name, bits<32> baseInst> { 951 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>; 952 defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>; 953} 954 955// Integer addition: add / add_sat_s / add_sat_u 956let isCommutable = 1 in { 957defm ADD : SIMDBinaryInt<add, "add", 110>; 958defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_sat_s", 111>; 959defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_sat_u", 112>; 960} // isCommutable = 1 961 962// Integer subtraction: sub / sub_sat_s / sub_sat_u 963defm SUB : SIMDBinaryInt<sub, "sub", 113>; 964defm SUB_SAT_S : 965 SIMDBinaryIntSmall<int_wasm_sub_sat_signed, "sub_sat_s", 114>; 966defm SUB_SAT_U : 967 SIMDBinaryIntSmall<int_wasm_sub_sat_unsigned, "sub_sat_u", 115>; 968 969// Integer multiplication: mul 970let isCommutable = 1 in 971defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>; 972 973// Integer min_s / min_u / max_s / max_u 974let isCommutable = 1 in { 975defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>; 976defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>; 977defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>; 978defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>; 979} // isCommutable = 1 980 981// Integer unsigned rounding average: avgr_u 982let isCommutable = 1 in { 983defm AVGR_U : SIMDBinary<I8x16, int_wasm_avgr_unsigned, "avgr_u", 123>; 984defm AVGR_U : SIMDBinary<I16x8, int_wasm_avgr_unsigned, "avgr_u", 155>; 985} 986 987def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), (add $lhs, $rhs), 988 "return N->getFlags().hasNoUnsignedWrap();">; 989 990foreach vec = [I8x16, I16x8] in { 991defvar inst = !cast<NI>("AVGR_U_"#vec); 992def : Pat<(wasm_shr_u 993 (add_nuw 994 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 995 (vec.splat (i32 1))), 996 (i32 1)), 997 (inst $lhs, $rhs)>; 998} 999 1000// Widening dot product: i32x4.dot_i16x8_s 1001let isCommutable = 1 in 1002defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 1003 [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))], 1004 "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s", 1005 186>; 1006 1007// Extending multiplication: extmul_{low,high}_P, extmul_high 1008multiclass SIMDExtBinary<Vec vec, Intrinsic node, string name, bits<32> simdop> { 1009 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 1010 (outs), (ins), 1011 [(set (vec.vt V128:$dst), (node 1012 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))], 1013 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 1014 vec.prefix#"."#name, simdop>; 1015} 1016 1017defm EXTMUL_LOW_S : 1018 SIMDExtBinary<I16x8, int_wasm_extmul_low_signed, "extmul_low_i8x16_s", 0x9c>; 1019defm EXTMUL_HIGH_S : 1020 SIMDExtBinary<I16x8, int_wasm_extmul_high_signed, "extmul_high_i8x16_s", 0x9d>; 1021defm EXTMUL_LOW_U : 1022 SIMDExtBinary<I16x8, int_wasm_extmul_low_unsigned, "extmul_low_i8x16_u", 0x9e>; 1023defm EXTMUL_HIGH_U : 1024 SIMDExtBinary<I16x8, int_wasm_extmul_high_unsigned, "extmul_high_i8x16_u", 0x9f>; 1025 1026defm EXTMUL_LOW_S : 1027 SIMDExtBinary<I32x4, int_wasm_extmul_low_signed, "extmul_low_i16x8_s", 0xbc>; 1028defm EXTMUL_HIGH_S : 1029 SIMDExtBinary<I32x4, int_wasm_extmul_high_signed, "extmul_high_i16x8_s", 0xbd>; 1030defm EXTMUL_LOW_U : 1031 SIMDExtBinary<I32x4, int_wasm_extmul_low_unsigned, "extmul_low_i16x8_u", 0xbe>; 1032defm EXTMUL_HIGH_U : 1033 SIMDExtBinary<I32x4, int_wasm_extmul_high_unsigned, "extmul_high_i16x8_u", 0xbf>; 1034 1035defm EXTMUL_LOW_S : 1036 SIMDExtBinary<I64x2, int_wasm_extmul_low_signed, "extmul_low_i32x4_s", 0xdc>; 1037defm EXTMUL_HIGH_S : 1038 SIMDExtBinary<I64x2, int_wasm_extmul_high_signed, "extmul_high_i32x4_s", 0xdd>; 1039defm EXTMUL_LOW_U : 1040 SIMDExtBinary<I64x2, int_wasm_extmul_low_unsigned, "extmul_low_i32x4_u", 0xde>; 1041defm EXTMUL_HIGH_U : 1042 SIMDExtBinary<I64x2, int_wasm_extmul_high_unsigned, "extmul_high_i32x4_u", 0xdf>; 1043 1044//===----------------------------------------------------------------------===// 1045// Floating-point unary arithmetic 1046//===----------------------------------------------------------------------===// 1047 1048multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> { 1049 defm "" : SIMDUnary<F32x4, node, name, baseInst>; 1050 defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>; 1051} 1052 1053// Absolute value: abs 1054defm ABS : SIMDUnaryFP<fabs, "abs", 224>; 1055 1056// Negation: neg 1057defm NEG : SIMDUnaryFP<fneg, "neg", 225>; 1058 1059// Square root: sqrt 1060defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>; 1061 1062// Rounding: ceil, floor, trunc, nearest 1063defm CEIL : SIMDUnary<F32x4, fceil, "ceil", 0x67>; 1064defm FLOOR : SIMDUnary<F32x4, ffloor, "floor", 0x68>; 1065defm TRUNC: SIMDUnary<F32x4, ftrunc, "trunc", 0x69>; 1066defm NEAREST: SIMDUnary<F32x4, fnearbyint, "nearest", 0x6a>; 1067defm CEIL : SIMDUnary<F64x2, fceil, "ceil", 0x74>; 1068defm FLOOR : SIMDUnary<F64x2, ffloor, "floor", 0x75>; 1069defm TRUNC: SIMDUnary<F64x2, ftrunc, "trunc", 0x7a>; 1070defm NEAREST: SIMDUnary<F64x2, fnearbyint, "nearest", 0x94>; 1071 1072//===----------------------------------------------------------------------===// 1073// Floating-point binary arithmetic 1074//===----------------------------------------------------------------------===// 1075 1076multiclass SIMDBinaryFP<SDPatternOperator node, string name, bits<32> baseInst> { 1077 defm "" : SIMDBinary<F32x4, node, name, baseInst>; 1078 defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>; 1079} 1080 1081// Addition: add 1082let isCommutable = 1 in 1083defm ADD : SIMDBinaryFP<fadd, "add", 228>; 1084 1085// Subtraction: sub 1086defm SUB : SIMDBinaryFP<fsub, "sub", 229>; 1087 1088// Multiplication: mul 1089let isCommutable = 1 in 1090defm MUL : SIMDBinaryFP<fmul, "mul", 230>; 1091 1092// Division: div 1093defm DIV : SIMDBinaryFP<fdiv, "div", 231>; 1094 1095// NaN-propagating minimum: min 1096defm MIN : SIMDBinaryFP<fminimum, "min", 232>; 1097 1098// NaN-propagating maximum: max 1099defm MAX : SIMDBinaryFP<fmaximum, "max", 233>; 1100 1101// Pseudo-minimum: pmin 1102defm PMIN : SIMDBinaryFP<int_wasm_pmin, "pmin", 234>; 1103 1104// Pseudo-maximum: pmax 1105defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>; 1106 1107//===----------------------------------------------------------------------===// 1108// Conversions 1109//===----------------------------------------------------------------------===// 1110 1111multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name, 1112 bits<32> simdop> { 1113 defm op#_#vec : 1114 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 1115 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))], 1116 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>; 1117} 1118 1119// Floating point to integer with saturation: trunc_sat 1120defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>; 1121defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>; 1122 1123// Support the saturating variety as well. 1124def trunc_s_sat32 : PatFrag<(ops node:$x), (fp_to_sint_sat $x, i32)>; 1125def trunc_u_sat32 : PatFrag<(ops node:$x), (fp_to_uint_sat $x, i32)>; 1126def : Pat<(v4i32 (trunc_s_sat32 (v4f32 V128:$src))), (fp_to_sint_I32x4 $src)>; 1127def : Pat<(v4i32 (trunc_u_sat32 (v4f32 V128:$src))), (fp_to_uint_I32x4 $src)>; 1128 1129def trunc_sat_zero_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1130def trunc_sat_zero_s : 1131 SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_S", trunc_sat_zero_t>; 1132def trunc_sat_zero_u : 1133 SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_U", trunc_sat_zero_t>; 1134defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_s, "trunc_sat_zero_f64x2_s", 1135 0xfc>; 1136defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_u, "trunc_sat_zero_f64x2_u", 1137 0xfd>; 1138 1139// Integer to floating point: convert 1140def convert_low_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1141def convert_low_s : SDNode<"WebAssemblyISD::CONVERT_LOW_S", convert_low_t>; 1142def convert_low_u : SDNode<"WebAssemblyISD::CONVERT_LOW_U", convert_low_t>; 1143defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>; 1144defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>; 1145defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>; 1146defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>; 1147 1148// Extending operations 1149def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1150def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>; 1151def extend_high_s : SDNode<"WebAssemblyISD::EXTEND_HIGH_S", extend_t>; 1152def extend_low_u : SDNode<"WebAssemblyISD::EXTEND_LOW_U", extend_t>; 1153def extend_high_u : SDNode<"WebAssemblyISD::EXTEND_HIGH_U", extend_t>; 1154 1155// TODO: refactor this to be uniform for i64x2 if the numbering is not changed. 1156multiclass SIMDExtend<Vec vec, bits<32> baseInst> { 1157 defm "" : SIMDConvert<vec, vec.split, extend_low_s, 1158 "extend_low_"#vec.split.prefix#"_s", baseInst>; 1159 defm "" : SIMDConvert<vec, vec.split, extend_high_s, 1160 "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>; 1161 defm "" : SIMDConvert<vec, vec.split, extend_low_u, 1162 "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>; 1163 defm "" : SIMDConvert<vec, vec.split, extend_high_u, 1164 "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>; 1165} 1166 1167defm "" : SIMDExtend<I16x8, 0x87>; 1168defm "" : SIMDExtend<I32x4, 0xa7>; 1169defm "" : SIMDExtend<I64x2, 0xc7>; 1170 1171// Narrowing operations 1172multiclass SIMDNarrow<Vec vec, bits<32> baseInst> { 1173 defvar name = vec.split.prefix#".narrow_"#vec.prefix; 1174 defm NARROW_S_#vec.split : 1175 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1176 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed 1177 (vec.vt V128:$low), (vec.vt V128:$high))))], 1178 name#"_s\t$dst, $low, $high", name#"_s", baseInst>; 1179 defm NARROW_U_#vec.split : 1180 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1181 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned 1182 (vec.vt V128:$low), (vec.vt V128:$high))))], 1183 name#"_u\t$dst, $low, $high", name#"_u", !add(baseInst, 1)>; 1184} 1185 1186defm "" : SIMDNarrow<I16x8, 101>; 1187defm "" : SIMDNarrow<I32x4, 133>; 1188 1189// Use narrowing operations for truncating stores. Since the narrowing 1190// operations are saturating instead of truncating, we need to mask 1191// the stored values first. 1192def store_v8i8_trunc_v8i16 : 1193 OutPatFrag<(ops node:$val), 1194 (EXTRACT_LANE_I64x2 1195 (NARROW_U_I8x16 1196 (AND 1197 (CONST_V128_I16x8 1198 0x00ff, 0x00ff, 0x00ff, 0x00ff, 1199 0x00ff, 0x00ff, 0x00ff, 0x00ff), 1200 node:$val), 1201 $val), // Unused input 1202 0)>; 1203 1204def store_v4i16_trunc_v4i32 : 1205 OutPatFrag<(ops node:$val), 1206 (EXTRACT_LANE_I64x2 1207 (NARROW_U_I16x8 1208 (AND 1209 (CONST_V128_I32x4 1210 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff), 1211 node:$val), 1212 $val), // Unused input 1213 0)>; 1214 1215// Store patterns adapted from WebAssemblyInstrMemory.td 1216multiclass NarrowingStorePatNoOffset<Vec vec, OutPatFrag out> { 1217 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1218 def : Pat<(node vec.vt:$val, I32:$addr), 1219 (STORE_I64_A32 0, 0, $addr, (out $val))>, 1220 Requires<[HasAddr32]>; 1221 def : Pat<(node vec.vt:$val, I64:$addr), 1222 (STORE_I64_A64 0, 0, $addr, (out $val))>, 1223 Requires<[HasAddr64]>; 1224} 1225 1226defm : NarrowingStorePatNoOffset<I16x8, store_v8i8_trunc_v8i16>; 1227defm : NarrowingStorePatNoOffset<I32x4, store_v4i16_trunc_v4i32>; 1228 1229multiclass NarrowingStorePatImmOff<Vec vec, PatFrag operand, OutPatFrag out> { 1230 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1231 def : Pat<(node vec.vt:$val, (operand I32:$addr, imm:$off)), 1232 (STORE_I64_A32 0, imm:$off, $addr, (out $val))>, 1233 Requires<[HasAddr32]>; 1234 def : Pat<(node vec.vt:$val, (operand I64:$addr, imm:$off)), 1235 (STORE_I64_A64 0, imm:$off, $addr, (out $val))>, 1236 Requires<[HasAddr64]>; 1237} 1238 1239defm : NarrowingStorePatImmOff<I16x8, regPlusImm, store_v8i8_trunc_v8i16>; 1240defm : NarrowingStorePatImmOff<I32x4, regPlusImm, store_v4i16_trunc_v4i32>; 1241defm : NarrowingStorePatImmOff<I16x8, or_is_add, store_v8i8_trunc_v8i16>; 1242defm : NarrowingStorePatImmOff<I32x4, or_is_add, store_v4i16_trunc_v4i32>; 1243 1244multiclass NarrowingStorePatOffsetOnly<Vec vec, OutPatFrag out> { 1245 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1246 def : Pat<(node vec.vt:$val, imm:$off), 1247 (STORE_I64_A32 0, imm:$off, (CONST_I32 0), (out $val))>, 1248 Requires<[HasAddr32]>; 1249 def : Pat<(node vec.vt:$val, imm:$off), 1250 (STORE_I64_A64 0, imm:$off, (CONST_I64 0), (out $val))>, 1251 Requires<[HasAddr64]>; 1252} 1253 1254defm : NarrowingStorePatOffsetOnly<I16x8, store_v8i8_trunc_v8i16>; 1255defm : NarrowingStorePatOffsetOnly<I32x4, store_v4i16_trunc_v4i32>; 1256 1257multiclass NarrowingStorePatGlobalAddrOffOnly<Vec vec, OutPatFrag out> { 1258 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1259 def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)), 1260 (STORE_I64_A32 0, tglobaladdr:$off, (CONST_I32 0), (out $val))>, 1261 Requires<[IsNotPIC, HasAddr32]>; 1262 def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)), 1263 (STORE_I64_A64 0, tglobaladdr:$off, (CONST_I64 0), (out $val))>, 1264 Requires<[IsNotPIC, HasAddr64]>; 1265} 1266 1267defm : NarrowingStorePatGlobalAddrOffOnly<I16x8, store_v8i8_trunc_v8i16>; 1268defm : NarrowingStorePatGlobalAddrOffOnly<I32x4, store_v4i16_trunc_v4i32>; 1269 1270// Bitcasts are nops 1271// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types 1272foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 1273foreach t2 = !foldl( 1274 []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 1275 acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)), 1276 acc, !listconcat(acc, [cur]) 1277 ) 1278) in 1279def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>; 1280 1281// Extended pairwise addition 1282defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed, 1283 "extadd_pairwise_i8x16_s", 0x7c>; 1284defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned, 1285 "extadd_pairwise_i8x16_u", 0x7d>; 1286defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed, 1287 "extadd_pairwise_i16x8_s", 0x7e>; 1288defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned, 1289 "extadd_pairwise_i16x8_u", 0x7f>; 1290 1291// Prototype f64x2 conversions 1292defm "" : SIMDConvert<F32x4, F64x2, int_wasm_demote_zero, 1293 "demote_zero_f64x2", 0x5e>; 1294defm "" : SIMDConvert<F64x2, F32x4, int_wasm_promote_low, 1295 "promote_low_f32x4", 0x5f>; 1296 1297//===----------------------------------------------------------------------===// 1298// Saturating Rounding Q-Format Multiplication 1299//===----------------------------------------------------------------------===// 1300 1301defm Q15MULR_SAT_S : 1302 SIMDBinary<I16x8, int_wasm_q15mulr_sat_signed, "q15mulr_sat_s", 0x82>; 1303