1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly SIMD operand code-gen constructs. 11/// 12//===----------------------------------------------------------------------===// 13 14// Instructions requiring HasSIMD128 and the simd128 prefix byte 15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 16 list<dag> pattern_r, string asmstr_r = "", 17 string asmstr_s = "", bits<32> simdop = -1> { 18 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 19 !if(!ge(simdop, 0x100), 20 !or(0xfd0000, !and(0xffff, simdop)), 21 !or(0xfd00, !and(0xff, simdop)))>, 22 Requires<[HasSIMD128]>; 23} 24 25defm "" : ARGUMENT<V128, v16i8>; 26defm "" : ARGUMENT<V128, v8i16>; 27defm "" : ARGUMENT<V128, v4i32>; 28defm "" : ARGUMENT<V128, v2i64>; 29defm "" : ARGUMENT<V128, v4f32>; 30defm "" : ARGUMENT<V128, v2f64>; 31 32// Constrained immediate argument types 33foreach SIZE = [8, 16] in 34def ImmI#SIZE : ImmLeaf<i32, 35 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));" 36>; 37foreach SIZE = [2, 4, 8, 16, 32] in 38def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; 39 40//===----------------------------------------------------------------------===// 41// Load and store 42//===----------------------------------------------------------------------===// 43 44// Load: v128.load 45let mayLoad = 1, UseNamedOperandTable = 1 in { 46defm LOAD_V128_A32 : 47 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 48 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 49 "v128.load\t$dst, ${off}(${addr})$p2align", 50 "v128.load\t$off$p2align", 0>; 51defm LOAD_V128_A64 : 52 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 53 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 54 "v128.load\t$dst, ${off}(${addr})$p2align", 55 "v128.load\t$off$p2align", 0>; 56} 57 58// Def load patterns from WebAssemblyInstrMemory.td for vector types 59foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 60defm : LoadPatNoOffset<vec_t, load, "LOAD_V128">; 61defm : LoadPatImmOff<vec_t, load, regPlusImm, "LOAD_V128">; 62defm : LoadPatImmOff<vec_t, load, or_is_add, "LOAD_V128">; 63defm : LoadPatOffsetOnly<vec_t, load, "LOAD_V128">; 64defm : LoadPatGlobalAddrOffOnly<vec_t, load, "LOAD_V128">; 65} 66 67// vNxM.load_splat 68multiclass SIMDLoadSplat<string vec, bits<32> simdop> { 69 let mayLoad = 1, UseNamedOperandTable = 1 in { 70 defm LOAD_SPLAT_#vec#_A32 : 71 SIMD_I<(outs V128:$dst), 72 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 73 (outs), 74 (ins P2Align:$p2align, offset32_op:$off), [], 75 vec#".load_splat\t$dst, ${off}(${addr})$p2align", 76 vec#".load_splat\t$off$p2align", simdop>; 77 defm LOAD_SPLAT_#vec#_A64 : 78 SIMD_I<(outs V128:$dst), 79 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 80 (outs), 81 (ins P2Align:$p2align, offset64_op:$off), [], 82 vec#".load_splat\t$dst, ${off}(${addr})$p2align", 83 vec#".load_splat\t$off$p2align", simdop>; 84 } 85} 86 87defm "" : SIMDLoadSplat<"v8x16", 7>; 88defm "" : SIMDLoadSplat<"v16x8", 8>; 89defm "" : SIMDLoadSplat<"v32x4", 9>; 90defm "" : SIMDLoadSplat<"v64x2", 10>; 91 92def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>; 93def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t, 94 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 95def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>; 96 97foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"], 98 ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in { 99defm : LoadPatNoOffset<!cast<ValueType>(args[0]), 100 load_splat, 101 "LOAD_SPLAT_"#args[1]>; 102defm : LoadPatImmOff<!cast<ValueType>(args[0]), 103 load_splat, 104 regPlusImm, 105 "LOAD_SPLAT_"#args[1]>; 106defm : LoadPatImmOff<!cast<ValueType>(args[0]), 107 load_splat, 108 or_is_add, 109 "LOAD_SPLAT_"#args[1]>; 110defm : LoadPatOffsetOnly<!cast<ValueType>(args[0]), 111 load_splat, 112 "LOAD_SPLAT_"#args[1]>; 113defm : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]), 114 load_splat, 115 "LOAD_SPLAT_"#args[1]>; 116} 117 118// Load and extend 119multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> { 120 let mayLoad = 1, UseNamedOperandTable = 1 in { 121 defm LOAD_EXTEND_S_#vec_t#_A32 : 122 SIMD_I<(outs V128:$dst), 123 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 124 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 125 name#"_s\t$dst, ${off}(${addr})$p2align", 126 name#"_s\t$off$p2align", simdop>; 127 defm LOAD_EXTEND_U_#vec_t#_A32 : 128 SIMD_I<(outs V128:$dst), 129 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 130 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 131 name#"_u\t$dst, ${off}(${addr})$p2align", 132 name#"_u\t$off$p2align", !add(simdop, 1)>; 133 defm LOAD_EXTEND_S_#vec_t#_A64 : 134 SIMD_I<(outs V128:$dst), 135 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 136 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 137 name#"_s\t$dst, ${off}(${addr})$p2align", 138 name#"_s\t$off$p2align", simdop>; 139 defm LOAD_EXTEND_U_#vec_t#_A64 : 140 SIMD_I<(outs V128:$dst), 141 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 142 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 143 name#"_u\t$dst, ${off}(${addr})$p2align", 144 name#"_u\t$off$p2align", !add(simdop, 1)>; 145 } 146} 147 148defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 1>; 149defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 3>; 150defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 5>; 151 152foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in 153foreach exts = [["sextloadv", "_S"], 154 ["zextloadv", "_U"], 155 ["extloadv", "_U"]] in { 156defm : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]), 157 "LOAD_EXTEND"#exts[1]#"_"#types[0]>; 158defm : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm, 159 "LOAD_EXTEND"#exts[1]#"_"#types[0]>; 160defm : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add, 161 "LOAD_EXTEND"#exts[1]#"_"#types[0]>; 162defm : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]), 163 "LOAD_EXTEND"#exts[1]#"_"#types[0]>; 164defm : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]), 165 "LOAD_EXTEND"#exts[1]#"_"#types[0]>; 166} 167 168// Load lane into zero vector 169multiclass SIMDLoadZero<ValueType vec_t, string name, bits<32> simdop> { 170 let mayLoad = 1, UseNamedOperandTable = 1 in { 171 defm LOAD_ZERO_#vec_t#_A32 : 172 SIMD_I<(outs V128:$dst), 173 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 174 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 175 name#"\t$dst, ${off}(${addr})$p2align", 176 name#"\t$off$p2align", simdop>; 177 defm LOAD_ZERO_#vec_t#_A64 : 178 SIMD_I<(outs V128:$dst), 179 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 180 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 181 name#"\t$dst, ${off}(${addr})$p2align", 182 name#"\t$off$p2align", simdop>; 183 } // mayLoad = 1, UseNamedOperandTable = 1 184} 185 186// TODO: Also support v4f32 and v2f64 once the instructions are merged 187// to the proposal 188defm "" : SIMDLoadZero<v4i32, "v128.load32_zero", 252>; 189defm "" : SIMDLoadZero<v2i64, "v128.load64_zero", 253>; 190 191defm : LoadPatNoOffset<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">; 192defm : LoadPatNoOffset<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">; 193 194defm : LoadPatImmOff<v4i32, int_wasm_load32_zero, regPlusImm, "LOAD_ZERO_v4i32">; 195defm : LoadPatImmOff<v2i64, int_wasm_load64_zero, regPlusImm, "LOAD_ZERO_v2i64">; 196 197defm : LoadPatImmOff<v4i32, int_wasm_load32_zero, or_is_add, "LOAD_ZERO_v4i32">; 198defm : LoadPatImmOff<v2i64, int_wasm_load64_zero, or_is_add, "LOAD_ZERO_v2i64">; 199 200defm : LoadPatOffsetOnly<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">; 201defm : LoadPatOffsetOnly<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">; 202 203defm : LoadPatGlobalAddrOffOnly<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">; 204defm : LoadPatGlobalAddrOffOnly<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">; 205 206// Load lane 207multiclass SIMDLoadLane<ValueType vec_t, string name, bits<32> simdop> { 208 let mayLoad = 1, UseNamedOperandTable = 1 in { 209 defm LOAD_LANE_#vec_t#_A32 : 210 SIMD_I<(outs V128:$dst), 211 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 212 I32:$addr, V128:$vec), 213 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 214 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 215 name#"\t$off$p2align, $idx", simdop>; 216 defm LOAD_LANE_#vec_t#_A64 : 217 SIMD_I<(outs V128:$dst), 218 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 219 I64:$addr, V128:$vec), 220 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 221 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 222 name#"\t$off$p2align, $idx", simdop>; 223 } // mayLoad = 1, UseNamedOperandTable = 1 224} 225 226// TODO: Also support v4f32 and v2f64 once the instructions are merged 227// to the proposal 228defm "" : SIMDLoadLane<v16i8, "v128.load8_lane", 88>; 229defm "" : SIMDLoadLane<v8i16, "v128.load16_lane", 89>; 230defm "" : SIMDLoadLane<v4i32, "v128.load32_lane", 90>; 231defm "" : SIMDLoadLane<v2i64, "v128.load64_lane", 91>; 232 233// Select loads with no constant offset. 234multiclass LoadLanePatNoOffset<ValueType ty, PatFrag kind, ImmLeaf lane_imm_t> { 235 def : Pat<(ty (kind (i32 I32:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx))), 236 (!cast<NI>("LOAD_LANE_"#ty#"_A32") 0, 0, imm:$idx, I32:$addr, V128:$vec)>, 237 Requires<[HasAddr32]>; 238 def : Pat<(ty (kind (i64 I64:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx))), 239 (!cast<NI>("LOAD_LANE_"#ty#"_A64") 0, 0, imm:$idx, I64:$addr, V128:$vec)>, 240 Requires<[HasAddr64]>; 241} 242 243defm : LoadLanePatNoOffset<v16i8, int_wasm_load8_lane, LaneIdx16>; 244defm : LoadLanePatNoOffset<v8i16, int_wasm_load16_lane, LaneIdx8>; 245defm : LoadLanePatNoOffset<v4i32, int_wasm_load32_lane, LaneIdx4>; 246defm : LoadLanePatNoOffset<v2i64, int_wasm_load64_lane, LaneIdx2>; 247 248// TODO: Also support the other load patterns for load_lane once the instructions 249// are merged to the proposal. 250 251// Store: v128.store 252let mayStore = 1, UseNamedOperandTable = 1 in { 253defm STORE_V128_A32 : 254 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec), 255 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 256 "v128.store\t${off}(${addr})$p2align, $vec", 257 "v128.store\t$off$p2align", 11>; 258defm STORE_V128_A64 : 259 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec), 260 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 261 "v128.store\t${off}(${addr})$p2align, $vec", 262 "v128.store\t$off$p2align", 11>; 263} 264 265// Def store patterns from WebAssemblyInstrMemory.td for vector types 266foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 267defm : StorePatNoOffset<vec_t, store, "STORE_V128">; 268defm : StorePatImmOff<vec_t, store, regPlusImm, "STORE_V128">; 269defm : StorePatImmOff<vec_t, store, or_is_add, "STORE_V128">; 270defm : StorePatOffsetOnly<vec_t, store, "STORE_V128">; 271defm : StorePatGlobalAddrOffOnly<vec_t, store, "STORE_V128">; 272} 273 274// Store lane 275multiclass SIMDStoreLane<ValueType vec_t, string name, bits<32> simdop> { 276 let mayStore = 1, UseNamedOperandTable = 1 in { 277 defm STORE_LANE_#vec_t#_A32 : 278 SIMD_I<(outs), 279 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 280 I32:$addr, V128:$vec), 281 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 282 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 283 name#"\t$off$p2align, $idx", simdop>; 284 defm STORE_LANE_#vec_t#_A64 : 285 SIMD_I<(outs V128:$dst), 286 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 287 I64:$addr, V128:$vec), 288 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 289 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 290 name#"\t$off$p2align, $idx", simdop>; 291 } // mayStore = 1, UseNamedOperandTable = 1 292} 293 294// TODO: Also support v4f32 and v2f64 once the instructions are merged 295// to the proposal 296defm "" : SIMDStoreLane<v16i8, "v128.store8_lane", 92>; 297defm "" : SIMDStoreLane<v8i16, "v128.store16_lane", 93>; 298defm "" : SIMDStoreLane<v4i32, "v128.store32_lane", 94>; 299defm "" : SIMDStoreLane<v2i64, "v128.store64_lane", 95>; 300 301// Select stores with no constant offset. 302multiclass StoreLanePatNoOffset<ValueType ty, PatFrag kind, ImmLeaf lane_imm_t> { 303 def : Pat<(kind (i32 I32:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx)), 304 (!cast<NI>("STORE_LANE_"#ty#"_A32") 305 0, 0, imm:$idx, I32:$addr, ty:$vec)>, 306 Requires<[HasAddr32]>; 307 def : Pat<(kind (i64 I64:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx)), 308 (!cast<NI>("STORE_LANE_"#ty#"_A64") 309 0, 0, imm:$idx, I64:$addr, ty:$vec)>, 310 Requires<[HasAddr64]>; 311} 312 313defm : StoreLanePatNoOffset<v16i8, int_wasm_store8_lane, LaneIdx16>; 314defm : StoreLanePatNoOffset<v8i16, int_wasm_store16_lane, LaneIdx8>; 315defm : StoreLanePatNoOffset<v4i32, int_wasm_store32_lane, LaneIdx4>; 316defm : StoreLanePatNoOffset<v2i64, int_wasm_store64_lane, LaneIdx2>; 317 318// TODO: Also support the other store patterns for store_lane once the 319// instructions are merged to the proposal. 320 321//===----------------------------------------------------------------------===// 322// Constructing SIMD values 323//===----------------------------------------------------------------------===// 324 325// Constant: v128.const 326multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { 327 let isMoveImm = 1, isReMaterializable = 1, 328 Predicates = [HasUnimplementedSIMD128] in 329 defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, 330 [(set V128:$dst, (vec_t pat))], 331 "v128.const\t$dst, "#args, 332 "v128.const\t"#args, 12>; 333} 334 335defm "" : ConstVec<v16i8, 336 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, 337 vec_i8imm_op:$i2, vec_i8imm_op:$i3, 338 vec_i8imm_op:$i4, vec_i8imm_op:$i5, 339 vec_i8imm_op:$i6, vec_i8imm_op:$i7, 340 vec_i8imm_op:$i8, vec_i8imm_op:$i9, 341 vec_i8imm_op:$iA, vec_i8imm_op:$iB, 342 vec_i8imm_op:$iC, vec_i8imm_op:$iD, 343 vec_i8imm_op:$iE, vec_i8imm_op:$iF), 344 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, 345 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, 346 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, 347 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), 348 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", 349 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; 350defm "" : ConstVec<v8i16, 351 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, 352 vec_i16imm_op:$i2, vec_i16imm_op:$i3, 353 vec_i16imm_op:$i4, vec_i16imm_op:$i5, 354 vec_i16imm_op:$i6, vec_i16imm_op:$i7), 355 (build_vector 356 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, 357 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), 358 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; 359let IsCanonical = 1 in 360defm "" : ConstVec<v4i32, 361 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, 362 vec_i32imm_op:$i2, vec_i32imm_op:$i3), 363 (build_vector (i32 imm:$i0), (i32 imm:$i1), 364 (i32 imm:$i2), (i32 imm:$i3)), 365 "$i0, $i1, $i2, $i3">; 366defm "" : ConstVec<v2i64, 367 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), 368 (build_vector (i64 imm:$i0), (i64 imm:$i1)), 369 "$i0, $i1">; 370defm "" : ConstVec<v4f32, 371 (ins f32imm_op:$i0, f32imm_op:$i1, 372 f32imm_op:$i2, f32imm_op:$i3), 373 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), 374 (f32 fpimm:$i2), (f32 fpimm:$i3)), 375 "$i0, $i1, $i2, $i3">; 376defm "" : ConstVec<v2f64, 377 (ins f64imm_op:$i0, f64imm_op:$i1), 378 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), 379 "$i0, $i1">; 380 381// Shuffle lanes: shuffle 382defm SHUFFLE : 383 SIMD_I<(outs V128:$dst), 384 (ins V128:$x, V128:$y, 385 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 386 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 387 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 388 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 389 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 390 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 391 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 392 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 393 (outs), 394 (ins 395 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 396 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 397 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 398 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 399 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 400 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 401 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 402 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 403 [], 404 "v8x16.shuffle\t$dst, $x, $y, "# 405 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 406 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 407 "v8x16.shuffle\t"# 408 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 409 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 410 13>; 411 412// Shuffles after custom lowering 413def wasm_shuffle_t : SDTypeProfile<1, 18, []>; 414def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; 415foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 416def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y), 417 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 418 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 419 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 420 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 421 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 422 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 423 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 424 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))), 425 (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y), 426 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 427 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 428 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 429 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 430 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 431 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 432 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 433 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>; 434} 435 436// Swizzle lanes: v8x16.swizzle 437def wasm_swizzle_t : SDTypeProfile<1, 2, []>; 438def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>; 439defm SWIZZLE : 440 SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 441 [(set (v16i8 V128:$dst), 442 (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 443 "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 14>; 444 445def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)), 446 (SWIZZLE V128:$src, V128:$mask)>; 447 448// Create vector with identical lanes: splat 449def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>; 450def splat4 : PatFrag<(ops node:$x), (build_vector 451 node:$x, node:$x, node:$x, node:$x)>; 452def splat8 : PatFrag<(ops node:$x), (build_vector 453 node:$x, node:$x, node:$x, node:$x, 454 node:$x, node:$x, node:$x, node:$x)>; 455def splat16 : PatFrag<(ops node:$x), (build_vector 456 node:$x, node:$x, node:$x, node:$x, 457 node:$x, node:$x, node:$x, node:$x, 458 node:$x, node:$x, node:$x, node:$x, 459 node:$x, node:$x, node:$x, node:$x)>; 460 461multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t, 462 PatFrag splat_pat, bits<32> simdop> { 463 defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins), 464 [(set (vec_t V128:$dst), (splat_pat reg_t:$x))], 465 vec#".splat\t$dst, $x", vec#".splat", simdop>; 466} 467 468defm "" : Splat<v16i8, "i8x16", I32, splat16, 15>; 469defm "" : Splat<v8i16, "i16x8", I32, splat8, 16>; 470defm "" : Splat<v4i32, "i32x4", I32, splat4, 17>; 471defm "" : Splat<v2i64, "i64x2", I64, splat2, 18>; 472defm "" : Splat<v4f32, "f32x4", F32, splat4, 19>; 473defm "" : Splat<v2f64, "f64x2", F64, splat2, 20>; 474 475// scalar_to_vector leaves high lanes undefined, so can be a splat 476class ScalarSplatPat<ValueType vec_t, ValueType lane_t, 477 WebAssemblyRegClass reg_t> : 478 Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))), 479 (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>; 480 481def : ScalarSplatPat<v16i8, i32, I32>; 482def : ScalarSplatPat<v8i16, i32, I32>; 483def : ScalarSplatPat<v4i32, i32, I32>; 484def : ScalarSplatPat<v2i64, i64, I64>; 485def : ScalarSplatPat<v4f32, f32, F32>; 486def : ScalarSplatPat<v2f64, f64, F64>; 487 488//===----------------------------------------------------------------------===// 489// Accessing lanes 490//===----------------------------------------------------------------------===// 491 492// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u 493multiclass ExtractLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t, 494 bits<32> simdop, string suffix = ""> { 495 defm EXTRACT_LANE_#vec_t#suffix : 496 SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx), 497 (outs), (ins vec_i8imm_op:$idx), [], 498 vec#".extract_lane"#suffix#"\t$dst, $vec, $idx", 499 vec#".extract_lane"#suffix#"\t$idx", simdop>; 500} 501 502defm "" : ExtractLane<v16i8, "i8x16", I32, 21, "_s">; 503defm "" : ExtractLane<v16i8, "i8x16", I32, 22, "_u">; 504defm "" : ExtractLane<v8i16, "i16x8", I32, 24, "_s">; 505defm "" : ExtractLane<v8i16, "i16x8", I32, 25, "_u">; 506defm "" : ExtractLane<v4i32, "i32x4", I32, 27>; 507defm "" : ExtractLane<v2i64, "i64x2", I64, 29>; 508defm "" : ExtractLane<v4f32, "f32x4", F32, 31>; 509defm "" : ExtractLane<v2f64, "f64x2", F64, 33>; 510 511def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), 512 (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>; 513def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), 514 (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>; 515def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)), 516 (EXTRACT_LANE_v4i32 V128:$vec, imm:$idx)>; 517def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)), 518 (EXTRACT_LANE_v4f32 V128:$vec, imm:$idx)>; 519def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)), 520 (EXTRACT_LANE_v2i64 V128:$vec, imm:$idx)>; 521def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)), 522 (EXTRACT_LANE_v2f64 V128:$vec, imm:$idx)>; 523 524def : Pat< 525 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8), 526 (EXTRACT_LANE_v16i8_s V128:$vec, imm:$idx)>; 527def : Pat< 528 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)), 529 (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>; 530def : Pat< 531 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16), 532 (EXTRACT_LANE_v8i16_s V128:$vec, imm:$idx)>; 533def : Pat< 534 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)), 535 (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>; 536 537// Replace lane value: replace_lane 538multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t, 539 WebAssemblyRegClass reg_t, ValueType lane_t, 540 bits<32> simdop> { 541 defm REPLACE_LANE_#vec_t : 542 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x), 543 (outs), (ins vec_i8imm_op:$idx), 544 [(set V128:$dst, (vector_insert 545 (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))], 546 vec#".replace_lane\t$dst, $vec, $idx, $x", 547 vec#".replace_lane\t$idx", simdop>; 548} 549 550defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 23>; 551defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 26>; 552defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 28>; 553defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 30>; 554defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 32>; 555defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 34>; 556 557// Lower undef lane indices to zero 558def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef), 559 (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>; 560def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef), 561 (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>; 562def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef), 563 (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>; 564def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef), 565 (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>; 566def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef), 567 (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>; 568def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), 569 (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>; 570 571//===----------------------------------------------------------------------===// 572// Comparisons 573//===----------------------------------------------------------------------===// 574 575multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec, 576 string name, CondCode cond, bits<32> simdop> { 577 defm _#vec_t : 578 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 579 [(set (out_t V128:$dst), 580 (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond) 581 )], 582 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>; 583} 584 585multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { 586 defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>; 587 defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond, 588 !add(baseInst, 10)>; 589 defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond, 590 !add(baseInst, 20)>; 591} 592 593multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { 594 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>; 595 defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond, 596 !add(baseInst, 6)>; 597} 598 599// Equality: eq 600let isCommutable = 1 in { 601defm EQ : SIMDConditionInt<"eq", SETEQ, 35>; 602defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>; 603} // isCommutable = 1 604 605// Non-equality: ne 606let isCommutable = 1 in { 607defm NE : SIMDConditionInt<"ne", SETNE, 36>; 608defm NE : SIMDConditionFP<"ne", SETUNE, 66>; 609} // isCommutable = 1 610 611// Less than: lt_s / lt_u / lt 612defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>; 613defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>; 614defm LT : SIMDConditionFP<"lt", SETOLT, 67>; 615 616// Greater than: gt_s / gt_u / gt 617defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>; 618defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>; 619defm GT : SIMDConditionFP<"gt", SETOGT, 68>; 620 621// Less than or equal: le_s / le_u / le 622defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>; 623defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>; 624defm LE : SIMDConditionFP<"le", SETOLE, 69>; 625 626// Greater than or equal: ge_s / ge_u / ge 627defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>; 628defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>; 629defm GE : SIMDConditionFP<"ge", SETOGE, 70>; 630 631// Lower float comparisons that don't care about NaN to standard WebAssembly 632// float comparisons. These instructions are generated with nnan and in the 633// target-independent expansion of unordered comparisons and ordered ne. 634foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32], 635 [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in 636def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 637 (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>; 638 639foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64], 640 [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in 641def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 642 (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>; 643 644 645//===----------------------------------------------------------------------===// 646// Bitwise operations 647//===----------------------------------------------------------------------===// 648 649multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name, 650 bits<32> simdop> { 651 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 652 (outs), (ins), 653 [(set (vec_t V128:$dst), 654 (node (vec_t V128:$lhs), (vec_t V128:$rhs)) 655 )], 656 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, 657 simdop>; 658} 659 660multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> { 661 defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>; 662 defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>; 663 defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>; 664 defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>; 665} 666 667multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name, 668 bits<32> simdop> { 669 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 670 [(set (vec_t V128:$dst), 671 (vec_t (node (vec_t V128:$vec))) 672 )], 673 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>; 674} 675 676// Bitwise logic: v128.not 677foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in 678defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 77>; 679 680// Bitwise logic: v128.and / v128.or / v128.xor 681let isCommutable = 1 in { 682defm AND : SIMDBitwise<and, "and", 78>; 683defm OR : SIMDBitwise<or, "or", 80>; 684defm XOR : SIMDBitwise<xor, "xor", 81>; 685} // isCommutable = 1 686 687// Bitwise logic: v128.andnot 688def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>; 689defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>; 690 691// Bitwise select: v128.bitselect 692foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 693 defm BITSELECT_#vec_t : 694 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), 695 [(set (vec_t V128:$dst), 696 (vec_t (int_wasm_bitselect 697 (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c) 698 )) 699 )], 700 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>; 701 702// Bitselect is equivalent to (c & v1) | (~c & v2) 703foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in 704 def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)), 705 (and (vnot V128:$c), (vec_t V128:$v2)))), 706 (!cast<Instruction>("BITSELECT_"#vec_t) 707 V128:$v1, V128:$v2, V128:$c)>; 708 709// Also implement vselect in terms of bitselect 710foreach types = [[v16i8, v16i8], [v8i16, v8i16], [v4i32, v4i32], [v2i64, v2i64], 711 [v4f32, v4i32], [v2f64, v2i64]] in 712 def : Pat<(types[0] (vselect 713 (types[1] V128:$c), (types[0] V128:$v1), (types[0] V128:$v2) 714 )), 715 (!cast<Instruction>("BITSELECT_"#types[0]) 716 V128:$v1, V128:$v2, V128:$c 717 )>; 718 719// MVP select on v128 values 720foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 721defm SELECT_#vec_t : I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), 722 (outs), (ins), 723 [(set V128:$dst, 724 (select I32:$cond, 725 (vec_t V128:$lhs), (vec_t V128:$rhs) 726 ) 727 )], 728 "v128.select\t$dst, $lhs, $rhs, $cond", 729 "v128.select", 0x1b>; 730 731// ISD::SELECT requires its operand to conform to getBooleanContents, but 732// WebAssembly's select interprets any non-zero value as true, so we can fold 733// a setne with 0 into a select. 734def : Pat<(select 735 (i32 (setne I32:$cond, 0)), (vec_t V128:$lhs), (vec_t V128:$rhs) 736 ), 737 (!cast<Instruction>("SELECT_"#vec_t) 738 V128:$lhs, V128:$rhs, I32:$cond 739 )>; 740 741// And again, this time with seteq instead of setne and the arms reversed. 742def : Pat<(select 743 (i32 (seteq I32:$cond, 0)), (vec_t V128:$lhs), (vec_t V128:$rhs) 744 ), 745 (!cast<Instruction>("SELECT_"#vec_t) 746 V128:$rhs, V128:$lhs, I32:$cond 747 )>; 748} // foreach vec_t 749 750// Sign select 751multiclass SIMDSignSelect<ValueType vec_t, string vec, bits<32> simdop> { 752 defm SIGNSELECT_#vec_t : 753 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), 754 [(set (vec_t V128:$dst), 755 (vec_t (int_wasm_signselect 756 (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c) 757 )) 758 )], 759 vec#".signselect\t$dst, $v1, $v2, $c", vec#".signselect", simdop>; 760} 761 762defm : SIMDSignSelect<v16i8, "i8x16", 125>; 763defm : SIMDSignSelect<v8i16, "i16x8", 126>; 764defm : SIMDSignSelect<v4i32, "i32x4", 127>; 765defm : SIMDSignSelect<v2i64, "i64x2", 148>; 766 767//===----------------------------------------------------------------------===// 768// Integer unary arithmetic 769//===----------------------------------------------------------------------===// 770 771multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> { 772 defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>; 773 defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 774 defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 775 defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 776} 777 778multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name, 779 bits<32> simdop> { 780 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 781 [(set I32:$dst, (i32 (op (vec_t V128:$vec))))], 782 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>; 783} 784 785multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> { 786 defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>; 787 defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 32)>; 788 defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 64)>; 789 defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 96)>; 790} 791 792// Integer vector negation 793def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; 794 795// Integer absolute value: abs 796defm ABS : SIMDUnaryInt<abs, "abs", 96>; 797 798// Integer negation: neg 799defm NEG : SIMDUnaryInt<ivneg, "neg", 97>; 800 801// Any lane true: any_true 802defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>; 803 804// All lanes true: all_true 805defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>; 806 807// Population count: popcnt 808defm POPCNT : SIMDUnary<v16i8, "i8x16", int_wasm_popcnt, "popcnt", 124>; 809 810// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1 811// can be folded out 812foreach reduction = 813 [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in 814foreach ty = [v16i8, v8i16, v4i32, v2i64] in { 815def : Pat<(i32 (and 816 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 817 (i32 1) 818 )), 819 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 820def : Pat<(i32 (setne 821 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 822 (i32 0) 823 )), 824 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 825def : Pat<(i32 (seteq 826 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 827 (i32 1) 828 )), 829 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 830} 831 832multiclass SIMDBitmask<ValueType vec_t, string vec, bits<32> simdop> { 833 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 834 [(set I32:$dst, 835 (i32 (int_wasm_bitmask (vec_t V128:$vec))) 836 )], 837 vec#".bitmask\t$dst, $vec", vec#".bitmask", simdop>; 838} 839 840defm BITMASK : SIMDBitmask<v16i8, "i8x16", 100>; 841defm BITMASK : SIMDBitmask<v8i16, "i16x8", 132>; 842defm BITMASK : SIMDBitmask<v4i32, "i32x4", 164>; 843 844//===----------------------------------------------------------------------===// 845// Bit shifts 846//===----------------------------------------------------------------------===// 847 848multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, string name, 849 bits<32> simdop> { 850 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), 851 (outs), (ins), 852 [(set (vec_t V128:$dst), (node V128:$vec, I32:$x))], 853 vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>; 854} 855 856multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> { 857 defm "" : SIMDShift<v16i8, "i8x16", node, name, baseInst>; 858 defm "" : SIMDShift<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 859 defm "" : SIMDShift<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 860 defm "" : SIMDShift<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 861} 862 863// WebAssembly SIMD shifts are nonstandard in that the shift amount is 864// an i32 rather than a vector, so they need custom nodes. 865def wasm_shift_t : SDTypeProfile<1, 2, 866 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>] 867>; 868def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>; 869def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>; 870def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>; 871 872// Left shift by scalar: shl 873defm SHL : SIMDShiftInt<wasm_shl, "shl", 107>; 874 875// Right shift by scalar: shr_s / shr_u 876defm SHR_S : SIMDShiftInt<wasm_shr_s, "shr_s", 108>; 877defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>; 878 879//===----------------------------------------------------------------------===// 880// Integer binary arithmetic 881//===----------------------------------------------------------------------===// 882 883multiclass SIMDBinaryIntNoI8x16<SDNode node, string name, bits<32> baseInst> { 884 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 885 defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 886 defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 887} 888 889multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> { 890 defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>; 891 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>; 892} 893 894multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> { 895 defm "" : SIMDBinaryIntSmall<node, name, baseInst>; 896 defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>; 897} 898 899multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> { 900 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>; 901 defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>; 902} 903 904// Integer addition: add / add_saturate_s / add_saturate_u 905let isCommutable = 1 in { 906defm ADD : SIMDBinaryInt<add, "add", 110>; 907defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>; 908defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 112>; 909} // isCommutable = 1 910 911// Integer subtraction: sub / sub_saturate_s / sub_saturate_u 912defm SUB : SIMDBinaryInt<sub, "sub", 113>; 913defm SUB_SAT_S : 914 SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 114>; 915defm SUB_SAT_U : 916 SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 115>; 917 918// Integer multiplication: mul 919let isCommutable = 1 in 920defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>; 921 922// Integer min_s / min_u / max_s / max_u 923let isCommutable = 1 in { 924defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>; 925defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>; 926defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>; 927defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>; 928} // isCommutable = 1 929 930// Integer unsigned rounding average: avgr_u 931let isCommutable = 1 in { 932defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 123>; 933defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 155>; 934} 935 936def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), 937 (add node:$lhs, node:$rhs), 938 "return N->getFlags().hasNoUnsignedWrap();">; 939 940foreach nodes = [[v16i8, splat16], [v8i16, splat8]] in 941def : Pat<(wasm_shr_u 942 (add_nuw 943 (add_nuw (nodes[0] V128:$lhs), (nodes[0] V128:$rhs)), 944 (nodes[1] (i32 1)) 945 ), 946 (i32 1) 947 ), 948 (!cast<NI>("AVGR_U_"#nodes[0]) V128:$lhs, V128:$rhs)>; 949 950// Widening dot product: i32x4.dot_i16x8_s 951let isCommutable = 1 in 952defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 953 [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))], 954 "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s", 955 186>; 956 957// Extending multiplication: extmul_{low,high}_P, extmul_high 958multiclass SIMDExtBinary<ValueType vec_t, ValueType arg_t, string vec, 959 SDNode node, string name, bits<32> simdop> { 960 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 961 (outs), (ins), 962 [(set (vec_t V128:$dst), 963 (node (arg_t V128:$lhs), (arg_t V128:$rhs)) 964 )], 965 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, 966 simdop>; 967} 968 969defm EXTMUL_LOW_S : 970 SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_low_signed, 971 "extmul_low_i8x16_s", 154>; 972defm EXTMUL_HIGH_S : 973 SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_high_signed, 974 "extmul_high_i8x16_s", 157>; 975defm EXTMUL_LOW_U : 976 SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_low_unsigned, 977 "extmul_low_i8x16_u", 158>; 978defm EXTMUL_HIGH_U : 979 SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_high_unsigned, 980 "extmul_high_i8x16_u", 159>; 981 982defm EXTMUL_LOW_S : 983 SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_low_signed, 984 "extmul_low_i16x8_s", 187>; 985defm EXTMUL_HIGH_S : 986 SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_high_signed, 987 "extmul_high_i16x8_s", 189>; 988defm EXTMUL_LOW_U : 989 SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_low_unsigned, 990 "extmul_low_i16x8_u", 190>; 991defm EXTMUL_HIGH_U : 992 SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_high_unsigned, 993 "extmul_high_i16x8_u", 191>; 994 995defm EXTMUL_LOW_S : 996 SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_low_signed, 997 "extmul_low_i32x4_s", 210>; 998defm EXTMUL_HIGH_S : 999 SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_high_signed, 1000 "extmul_high_i32x4_s", 211>; 1001defm EXTMUL_LOW_U : 1002 SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_low_unsigned, 1003 "extmul_low_i32x4_u", 214>; 1004defm EXTMUL_HIGH_U : 1005 SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_high_unsigned, 1006 "extmul_high_i32x4_u", 215>; 1007 1008//===----------------------------------------------------------------------===// 1009// Floating-point unary arithmetic 1010//===----------------------------------------------------------------------===// 1011 1012multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> { 1013 defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>; 1014 defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 12)>; 1015} 1016 1017// Absolute value: abs 1018defm ABS : SIMDUnaryFP<fabs, "abs", 224>; 1019 1020// Negation: neg 1021defm NEG : SIMDUnaryFP<fneg, "neg", 225>; 1022 1023// Square root: sqrt 1024defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>; 1025 1026// Rounding: ceil, floor, trunc, nearest 1027defm CEIL : SIMDUnary<v4f32, "f32x4", int_wasm_ceil, "ceil", 216>; 1028defm FLOOR : SIMDUnary<v4f32, "f32x4", int_wasm_floor, "floor", 217>; 1029defm TRUNC: SIMDUnary<v4f32, "f32x4", int_wasm_trunc, "trunc", 218>; 1030defm NEAREST: SIMDUnary<v4f32, "f32x4", int_wasm_nearest, "nearest", 219>; 1031defm CEIL : SIMDUnary<v2f64, "f64x2", int_wasm_ceil, "ceil", 220>; 1032defm FLOOR : SIMDUnary<v2f64, "f64x2", int_wasm_floor, "floor", 221>; 1033defm TRUNC: SIMDUnary<v2f64, "f64x2", int_wasm_trunc, "trunc", 222>; 1034defm NEAREST: SIMDUnary<v2f64, "f64x2", int_wasm_nearest, "nearest", 223>; 1035 1036//===----------------------------------------------------------------------===// 1037// Floating-point binary arithmetic 1038//===----------------------------------------------------------------------===// 1039 1040multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> { 1041 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>; 1042 defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 12)>; 1043} 1044 1045// Addition: add 1046let isCommutable = 1 in 1047defm ADD : SIMDBinaryFP<fadd, "add", 228>; 1048 1049// Subtraction: sub 1050defm SUB : SIMDBinaryFP<fsub, "sub", 229>; 1051 1052// Multiplication: mul 1053let isCommutable = 1 in 1054defm MUL : SIMDBinaryFP<fmul, "mul", 230>; 1055 1056// Division: div 1057defm DIV : SIMDBinaryFP<fdiv, "div", 231>; 1058 1059// NaN-propagating minimum: min 1060defm MIN : SIMDBinaryFP<fminimum, "min", 232>; 1061 1062// NaN-propagating maximum: max 1063defm MAX : SIMDBinaryFP<fmaximum, "max", 233>; 1064 1065// Pseudo-minimum: pmin 1066defm PMIN : SIMDBinaryFP<int_wasm_pmin, "pmin", 234>; 1067 1068// Pseudo-maximum: pmax 1069defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>; 1070 1071//===----------------------------------------------------------------------===// 1072// Conversions 1073//===----------------------------------------------------------------------===// 1074 1075multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op, 1076 string name, bits<32> simdop> { 1077 defm op#_#vec_t#_#arg_t : 1078 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 1079 [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))], 1080 name#"\t$dst, $vec", name, simdop>; 1081} 1082 1083// Floating point to integer with saturation: trunc_sat 1084defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 248>; 1085defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 249>; 1086 1087// Integer to floating point: convert 1088defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 250>; 1089defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 251>; 1090 1091// Lower llvm.wasm.trunc.saturate.* to saturating instructions 1092def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))), 1093 (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>; 1094def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))), 1095 (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>; 1096 1097// Widening operations 1098def widen_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1099def widen_low_s : SDNode<"WebAssemblyISD::WIDEN_LOW_S", widen_t>; 1100def widen_high_s : SDNode<"WebAssemblyISD::WIDEN_HIGH_S", widen_t>; 1101def widen_low_u : SDNode<"WebAssemblyISD::WIDEN_LOW_U", widen_t>; 1102def widen_high_u : SDNode<"WebAssemblyISD::WIDEN_HIGH_U", widen_t>; 1103 1104multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg, 1105 bits<32> baseInst> { 1106 defm "" : SIMDConvert<vec_t, arg_t, widen_low_s, 1107 vec#".widen_low_"#arg#"_s", baseInst>; 1108 defm "" : SIMDConvert<vec_t, arg_t, widen_high_s, 1109 vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>; 1110 defm "" : SIMDConvert<vec_t, arg_t, widen_low_u, 1111 vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>; 1112 defm "" : SIMDConvert<vec_t, arg_t, widen_high_u, 1113 vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>; 1114} 1115 1116defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 135>; 1117defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 167>; 1118 1119// Narrowing operations 1120multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg, 1121 bits<32> baseInst> { 1122 defm NARROW_S_#vec_t : 1123 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1124 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed 1125 (arg_t V128:$low), (arg_t V128:$high))))], 1126 vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s", 1127 baseInst>; 1128 defm NARROW_U_#vec_t : 1129 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1130 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned 1131 (arg_t V128:$low), (arg_t V128:$high))))], 1132 vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u", 1133 !add(baseInst, 1)>; 1134} 1135 1136defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 101>; 1137defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 133>; 1138 1139// Use narrowing operations for truncating stores. Since the narrowing 1140// operations are saturating instead of truncating, we need to mask 1141// the stored values first. 1142// TODO: Use consts instead of splats 1143def store_v8i8_trunc_v8i16 : 1144 OutPatFrag<(ops node:$val), 1145 (EXTRACT_LANE_v2i64 1146 (NARROW_U_v16i8 1147 (AND_v4i32 (SPLAT_v4i32 (CONST_I32 0x00ff00ff)), node:$val), 1148 node:$val // Unused input 1149 ), 1150 0 1151 )>; 1152 1153def store_v4i16_trunc_v4i32 : 1154 OutPatFrag<(ops node:$val), 1155 (EXTRACT_LANE_v2i64 1156 (NARROW_U_v8i16 1157 (AND_v4i32 (SPLAT_v4i32 (CONST_I32 0x0000ffff)), node:$val), 1158 node:$val // Unused input 1159 ), 1160 0 1161 )>; 1162 1163// Store patterns adapted from WebAssemblyInstrMemory.td 1164multiclass NarrowingStorePatNoOffset<ValueType ty, PatFrag node, 1165 OutPatFrag out> { 1166 def : Pat<(node ty:$val, I32:$addr), 1167 (STORE_I64_A32 0, 0, I32:$addr, (i64 (out ty:$val)))>, 1168 Requires<[HasAddr32]>; 1169 def : Pat<(node ty:$val, I64:$addr), 1170 (STORE_I64_A64 0, 0, I64:$addr, (i64 (out ty:$val)))>, 1171 Requires<[HasAddr64]>; 1172} 1173 1174defm : NarrowingStorePatNoOffset<v8i16, truncstorevi8, store_v8i8_trunc_v8i16>; 1175defm : NarrowingStorePatNoOffset<v4i32, truncstorevi16, 1176 store_v4i16_trunc_v4i32>; 1177 1178multiclass NarrowingStorePatImmOff<ValueType ty, PatFrag kind, 1179 PatFrag operand, OutPatFrag out> { 1180 def : Pat<(kind ty:$val, (operand I32:$addr, imm:$off)), 1181 (STORE_I64_A32 0, imm:$off, I32:$addr, (i64 (out ty:$val)))>, 1182 Requires<[HasAddr32]>; 1183 def : Pat<(kind ty:$val, (operand I64:$addr, imm:$off)), 1184 (STORE_I64_A64 0, imm:$off, I64:$addr, (i64 (out ty:$val)))>, 1185 Requires<[HasAddr64]>; 1186} 1187 1188defm : NarrowingStorePatImmOff<v8i16, truncstorevi8, regPlusImm, 1189 store_v8i8_trunc_v8i16>; 1190defm : NarrowingStorePatImmOff<v4i32, truncstorevi16, regPlusImm, 1191 store_v4i16_trunc_v4i32>; 1192defm : NarrowingStorePatImmOff<v8i16, truncstorevi8, or_is_add, 1193 store_v8i8_trunc_v8i16>; 1194defm : NarrowingStorePatImmOff<v4i32, truncstorevi16, or_is_add, 1195 store_v4i16_trunc_v4i32>; 1196 1197multiclass NarrowingStorePatOffsetOnly<ValueType ty, PatFrag kind, 1198 OutPatFrag out> { 1199 def : Pat<(kind ty:$val, imm:$off), 1200 (STORE_I64_A32 0, imm:$off, (CONST_I32 0), (i64 (out ty:$val)))>, 1201 Requires<[HasAddr32]>; 1202 def : Pat<(kind ty:$val, imm:$off), 1203 (STORE_I64_A64 0, imm:$off, (CONST_I64 0), (i64 (out ty:$val)))>, 1204 Requires<[HasAddr64]>; 1205} 1206 1207defm : NarrowingStorePatOffsetOnly<v8i16, truncstorevi8, 1208 store_v8i8_trunc_v8i16>; 1209defm : NarrowingStorePatOffsetOnly<v4i32, truncstorevi16, 1210 store_v4i16_trunc_v4i32>; 1211 1212multiclass NarrowingStorePatGlobalAddrOffOnly<ValueType ty, PatFrag kind, 1213 OutPatFrag out> { 1214 def : Pat<(kind ty:$val, (WebAssemblywrapper tglobaladdr:$off)), 1215 (STORE_I64_A32 1216 0, tglobaladdr:$off, (CONST_I32 0), (i64 (out ty:$val)))>, 1217 Requires<[IsNotPIC, HasAddr32]>; 1218 def : Pat<(kind ty:$val, (WebAssemblywrapper tglobaladdr:$off)), 1219 (STORE_I64_A64 1220 0, tglobaladdr:$off, (CONST_I64 0), (i64 (out ty:$val)))>, 1221 Requires<[IsNotPIC, HasAddr64]>; 1222} 1223 1224defm : NarrowingStorePatGlobalAddrOffOnly<v8i16, truncstorevi8, 1225 store_v8i8_trunc_v8i16>; 1226defm : NarrowingStorePatGlobalAddrOffOnly<v4i32, truncstorevi16, 1227 store_v4i16_trunc_v4i32>; 1228 1229// Bitcasts are nops 1230// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types 1231foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 1232foreach t2 = !foldl( 1233 []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 1234 acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)), 1235 acc, !listconcat(acc, [cur]) 1236 ) 1237) in 1238def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>; 1239 1240//===----------------------------------------------------------------------===// 1241// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS) 1242//===----------------------------------------------------------------------===// 1243 1244multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> simdopA, 1245 bits<32> simdopS> { 1246 defm QFMA_#vec_t : 1247 SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), 1248 (outs), (ins), 1249 [(set (vec_t V128:$dst), 1250 (int_wasm_qfma (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))], 1251 vec#".qfma\t$dst, $a, $b, $c", vec#".qfma", simdopA>; 1252 defm QFMS_#vec_t : 1253 SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), 1254 (outs), (ins), 1255 [(set (vec_t V128:$dst), 1256 (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))], 1257 vec#".qfms\t$dst, $a, $b, $c", vec#".qfms", simdopS>; 1258} 1259 1260defm "" : SIMDQFM<v4f32, "f32x4", 180, 212>; 1261defm "" : SIMDQFM<v2f64, "f64x2", 254, 255>; 1262 1263//===----------------------------------------------------------------------===// 1264// Saturating Rounding Q-Format Multiplication 1265//===----------------------------------------------------------------------===// 1266 1267defm Q15MULR_SAT_S : 1268 SIMDBinary<v8i16, "i16x8", int_wasm_q15mulr_saturate_signed, "q15mulr_sat_s", 1269 156>; 1270