1// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief WebAssembly Memory operand code-gen constructs.
12///
13//===----------------------------------------------------------------------===//
14
15// TODO:
16//  - HasAddr64
17//  - WebAssemblyTargetLowering::isLegalAddressingMode
18//  - WebAssemblyTargetLowering having to do with atomics
19//  - Each has optional alignment and immediate byte offset.
20
21// WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
22// local types. These memory-only types instead zero- or sign-extend into local
23// types when loading, and truncate when storing.
24
25let Defs = [ARGUMENTS] in {
26
27// Basic load.
28def LOAD_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
29                 "i32.load\t$dst, $off($addr)">;
30def LOAD_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
31                 "i64.load\t$dst, $off($addr)">;
32def LOAD_F32 : I<(outs F32:$dst), (ins I32:$off, I32:$addr), [],
33                 "f32.load\t$dst, $off($addr)">;
34def LOAD_F64 : I<(outs F64:$dst), (ins I32:$off, I32:$addr), [],
35                 "f64.load\t$dst, $off($addr)">;
36
37// Extending load.
38def LOAD8_S_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
39                     "i32.load8_s\t$dst, $off($addr)">;
40def LOAD8_U_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
41                     "i32.load8_u\t$dst, $off($addr)">;
42def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
43                     "i32.load16_s\t$dst, $off($addr)">;
44def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
45                     "i32.load16_u\t$dst, $off($addr)">;
46def LOAD8_S_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
47                     "i64.load8_s\t$dst, $off($addr)">;
48def LOAD8_U_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
49                     "i64.load8_u\t$dst, $off($addr)">;
50def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
51                     "i64.load16_s\t$dst, $off($addr)">;
52def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
53                     "i64.load16_u\t$dst, $off($addr)">;
54def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
55                     "i64.load32_s\t$dst, $off($addr)">;
56def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
57                     "i64.load32_u\t$dst, $off($addr)">;
58
59} // Defs = [ARGUMENTS]
60
61// Select loads with no constant offset.
62def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr)>;
63def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr)>;
64def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr)>;
65def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr)>;
66
67// Select extending loads with no constant offset.
68def : Pat<(i32 (sextloadi8 I32:$addr)), (LOAD8_S_I32 0, $addr)>;
69def : Pat<(i32 (zextloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr)>;
70def : Pat<(i32 (sextloadi16 I32:$addr)), (LOAD16_S_I32 0, $addr)>;
71def : Pat<(i32 (zextloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>;
72def : Pat<(i64 (sextloadi8 I32:$addr)), (LOAD8_S_I64 0, $addr)>;
73def : Pat<(i64 (zextloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr)>;
74def : Pat<(i64 (sextloadi16 I32:$addr)), (LOAD16_S_I64 0, $addr)>;
75def : Pat<(i64 (zextloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>;
76def : Pat<(i64 (sextloadi32 I32:$addr)), (LOAD32_S_I64 0, $addr)>;
77def : Pat<(i64 (zextloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>;
78
79// "Don't care" extending load become zero-extending load.
80def : Pat<(i32 (extloadi8 I32:$addr)),  (LOAD8_U_I32 0, $addr)>;
81def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>;
82def : Pat<(i64 (extloadi8 I32:$addr)),  (LOAD8_U_I64 0, $addr)>;
83def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>;
84def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>;
85
86let Defs = [ARGUMENTS] in {
87
88// Basic store.
89// Note that we split the patterns out of the instruction definitions because
90// WebAssembly's stores return their operand value, and tablegen doesn't like
91// instruction definition patterns that don't reference all of the output
92// operands.
93// Note: WebAssembly inverts SelectionDAG's usual operand order.
94def STORE_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
95                   "i32.store\t$dst, $off($addr), $val">;
96def STORE_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
97                   "i64.store\t$dst, $off($addr), $val">;
98def STORE_F32  : I<(outs F32:$dst), (ins I32:$off, I32:$addr, F32:$val), [],
99                   "f32.store\t$dst, $off($addr), $val">;
100def STORE_F64  : I<(outs F64:$dst), (ins I32:$off, I32:$addr, F64:$val), [],
101                   "f64.store\t$dst, $off($addr), $val">;
102
103} // Defs = [ARGUMENTS]
104
105def : Pat<(store I32:$val, I32:$addr), (STORE_I32 0, I32:$addr, I32:$val)>;
106def : Pat<(store I64:$val, I32:$addr), (STORE_I64 0, I32:$addr, I64:$val)>;
107def : Pat<(store F32:$val, I32:$addr), (STORE_F32 0, I32:$addr, F32:$val)>;
108def : Pat<(store F64:$val, I32:$addr), (STORE_F64 0, I32:$addr, F64:$val)>;
109
110// FIXME: This pattern matches an immediate to actually use the offset field
111// in the store instruction; however only unsigned offsets are supported in
112// wasm, so we need to constrain the immediate we match. This may require
113// custom code rather than a simple pattern.
114// def : Pat<(store I32:$val, (add I32:$addr, (i32 imm:$off))),
115//           (STORE_I32 imm:$off, I32:$addr, I32:$val)>;
116
117let Defs = [ARGUMENTS] in {
118
119// Truncating store.
120def STORE8_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
121                    "i32.store8\t$dst, $off($addr), $val">;
122def STORE16_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
123                    "i32.store16\t$dst, $off($addr), $val">;
124def STORE8_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
125                    "i64.store8\t$dst, $off($addr), $val">;
126def STORE16_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
127                    "i64.store16\t$dst, $off($addr), $val">;
128def STORE32_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
129                    "i64.store32\t$dst, $off($addr), $val">;
130
131} // Defs = [ARGUMENTS]
132
133def : Pat<(truncstorei8 I32:$val, I32:$addr),
134          (STORE8_I32 0, I32:$addr, I32:$val)>;
135def : Pat<(truncstorei16 I32:$val, I32:$addr),
136          (STORE16_I32 0, I32:$addr, I32:$val)>;
137def : Pat<(truncstorei8 I64:$val, I32:$addr),
138          (STORE8_I64 0, I32:$addr, I64:$val)>;
139def : Pat<(truncstorei16 I64:$val, I32:$addr),
140          (STORE16_I64 0, I32:$addr, I64:$val)>;
141def : Pat<(truncstorei32 I64:$val, I32:$addr),
142          (STORE32_I64 0, I32:$addr, I64:$val)>;
143
144let Defs = [ARGUMENTS] in {
145
146// Memory size.
147def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
148                        [(set I32:$dst, (int_wasm_memory_size))],
149                        "memory_size\t$dst">,
150                      Requires<[HasAddr32]>;
151def MEMORY_SIZE_I64 : I<(outs I64:$dst), (ins),
152                        [(set I64:$dst, (int_wasm_memory_size))],
153                        "memory_size\t$dst">,
154                      Requires<[HasAddr64]>;
155
156// Grow memory.
157def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
158                        [(int_wasm_grow_memory I32:$delta)],
159                        "grow_memory\t$delta">,
160                      Requires<[HasAddr32]>;
161def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
162                        [(int_wasm_grow_memory I64:$delta)],
163                        "grow_memory\t$delta">,
164                      Requires<[HasAddr64]>;
165
166} // Defs = [ARGUMENTS]
167