1 //- WebAssemblyISelDAGToDAG.cpp - A dag to dag inst selector for WebAssembly -// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file defines an instruction selector for the WebAssembly target. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 15 #include "WebAssembly.h" 16 #include "WebAssemblyTargetMachine.h" 17 #include "llvm/CodeGen/SelectionDAGISel.h" 18 #include "llvm/IR/Function.h" // To access function attributes. 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/KnownBits.h" 21 #include "llvm/Support/MathExtras.h" 22 #include "llvm/Support/raw_ostream.h" 23 using namespace llvm; 24 25 #define DEBUG_TYPE "wasm-isel" 26 27 //===--------------------------------------------------------------------===// 28 /// WebAssembly-specific code to select WebAssembly machine instructions for 29 /// SelectionDAG operations. 30 /// 31 namespace { 32 class WebAssemblyDAGToDAGISel final : public SelectionDAGISel { 33 /// Keep a pointer to the WebAssemblySubtarget around so that we can make the 34 /// right decision when generating code for different targets. 35 const WebAssemblySubtarget *Subtarget; 36 37 bool ForCodeSize; 38 39 public: 40 WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM, 41 CodeGenOpt::Level OptLevel) 42 : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr), ForCodeSize(false) { 43 } 44 45 StringRef getPassName() const override { 46 return "WebAssembly Instruction Selection"; 47 } 48 49 bool runOnMachineFunction(MachineFunction &MF) override { 50 LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n" 51 "********** Function: " 52 << MF.getName() << '\n'); 53 54 ForCodeSize = MF.getFunction().hasOptSize(); 55 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>(); 56 return SelectionDAGISel::runOnMachineFunction(MF); 57 } 58 59 void Select(SDNode *Node) override; 60 61 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 62 std::vector<SDValue> &OutOps) override; 63 64 // Include the pieces autogenerated from the target description. 65 #include "WebAssemblyGenDAGISel.inc" 66 67 private: 68 // add select functions here... 69 }; 70 } // end anonymous namespace 71 72 void WebAssemblyDAGToDAGISel::Select(SDNode *Node) { 73 // If we have a custom node, we already have selected! 74 if (Node->isMachineOpcode()) { 75 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 76 Node->setNodeId(-1); 77 return; 78 } 79 80 // Few custom selection stuff. 81 SDLoc DL(Node); 82 MachineFunction &MF = CurDAG->getMachineFunction(); 83 switch (Node->getOpcode()) { 84 case ISD::ATOMIC_FENCE: { 85 if (!MF.getSubtarget<WebAssemblySubtarget>().hasAtomics()) 86 break; 87 88 uint64_t SyncScopeID = 89 cast<ConstantSDNode>(Node->getOperand(2).getNode())->getZExtValue(); 90 switch (SyncScopeID) { 91 case SyncScope::SingleThread: { 92 // We lower a single-thread fence to a pseudo compiler barrier instruction 93 // preventing instruction reordering. This will not be emitted in final 94 // binary. 95 MachineSDNode *Fence = 96 CurDAG->getMachineNode(WebAssembly::COMPILER_FENCE, 97 DL, // debug loc 98 MVT::Other, // outchain type 99 Node->getOperand(0) // inchain 100 ); 101 ReplaceNode(Node, Fence); 102 CurDAG->RemoveDeadNode(Node); 103 return; 104 } 105 106 case SyncScope::System: { 107 // For non-emscripten systems, we have not decided on what we should 108 // traslate fences to yet. 109 if (!Subtarget->getTargetTriple().isOSEmscripten()) 110 report_fatal_error( 111 "ATOMIC_FENCE is not yet supported in non-emscripten OSes"); 112 113 // Wasm does not have a fence instruction, but because all atomic 114 // instructions in wasm are sequentially consistent, we translate a 115 // fence to an idempotent atomic RMW instruction to a linear memory 116 // address. All atomic instructions in wasm are sequentially consistent, 117 // but this is to ensure a fence also prevents reordering of non-atomic 118 // instructions in the VM. Even though LLVM IR's fence instruction does 119 // not say anything about its relationship with non-atomic instructions, 120 // we think this is more user-friendly. 121 // 122 // While any address can work, here we use a value stored in 123 // __stack_pointer wasm global because there's high chance that area is 124 // in cache. 125 // 126 // So the selected instructions will be in the form of: 127 // %addr = get_global $__stack_pointer 128 // %0 = i32.const 0 129 // i32.atomic.rmw.or %addr, %0 130 SDValue StackPtrSym = CurDAG->getTargetExternalSymbol( 131 "__stack_pointer", TLI->getPointerTy(CurDAG->getDataLayout())); 132 MachineSDNode *GetGlobal = 133 CurDAG->getMachineNode(WebAssembly::GLOBAL_GET_I32, // opcode 134 DL, // debug loc 135 MVT::i32, // result type 136 StackPtrSym // __stack_pointer symbol 137 ); 138 139 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); 140 auto *MMO = MF.getMachineMemOperand( 141 MachinePointerInfo::getUnknownStack(MF), 142 // FIXME Volatile isn't really correct, but currently all LLVM 143 // atomic instructions are treated as volatiles in the backend, so 144 // we should be consistent. 145 MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad | 146 MachineMemOperand::MOStore, 147 4, 4, AAMDNodes(), nullptr, SyncScope::System, 148 AtomicOrdering::SequentiallyConsistent); 149 MachineSDNode *Const0 = 150 CurDAG->getMachineNode(WebAssembly::CONST_I32, DL, MVT::i32, Zero); 151 MachineSDNode *AtomicRMW = CurDAG->getMachineNode( 152 WebAssembly::ATOMIC_RMW_OR_I32, // opcode 153 DL, // debug loc 154 MVT::i32, // result type 155 MVT::Other, // outchain type 156 { 157 Zero, // alignment 158 Zero, // offset 159 SDValue(GetGlobal, 0), // __stack_pointer 160 SDValue(Const0, 0), // OR with 0 to make it idempotent 161 Node->getOperand(0) // inchain 162 }); 163 164 CurDAG->setNodeMemRefs(AtomicRMW, {MMO}); 165 ReplaceUses(SDValue(Node, 0), SDValue(AtomicRMW, 1)); 166 CurDAG->RemoveDeadNode(Node); 167 return; 168 } 169 default: 170 llvm_unreachable("Unknown scope!"); 171 } 172 } 173 174 default: 175 break; 176 } 177 178 // Select the default instruction. 179 SelectCode(Node); 180 } 181 182 bool WebAssemblyDAGToDAGISel::SelectInlineAsmMemoryOperand( 183 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) { 184 switch (ConstraintID) { 185 case InlineAsm::Constraint_i: 186 case InlineAsm::Constraint_m: 187 // We just support simple memory operands that just have a single address 188 // operand and need no special handling. 189 OutOps.push_back(Op); 190 return false; 191 default: 192 break; 193 } 194 195 return true; 196 } 197 198 /// This pass converts a legalized DAG into a WebAssembly-specific DAG, ready 199 /// for instruction scheduling. 200 FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, 201 CodeGenOpt::Level OptLevel) { 202 return new WebAssemblyDAGToDAGISel(TM, OptLevel); 203 } 204