1 //===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific support for the FastISel
11 /// class. Some of the target-specific code is generated by tablegen in the file
12 /// WebAssemblyGenFastISel.inc, which is #included here.
13 ///
14 /// TODO: kill flags
15 ///
16 //===----------------------------------------------------------------------===//
17 
18 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
19 #include "WebAssembly.h"
20 #include "WebAssemblyMachineFunctionInfo.h"
21 #include "WebAssemblySubtarget.h"
22 #include "WebAssemblyTargetMachine.h"
23 #include "llvm/Analysis/BranchProbabilityInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GetElementPtrTypeIterator.h"
34 #include "llvm/IR/GlobalAlias.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/IntrinsicInst.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/IR/PatternMatch.h"
40 
41 using namespace llvm;
42 using namespace PatternMatch;
43 
44 #define DEBUG_TYPE "wasm-fastisel"
45 
46 namespace {
47 
48 class WebAssemblyFastISel final : public FastISel {
49   // All possible address modes.
50   class Address {
51   public:
52     using BaseKind = enum { RegBase, FrameIndexBase };
53 
54   private:
55     BaseKind Kind = RegBase;
56     union {
57       unsigned Reg;
58       int FI;
59     } Base;
60 
61     int64_t Offset = 0;
62 
63     const GlobalValue *GV = nullptr;
64 
65   public:
66     // Innocuous defaults for our address.
67     Address() { Base.Reg = 0; }
68     void setKind(BaseKind K) {
69       assert(!isSet() && "Can't change kind with non-zero base");
70       Kind = K;
71     }
72     BaseKind getKind() const { return Kind; }
73     bool isRegBase() const { return Kind == RegBase; }
74     bool isFIBase() const { return Kind == FrameIndexBase; }
75     void setReg(unsigned Reg) {
76       assert(isRegBase() && "Invalid base register access!");
77       assert(Base.Reg == 0 && "Overwriting non-zero register");
78       Base.Reg = Reg;
79     }
80     unsigned getReg() const {
81       assert(isRegBase() && "Invalid base register access!");
82       return Base.Reg;
83     }
84     void setFI(unsigned FI) {
85       assert(isFIBase() && "Invalid base frame index access!");
86       assert(Base.FI == 0 && "Overwriting non-zero frame index");
87       Base.FI = FI;
88     }
89     unsigned getFI() const {
90       assert(isFIBase() && "Invalid base frame index access!");
91       return Base.FI;
92     }
93 
94     void setOffset(int64_t NewOffset) {
95       assert(NewOffset >= 0 && "Offsets must be non-negative");
96       Offset = NewOffset;
97     }
98     int64_t getOffset() const { return Offset; }
99     void setGlobalValue(const GlobalValue *G) { GV = G; }
100     const GlobalValue *getGlobalValue() const { return GV; }
101     bool isSet() const {
102       if (isRegBase()) {
103         return Base.Reg != 0;
104       } else {
105         return Base.FI != 0;
106       }
107     }
108   };
109 
110   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
111   /// right decision when generating code for different targets.
112   const WebAssemblySubtarget *Subtarget;
113   LLVMContext *Context;
114 
115 private:
116   // Utility helper routines
117   MVT::SimpleValueType getSimpleType(Type *Ty) {
118     EVT VT = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true);
119     return VT.isSimple() ? VT.getSimpleVT().SimpleTy
120                          : MVT::INVALID_SIMPLE_VALUE_TYPE;
121   }
122   MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
123     switch (VT) {
124     case MVT::i1:
125     case MVT::i8:
126     case MVT::i16:
127       return MVT::i32;
128     case MVT::i32:
129     case MVT::i64:
130     case MVT::f32:
131     case MVT::f64:
132     case MVT::exnref:
133       return VT;
134     case MVT::f16:
135       return MVT::f32;
136     case MVT::v16i8:
137     case MVT::v8i16:
138     case MVT::v4i32:
139     case MVT::v4f32:
140       if (Subtarget->hasSIMD128())
141         return VT;
142       break;
143     case MVT::v2i64:
144     case MVT::v2f64:
145       if (Subtarget->hasUnimplementedSIMD128())
146         return VT;
147       break;
148     default:
149       break;
150     }
151     return MVT::INVALID_SIMPLE_VALUE_TYPE;
152   }
153   bool computeAddress(const Value *Obj, Address &Addr);
154   void materializeLoadStoreOperands(Address &Addr);
155   void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
156                             MachineMemOperand *MMO);
157   unsigned maskI1Value(unsigned Reg, const Value *V);
158   unsigned getRegForI1Value(const Value *V, bool &Not);
159   unsigned zeroExtendToI32(unsigned Reg, const Value *V,
160                            MVT::SimpleValueType From);
161   unsigned signExtendToI32(unsigned Reg, const Value *V,
162                            MVT::SimpleValueType From);
163   unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
164                       MVT::SimpleValueType To);
165   unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
166                       MVT::SimpleValueType To);
167   unsigned getRegForUnsignedValue(const Value *V);
168   unsigned getRegForSignedValue(const Value *V);
169   unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
170   unsigned notValue(unsigned Reg);
171   unsigned copyValue(unsigned Reg);
172 
173   // Backend specific FastISel code.
174   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
175   unsigned fastMaterializeConstant(const Constant *C) override;
176   bool fastLowerArguments() override;
177 
178   // Selection routines.
179   bool selectCall(const Instruction *I);
180   bool selectSelect(const Instruction *I);
181   bool selectTrunc(const Instruction *I);
182   bool selectZExt(const Instruction *I);
183   bool selectSExt(const Instruction *I);
184   bool selectICmp(const Instruction *I);
185   bool selectFCmp(const Instruction *I);
186   bool selectBitCast(const Instruction *I);
187   bool selectLoad(const Instruction *I);
188   bool selectStore(const Instruction *I);
189   bool selectBr(const Instruction *I);
190   bool selectRet(const Instruction *I);
191   bool selectUnreachable(const Instruction *I);
192 
193 public:
194   // Backend specific FastISel code.
195   WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
196                       const TargetLibraryInfo *LibInfo)
197       : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
198     Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
199     Context = &FuncInfo.Fn->getContext();
200   }
201 
202   bool fastSelectInstruction(const Instruction *I) override;
203 
204 #include "WebAssemblyGenFastISel.inc"
205 };
206 
207 } // end anonymous namespace
208 
209 bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
210   const User *U = nullptr;
211   unsigned Opcode = Instruction::UserOp1;
212   if (const auto *I = dyn_cast<Instruction>(Obj)) {
213     // Don't walk into other basic blocks unless the object is an alloca from
214     // another block, otherwise it may not have a virtual register assigned.
215     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
216         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
217       Opcode = I->getOpcode();
218       U = I;
219     }
220   } else if (const auto *C = dyn_cast<ConstantExpr>(Obj)) {
221     Opcode = C->getOpcode();
222     U = C;
223   }
224 
225   if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
226     if (Ty->getAddressSpace() > 255)
227       // Fast instruction selection doesn't support the special
228       // address spaces.
229       return false;
230 
231   if (const auto *GV = dyn_cast<GlobalValue>(Obj)) {
232     if (TLI.isPositionIndependent())
233       return false;
234     if (Addr.getGlobalValue())
235       return false;
236     if (GV->isThreadLocal())
237       return false;
238     Addr.setGlobalValue(GV);
239     return true;
240   }
241 
242   switch (Opcode) {
243   default:
244     break;
245   case Instruction::BitCast: {
246     // Look through bitcasts.
247     return computeAddress(U->getOperand(0), Addr);
248   }
249   case Instruction::IntToPtr: {
250     // Look past no-op inttoptrs.
251     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
252         TLI.getPointerTy(DL))
253       return computeAddress(U->getOperand(0), Addr);
254     break;
255   }
256   case Instruction::PtrToInt: {
257     // Look past no-op ptrtoints.
258     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
259       return computeAddress(U->getOperand(0), Addr);
260     break;
261   }
262   case Instruction::GetElementPtr: {
263     Address SavedAddr = Addr;
264     uint64_t TmpOffset = Addr.getOffset();
265     // Non-inbounds geps can wrap; wasm's offsets can't.
266     if (!cast<GEPOperator>(U)->isInBounds())
267       goto unsupported_gep;
268     // Iterate through the GEP folding the constants into offsets where
269     // we can.
270     for (gep_type_iterator GTI = gep_type_begin(U), E = gep_type_end(U);
271          GTI != E; ++GTI) {
272       const Value *Op = GTI.getOperand();
273       if (StructType *STy = GTI.getStructTypeOrNull()) {
274         const StructLayout *SL = DL.getStructLayout(STy);
275         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
276         TmpOffset += SL->getElementOffset(Idx);
277       } else {
278         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
279         for (;;) {
280           if (const auto *CI = dyn_cast<ConstantInt>(Op)) {
281             // Constant-offset addressing.
282             TmpOffset += CI->getSExtValue() * S;
283             break;
284           }
285           if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
286             // An unscaled add of a register. Set it as the new base.
287             unsigned Reg = getRegForValue(Op);
288             if (Reg == 0)
289               return false;
290             Addr.setReg(Reg);
291             break;
292           }
293           if (canFoldAddIntoGEP(U, Op)) {
294             // A compatible add with a constant operand. Fold the constant.
295             auto *CI = cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
296             TmpOffset += CI->getSExtValue() * S;
297             // Iterate on the other operand.
298             Op = cast<AddOperator>(Op)->getOperand(0);
299             continue;
300           }
301           // Unsupported
302           goto unsupported_gep;
303         }
304       }
305     }
306     // Don't fold in negative offsets.
307     if (int64_t(TmpOffset) >= 0) {
308       // Try to grab the base operand now.
309       Addr.setOffset(TmpOffset);
310       if (computeAddress(U->getOperand(0), Addr))
311         return true;
312     }
313     // We failed, restore everything and try the other options.
314     Addr = SavedAddr;
315   unsupported_gep:
316     break;
317   }
318   case Instruction::Alloca: {
319     const auto *AI = cast<AllocaInst>(Obj);
320     DenseMap<const AllocaInst *, int>::iterator SI =
321         FuncInfo.StaticAllocaMap.find(AI);
322     if (SI != FuncInfo.StaticAllocaMap.end()) {
323       if (Addr.isSet()) {
324         return false;
325       }
326       Addr.setKind(Address::FrameIndexBase);
327       Addr.setFI(SI->second);
328       return true;
329     }
330     break;
331   }
332   case Instruction::Add: {
333     // Adds of constants are common and easy enough.
334     const Value *LHS = U->getOperand(0);
335     const Value *RHS = U->getOperand(1);
336 
337     if (isa<ConstantInt>(LHS))
338       std::swap(LHS, RHS);
339 
340     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
341       uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
342       if (int64_t(TmpOffset) >= 0) {
343         Addr.setOffset(TmpOffset);
344         return computeAddress(LHS, Addr);
345       }
346     }
347 
348     Address Backup = Addr;
349     if (computeAddress(LHS, Addr) && computeAddress(RHS, Addr))
350       return true;
351     Addr = Backup;
352 
353     break;
354   }
355   case Instruction::Sub: {
356     // Subs of constants are common and easy enough.
357     const Value *LHS = U->getOperand(0);
358     const Value *RHS = U->getOperand(1);
359 
360     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
361       int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
362       if (TmpOffset >= 0) {
363         Addr.setOffset(TmpOffset);
364         return computeAddress(LHS, Addr);
365       }
366     }
367     break;
368   }
369   }
370   if (Addr.isSet()) {
371     return false;
372   }
373   unsigned Reg = getRegForValue(Obj);
374   if (Reg == 0)
375     return false;
376   Addr.setReg(Reg);
377   return Addr.getReg() != 0;
378 }
379 
380 void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
381   if (Addr.isRegBase()) {
382     unsigned Reg = Addr.getReg();
383     if (Reg == 0) {
384       Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
385                                                    : &WebAssembly::I32RegClass);
386       unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
387                                             : WebAssembly::CONST_I32;
388       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
389           .addImm(0);
390       Addr.setReg(Reg);
391     }
392   }
393 }
394 
395 void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
396                                                const MachineInstrBuilder &MIB,
397                                                MachineMemOperand *MMO) {
398   // Set the alignment operand (this is rewritten in SetP2AlignOperands).
399   // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
400   MIB.addImm(0);
401 
402   if (const GlobalValue *GV = Addr.getGlobalValue())
403     MIB.addGlobalAddress(GV, Addr.getOffset());
404   else
405     MIB.addImm(Addr.getOffset());
406 
407   if (Addr.isRegBase())
408     MIB.addReg(Addr.getReg());
409   else
410     MIB.addFrameIndex(Addr.getFI());
411 
412   MIB.addMemOperand(MMO);
413 }
414 
415 unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
416   return zeroExtendToI32(Reg, V, MVT::i1);
417 }
418 
419 unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V, bool &Not) {
420   if (const auto *ICmp = dyn_cast<ICmpInst>(V))
421     if (const ConstantInt *C = dyn_cast<ConstantInt>(ICmp->getOperand(1)))
422       if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(32)) {
423         Not = ICmp->isTrueWhenEqual();
424         return getRegForValue(ICmp->getOperand(0));
425       }
426 
427   Value *NotV;
428   if (match(V, m_Not(m_Value(NotV))) && V->getType()->isIntegerTy(32)) {
429     Not = true;
430     return getRegForValue(NotV);
431   }
432 
433   Not = false;
434   unsigned Reg = getRegForValue(V);
435   if (Reg == 0)
436     return 0;
437   return maskI1Value(Reg, V);
438 }
439 
440 unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
441                                               MVT::SimpleValueType From) {
442   if (Reg == 0)
443     return 0;
444 
445   switch (From) {
446   case MVT::i1:
447     // If the value is naturally an i1, we don't need to mask it. We only know
448     // if a value is naturally an i1 if it is definitely lowered by FastISel,
449     // not a DAG ISel fallback.
450     if (V != nullptr && isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr())
451       return copyValue(Reg);
452     break;
453   case MVT::i8:
454   case MVT::i16:
455     break;
456   case MVT::i32:
457     return copyValue(Reg);
458   default:
459     return 0;
460   }
461 
462   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
463   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
464           TII.get(WebAssembly::CONST_I32), Imm)
465       .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));
466 
467   unsigned Result = createResultReg(&WebAssembly::I32RegClass);
468   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
469           TII.get(WebAssembly::AND_I32), Result)
470       .addReg(Reg)
471       .addReg(Imm);
472 
473   return Result;
474 }
475 
476 unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
477                                               MVT::SimpleValueType From) {
478   if (Reg == 0)
479     return 0;
480 
481   switch (From) {
482   case MVT::i1:
483   case MVT::i8:
484   case MVT::i16:
485     break;
486   case MVT::i32:
487     return copyValue(Reg);
488   default:
489     return 0;
490   }
491 
492   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
493   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
494           TII.get(WebAssembly::CONST_I32), Imm)
495       .addImm(32 - MVT(From).getSizeInBits());
496 
497   unsigned Left = createResultReg(&WebAssembly::I32RegClass);
498   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
499           TII.get(WebAssembly::SHL_I32), Left)
500       .addReg(Reg)
501       .addReg(Imm);
502 
503   unsigned Right = createResultReg(&WebAssembly::I32RegClass);
504   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
505           TII.get(WebAssembly::SHR_S_I32), Right)
506       .addReg(Left)
507       .addReg(Imm);
508 
509   return Right;
510 }
511 
512 unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
513                                          MVT::SimpleValueType From,
514                                          MVT::SimpleValueType To) {
515   if (To == MVT::i64) {
516     if (From == MVT::i64)
517       return copyValue(Reg);
518 
519     Reg = zeroExtendToI32(Reg, V, From);
520 
521     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
522     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523             TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
524         .addReg(Reg);
525     return Result;
526   }
527 
528   if (To == MVT::i32)
529     return zeroExtendToI32(Reg, V, From);
530 
531   return 0;
532 }
533 
534 unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
535                                          MVT::SimpleValueType From,
536                                          MVT::SimpleValueType To) {
537   if (To == MVT::i64) {
538     if (From == MVT::i64)
539       return copyValue(Reg);
540 
541     Reg = signExtendToI32(Reg, V, From);
542 
543     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
544     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
545             TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
546         .addReg(Reg);
547     return Result;
548   }
549 
550   if (To == MVT::i32)
551     return signExtendToI32(Reg, V, From);
552 
553   return 0;
554 }
555 
556 unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
557   MVT::SimpleValueType From = getSimpleType(V->getType());
558   MVT::SimpleValueType To = getLegalType(From);
559   unsigned VReg = getRegForValue(V);
560   if (VReg == 0)
561     return 0;
562   return zeroExtend(VReg, V, From, To);
563 }
564 
565 unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
566   MVT::SimpleValueType From = getSimpleType(V->getType());
567   MVT::SimpleValueType To = getLegalType(From);
568   unsigned VReg = getRegForValue(V);
569   if (VReg == 0)
570     return 0;
571   return signExtend(VReg, V, From, To);
572 }
573 
574 unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
575                                                      bool IsSigned) {
576   return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
577 }
578 
579 unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
580   assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
581 
582   unsigned NotReg = createResultReg(&WebAssembly::I32RegClass);
583   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
584           TII.get(WebAssembly::EQZ_I32), NotReg)
585       .addReg(Reg);
586   return NotReg;
587 }
588 
589 unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
590   unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
591   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
592           ResultReg)
593       .addReg(Reg);
594   return ResultReg;
595 }
596 
597 unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
598   DenseMap<const AllocaInst *, int>::iterator SI =
599       FuncInfo.StaticAllocaMap.find(AI);
600 
601   if (SI != FuncInfo.StaticAllocaMap.end()) {
602     unsigned ResultReg =
603         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
604                                                : &WebAssembly::I32RegClass);
605     unsigned Opc =
606         Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
607     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
608         .addFrameIndex(SI->second);
609     return ResultReg;
610   }
611 
612   return 0;
613 }
614 
615 unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
616   if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
617     if (TLI.isPositionIndependent())
618       return 0;
619     if (GV->isThreadLocal())
620       return 0;
621     unsigned ResultReg =
622         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
623                                                : &WebAssembly::I32RegClass);
624     unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
625                                           : WebAssembly::CONST_I32;
626     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
627         .addGlobalAddress(GV);
628     return ResultReg;
629   }
630 
631   // Let target-independent code handle it.
632   return 0;
633 }
634 
635 bool WebAssemblyFastISel::fastLowerArguments() {
636   if (!FuncInfo.CanLowerReturn)
637     return false;
638 
639   const Function *F = FuncInfo.Fn;
640   if (F->isVarArg())
641     return false;
642 
643   unsigned I = 0;
644   for (auto const &Arg : F->args()) {
645     const AttributeList &Attrs = F->getAttributes();
646     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
647         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
648         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
649         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
650         Attrs.hasParamAttribute(I, Attribute::Nest))
651       return false;
652 
653     Type *ArgTy = Arg.getType();
654     if (ArgTy->isStructTy() || ArgTy->isArrayTy())
655       return false;
656     if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
657       return false;
658 
659     unsigned Opc;
660     const TargetRegisterClass *RC;
661     switch (getSimpleType(ArgTy)) {
662     case MVT::i1:
663     case MVT::i8:
664     case MVT::i16:
665     case MVT::i32:
666       Opc = WebAssembly::ARGUMENT_i32;
667       RC = &WebAssembly::I32RegClass;
668       break;
669     case MVT::i64:
670       Opc = WebAssembly::ARGUMENT_i64;
671       RC = &WebAssembly::I64RegClass;
672       break;
673     case MVT::f32:
674       Opc = WebAssembly::ARGUMENT_f32;
675       RC = &WebAssembly::F32RegClass;
676       break;
677     case MVT::f64:
678       Opc = WebAssembly::ARGUMENT_f64;
679       RC = &WebAssembly::F64RegClass;
680       break;
681     case MVT::v16i8:
682       Opc = WebAssembly::ARGUMENT_v16i8;
683       RC = &WebAssembly::V128RegClass;
684       break;
685     case MVT::v8i16:
686       Opc = WebAssembly::ARGUMENT_v8i16;
687       RC = &WebAssembly::V128RegClass;
688       break;
689     case MVT::v4i32:
690       Opc = WebAssembly::ARGUMENT_v4i32;
691       RC = &WebAssembly::V128RegClass;
692       break;
693     case MVT::v2i64:
694       Opc = WebAssembly::ARGUMENT_v2i64;
695       RC = &WebAssembly::V128RegClass;
696       break;
697     case MVT::v4f32:
698       Opc = WebAssembly::ARGUMENT_v4f32;
699       RC = &WebAssembly::V128RegClass;
700       break;
701     case MVT::v2f64:
702       Opc = WebAssembly::ARGUMENT_v2f64;
703       RC = &WebAssembly::V128RegClass;
704       break;
705     case MVT::exnref:
706       Opc = WebAssembly::ARGUMENT_exnref;
707       RC = &WebAssembly::EXNREFRegClass;
708       break;
709     default:
710       return false;
711     }
712     unsigned ResultReg = createResultReg(RC);
713     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
714         .addImm(I);
715     updateValueMap(&Arg, ResultReg);
716 
717     ++I;
718   }
719 
720   MRI.addLiveIn(WebAssembly::ARGUMENTS);
721 
722   auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
723   for (auto const &Arg : F->args()) {
724     MVT::SimpleValueType ArgTy = getLegalType(getSimpleType(Arg.getType()));
725     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
726       MFI->clearParamsAndResults();
727       return false;
728     }
729     MFI->addParam(ArgTy);
730   }
731 
732   if (!F->getReturnType()->isVoidTy()) {
733     MVT::SimpleValueType RetTy =
734         getLegalType(getSimpleType(F->getReturnType()));
735     if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
736       MFI->clearParamsAndResults();
737       return false;
738     }
739     MFI->addResult(RetTy);
740   }
741 
742   return true;
743 }
744 
745 bool WebAssemblyFastISel::selectCall(const Instruction *I) {
746   const auto *Call = cast<CallInst>(I);
747 
748   // TODO: Support tail calls in FastISel
749   if (Call->isMustTailCall() || Call->isInlineAsm() ||
750       Call->getFunctionType()->isVarArg())
751     return false;
752 
753   Function *Func = Call->getCalledFunction();
754   if (Func && Func->isIntrinsic())
755     return false;
756 
757   bool IsDirect = Func != nullptr;
758   if (!IsDirect && isa<ConstantExpr>(Call->getCalledValue()))
759     return false;
760 
761   FunctionType *FuncTy = Call->getFunctionType();
762   unsigned Opc = IsDirect ? WebAssembly::CALL : WebAssembly::CALL_INDIRECT;
763   bool IsVoid = FuncTy->getReturnType()->isVoidTy();
764   unsigned ResultReg;
765   if (!IsVoid) {
766     if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
767       return false;
768 
769     MVT::SimpleValueType RetTy = getSimpleType(Call->getType());
770     switch (RetTy) {
771     case MVT::i1:
772     case MVT::i8:
773     case MVT::i16:
774     case MVT::i32:
775       ResultReg = createResultReg(&WebAssembly::I32RegClass);
776       break;
777     case MVT::i64:
778       ResultReg = createResultReg(&WebAssembly::I64RegClass);
779       break;
780     case MVT::f32:
781       ResultReg = createResultReg(&WebAssembly::F32RegClass);
782       break;
783     case MVT::f64:
784       ResultReg = createResultReg(&WebAssembly::F64RegClass);
785       break;
786     case MVT::v16i8:
787       ResultReg = createResultReg(&WebAssembly::V128RegClass);
788       break;
789     case MVT::v8i16:
790       ResultReg = createResultReg(&WebAssembly::V128RegClass);
791       break;
792     case MVT::v4i32:
793       ResultReg = createResultReg(&WebAssembly::V128RegClass);
794       break;
795     case MVT::v2i64:
796       ResultReg = createResultReg(&WebAssembly::V128RegClass);
797       break;
798     case MVT::v4f32:
799       ResultReg = createResultReg(&WebAssembly::V128RegClass);
800       break;
801     case MVT::v2f64:
802       ResultReg = createResultReg(&WebAssembly::V128RegClass);
803       break;
804     case MVT::exnref:
805       ResultReg = createResultReg(&WebAssembly::EXNREFRegClass);
806       break;
807     default:
808       return false;
809     }
810   }
811 
812   SmallVector<unsigned, 8> Args;
813   for (unsigned I = 0, E = Call->getNumArgOperands(); I < E; ++I) {
814     Value *V = Call->getArgOperand(I);
815     MVT::SimpleValueType ArgTy = getSimpleType(V->getType());
816     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
817       return false;
818 
819     const AttributeList &Attrs = Call->getAttributes();
820     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
821         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
822         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
823         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
824         Attrs.hasParamAttribute(I, Attribute::Nest))
825       return false;
826 
827     unsigned Reg;
828 
829     if (Attrs.hasParamAttribute(I, Attribute::SExt))
830       Reg = getRegForSignedValue(V);
831     else if (Attrs.hasParamAttribute(I, Attribute::ZExt))
832       Reg = getRegForUnsignedValue(V);
833     else
834       Reg = getRegForValue(V);
835 
836     if (Reg == 0)
837       return false;
838 
839     Args.push_back(Reg);
840   }
841 
842   unsigned CalleeReg = 0;
843   if (!IsDirect) {
844     CalleeReg = getRegForValue(Call->getCalledValue());
845     if (!CalleeReg)
846       return false;
847   }
848 
849   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
850 
851   if (!IsVoid)
852     MIB.addReg(ResultReg, RegState::Define);
853 
854   if (IsDirect) {
855     MIB.addGlobalAddress(Func);
856   } else {
857     // Add placeholders for the type index and immediate flags
858     MIB.addImm(0);
859     MIB.addImm(0);
860   }
861 
862   for (unsigned ArgReg : Args)
863     MIB.addReg(ArgReg);
864 
865   if (!IsDirect)
866     MIB.addReg(CalleeReg);
867 
868   if (!IsVoid)
869     updateValueMap(Call, ResultReg);
870   return true;
871 }
872 
873 bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
874   const auto *Select = cast<SelectInst>(I);
875 
876   bool Not;
877   unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
878   if (CondReg == 0)
879     return false;
880 
881   unsigned TrueReg = getRegForValue(Select->getTrueValue());
882   if (TrueReg == 0)
883     return false;
884 
885   unsigned FalseReg = getRegForValue(Select->getFalseValue());
886   if (FalseReg == 0)
887     return false;
888 
889   if (Not)
890     std::swap(TrueReg, FalseReg);
891 
892   unsigned Opc;
893   const TargetRegisterClass *RC;
894   switch (getSimpleType(Select->getType())) {
895   case MVT::i1:
896   case MVT::i8:
897   case MVT::i16:
898   case MVT::i32:
899     Opc = WebAssembly::SELECT_I32;
900     RC = &WebAssembly::I32RegClass;
901     break;
902   case MVT::i64:
903     Opc = WebAssembly::SELECT_I64;
904     RC = &WebAssembly::I64RegClass;
905     break;
906   case MVT::f32:
907     Opc = WebAssembly::SELECT_F32;
908     RC = &WebAssembly::F32RegClass;
909     break;
910   case MVT::f64:
911     Opc = WebAssembly::SELECT_F64;
912     RC = &WebAssembly::F64RegClass;
913     break;
914   case MVT::exnref:
915     Opc = WebAssembly::SELECT_EXNREF;
916     RC = &WebAssembly::EXNREFRegClass;
917     break;
918   default:
919     return false;
920   }
921 
922   unsigned ResultReg = createResultReg(RC);
923   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
924       .addReg(TrueReg)
925       .addReg(FalseReg)
926       .addReg(CondReg);
927 
928   updateValueMap(Select, ResultReg);
929   return true;
930 }
931 
932 bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
933   const auto *Trunc = cast<TruncInst>(I);
934 
935   unsigned Reg = getRegForValue(Trunc->getOperand(0));
936   if (Reg == 0)
937     return false;
938 
939   if (Trunc->getOperand(0)->getType()->isIntegerTy(64)) {
940     unsigned Result = createResultReg(&WebAssembly::I32RegClass);
941     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
942             TII.get(WebAssembly::I32_WRAP_I64), Result)
943         .addReg(Reg);
944     Reg = Result;
945   }
946 
947   updateValueMap(Trunc, Reg);
948   return true;
949 }
950 
951 bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
952   const auto *ZExt = cast<ZExtInst>(I);
953 
954   const Value *Op = ZExt->getOperand(0);
955   MVT::SimpleValueType From = getSimpleType(Op->getType());
956   MVT::SimpleValueType To = getLegalType(getSimpleType(ZExt->getType()));
957   unsigned In = getRegForValue(Op);
958   if (In == 0)
959     return false;
960   unsigned Reg = zeroExtend(In, Op, From, To);
961   if (Reg == 0)
962     return false;
963 
964   updateValueMap(ZExt, Reg);
965   return true;
966 }
967 
968 bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
969   const auto *SExt = cast<SExtInst>(I);
970 
971   const Value *Op = SExt->getOperand(0);
972   MVT::SimpleValueType From = getSimpleType(Op->getType());
973   MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType()));
974   unsigned In = getRegForValue(Op);
975   if (In == 0)
976     return false;
977   unsigned Reg = signExtend(In, Op, From, To);
978   if (Reg == 0)
979     return false;
980 
981   updateValueMap(SExt, Reg);
982   return true;
983 }
984 
985 bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
986   const auto *ICmp = cast<ICmpInst>(I);
987 
988   bool I32 = getSimpleType(ICmp->getOperand(0)->getType()) != MVT::i64;
989   unsigned Opc;
990   bool IsSigned = false;
991   switch (ICmp->getPredicate()) {
992   case ICmpInst::ICMP_EQ:
993     Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
994     break;
995   case ICmpInst::ICMP_NE:
996     Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
997     break;
998   case ICmpInst::ICMP_UGT:
999     Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
1000     break;
1001   case ICmpInst::ICMP_UGE:
1002     Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
1003     break;
1004   case ICmpInst::ICMP_ULT:
1005     Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
1006     break;
1007   case ICmpInst::ICMP_ULE:
1008     Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
1009     break;
1010   case ICmpInst::ICMP_SGT:
1011     Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
1012     IsSigned = true;
1013     break;
1014   case ICmpInst::ICMP_SGE:
1015     Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
1016     IsSigned = true;
1017     break;
1018   case ICmpInst::ICMP_SLT:
1019     Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
1020     IsSigned = true;
1021     break;
1022   case ICmpInst::ICMP_SLE:
1023     Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
1024     IsSigned = true;
1025     break;
1026   default:
1027     return false;
1028   }
1029 
1030   unsigned LHS = getRegForPromotedValue(ICmp->getOperand(0), IsSigned);
1031   if (LHS == 0)
1032     return false;
1033 
1034   unsigned RHS = getRegForPromotedValue(ICmp->getOperand(1), IsSigned);
1035   if (RHS == 0)
1036     return false;
1037 
1038   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1039   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1040       .addReg(LHS)
1041       .addReg(RHS);
1042   updateValueMap(ICmp, ResultReg);
1043   return true;
1044 }
1045 
1046 bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
1047   const auto *FCmp = cast<FCmpInst>(I);
1048 
1049   unsigned LHS = getRegForValue(FCmp->getOperand(0));
1050   if (LHS == 0)
1051     return false;
1052 
1053   unsigned RHS = getRegForValue(FCmp->getOperand(1));
1054   if (RHS == 0)
1055     return false;
1056 
1057   bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64;
1058   unsigned Opc;
1059   bool Not = false;
1060   switch (FCmp->getPredicate()) {
1061   case FCmpInst::FCMP_OEQ:
1062     Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
1063     break;
1064   case FCmpInst::FCMP_UNE:
1065     Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
1066     break;
1067   case FCmpInst::FCMP_OGT:
1068     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1069     break;
1070   case FCmpInst::FCMP_OGE:
1071     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1072     break;
1073   case FCmpInst::FCMP_OLT:
1074     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1075     break;
1076   case FCmpInst::FCMP_OLE:
1077     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1078     break;
1079   case FCmpInst::FCMP_UGT:
1080     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1081     Not = true;
1082     break;
1083   case FCmpInst::FCMP_UGE:
1084     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1085     Not = true;
1086     break;
1087   case FCmpInst::FCMP_ULT:
1088     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1089     Not = true;
1090     break;
1091   case FCmpInst::FCMP_ULE:
1092     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1093     Not = true;
1094     break;
1095   default:
1096     return false;
1097   }
1098 
1099   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1100   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1101       .addReg(LHS)
1102       .addReg(RHS);
1103 
1104   if (Not)
1105     ResultReg = notValue(ResultReg);
1106 
1107   updateValueMap(FCmp, ResultReg);
1108   return true;
1109 }
1110 
1111 bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
1112   // Target-independent code can handle this, except it doesn't set the dead
1113   // flag on the ARGUMENTS clobber, so we have to do that manually in order
1114   // to satisfy code that expects this of isBitcast() instructions.
1115   EVT VT = TLI.getValueType(DL, I->getOperand(0)->getType());
1116   EVT RetVT = TLI.getValueType(DL, I->getType());
1117   if (!VT.isSimple() || !RetVT.isSimple())
1118     return false;
1119 
1120   unsigned In = getRegForValue(I->getOperand(0));
1121   if (In == 0)
1122     return false;
1123 
1124   if (VT == RetVT) {
1125     // No-op bitcast.
1126     updateValueMap(I, In);
1127     return true;
1128   }
1129 
1130   Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
1131                                         In, I->getOperand(0)->hasOneUse());
1132   if (!Reg)
1133     return false;
1134   MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
1135   --Iter;
1136   assert(Iter->isBitcast());
1137   Iter->setPhysRegsDeadExcept(ArrayRef<Register>(), TRI);
1138   updateValueMap(I, Reg);
1139   return true;
1140 }
1141 
1142 bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
1143   const auto *Load = cast<LoadInst>(I);
1144   if (Load->isAtomic())
1145     return false;
1146   if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
1147     return false;
1148 
1149   Address Addr;
1150   if (!computeAddress(Load->getPointerOperand(), Addr))
1151     return false;
1152 
1153   // TODO: Fold a following sign-/zero-extend into the load instruction.
1154 
1155   unsigned Opc;
1156   const TargetRegisterClass *RC;
1157   switch (getSimpleType(Load->getType())) {
1158   case MVT::i1:
1159   case MVT::i8:
1160     Opc = WebAssembly::LOAD8_U_I32;
1161     RC = &WebAssembly::I32RegClass;
1162     break;
1163   case MVT::i16:
1164     Opc = WebAssembly::LOAD16_U_I32;
1165     RC = &WebAssembly::I32RegClass;
1166     break;
1167   case MVT::i32:
1168     Opc = WebAssembly::LOAD_I32;
1169     RC = &WebAssembly::I32RegClass;
1170     break;
1171   case MVT::i64:
1172     Opc = WebAssembly::LOAD_I64;
1173     RC = &WebAssembly::I64RegClass;
1174     break;
1175   case MVT::f32:
1176     Opc = WebAssembly::LOAD_F32;
1177     RC = &WebAssembly::F32RegClass;
1178     break;
1179   case MVT::f64:
1180     Opc = WebAssembly::LOAD_F64;
1181     RC = &WebAssembly::F64RegClass;
1182     break;
1183   default:
1184     return false;
1185   }
1186 
1187   materializeLoadStoreOperands(Addr);
1188 
1189   unsigned ResultReg = createResultReg(RC);
1190   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1191                      ResultReg);
1192 
1193   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
1194 
1195   updateValueMap(Load, ResultReg);
1196   return true;
1197 }
1198 
1199 bool WebAssemblyFastISel::selectStore(const Instruction *I) {
1200   const auto *Store = cast<StoreInst>(I);
1201   if (Store->isAtomic())
1202     return false;
1203   if (!Subtarget->hasSIMD128() &&
1204       Store->getValueOperand()->getType()->isVectorTy())
1205     return false;
1206 
1207   Address Addr;
1208   if (!computeAddress(Store->getPointerOperand(), Addr))
1209     return false;
1210 
1211   unsigned Opc;
1212   bool VTIsi1 = false;
1213   switch (getSimpleType(Store->getValueOperand()->getType())) {
1214   case MVT::i1:
1215     VTIsi1 = true;
1216     LLVM_FALLTHROUGH;
1217   case MVT::i8:
1218     Opc = WebAssembly::STORE8_I32;
1219     break;
1220   case MVT::i16:
1221     Opc = WebAssembly::STORE16_I32;
1222     break;
1223   case MVT::i32:
1224     Opc = WebAssembly::STORE_I32;
1225     break;
1226   case MVT::i64:
1227     Opc = WebAssembly::STORE_I64;
1228     break;
1229   case MVT::f32:
1230     Opc = WebAssembly::STORE_F32;
1231     break;
1232   case MVT::f64:
1233     Opc = WebAssembly::STORE_F64;
1234     break;
1235   default:
1236     return false;
1237   }
1238 
1239   materializeLoadStoreOperands(Addr);
1240 
1241   unsigned ValueReg = getRegForValue(Store->getValueOperand());
1242   if (ValueReg == 0)
1243     return false;
1244   if (VTIsi1)
1245     ValueReg = maskI1Value(ValueReg, Store->getValueOperand());
1246 
1247   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1248 
1249   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Store));
1250 
1251   MIB.addReg(ValueReg);
1252   return true;
1253 }
1254 
1255 bool WebAssemblyFastISel::selectBr(const Instruction *I) {
1256   const auto *Br = cast<BranchInst>(I);
1257   if (Br->isUnconditional()) {
1258     MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
1259     fastEmitBranch(MSucc, Br->getDebugLoc());
1260     return true;
1261   }
1262 
1263   MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
1264   MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
1265 
1266   bool Not;
1267   unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
1268   if (CondReg == 0)
1269     return false;
1270 
1271   unsigned Opc = WebAssembly::BR_IF;
1272   if (Not)
1273     Opc = WebAssembly::BR_UNLESS;
1274 
1275   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1276       .addMBB(TBB)
1277       .addReg(CondReg);
1278 
1279   finishCondBranch(Br->getParent(), TBB, FBB);
1280   return true;
1281 }
1282 
1283 bool WebAssemblyFastISel::selectRet(const Instruction *I) {
1284   if (!FuncInfo.CanLowerReturn)
1285     return false;
1286 
1287   const auto *Ret = cast<ReturnInst>(I);
1288 
1289   if (Ret->getNumOperands() == 0) {
1290     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1291             TII.get(WebAssembly::RETURN));
1292     return true;
1293   }
1294 
1295   // TODO: support multiple return in FastISel
1296   if (Ret->getNumOperands() > 1)
1297     return false;
1298 
1299   Value *RV = Ret->getOperand(0);
1300   if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
1301     return false;
1302 
1303   switch (getSimpleType(RV->getType())) {
1304   case MVT::i1:
1305   case MVT::i8:
1306   case MVT::i16:
1307   case MVT::i32:
1308   case MVT::i64:
1309   case MVT::f32:
1310   case MVT::f64:
1311   case MVT::v16i8:
1312   case MVT::v8i16:
1313   case MVT::v4i32:
1314   case MVT::v2i64:
1315   case MVT::v4f32:
1316   case MVT::v2f64:
1317   case MVT::exnref:
1318     break;
1319   default:
1320     return false;
1321   }
1322 
1323   unsigned Reg;
1324   if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
1325     Reg = getRegForSignedValue(RV);
1326   else if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::ZExt))
1327     Reg = getRegForUnsignedValue(RV);
1328   else
1329     Reg = getRegForValue(RV);
1330 
1331   if (Reg == 0)
1332     return false;
1333 
1334   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1335           TII.get(WebAssembly::RETURN))
1336       .addReg(Reg);
1337   return true;
1338 }
1339 
1340 bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
1341   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1342           TII.get(WebAssembly::UNREACHABLE));
1343   return true;
1344 }
1345 
1346 bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
1347   switch (I->getOpcode()) {
1348   case Instruction::Call:
1349     if (selectCall(I))
1350       return true;
1351     break;
1352   case Instruction::Select:
1353     return selectSelect(I);
1354   case Instruction::Trunc:
1355     return selectTrunc(I);
1356   case Instruction::ZExt:
1357     return selectZExt(I);
1358   case Instruction::SExt:
1359     return selectSExt(I);
1360   case Instruction::ICmp:
1361     return selectICmp(I);
1362   case Instruction::FCmp:
1363     return selectFCmp(I);
1364   case Instruction::BitCast:
1365     return selectBitCast(I);
1366   case Instruction::Load:
1367     return selectLoad(I);
1368   case Instruction::Store:
1369     return selectStore(I);
1370   case Instruction::Br:
1371     return selectBr(I);
1372   case Instruction::Ret:
1373     return selectRet(I);
1374   case Instruction::Unreachable:
1375     return selectUnreachable(I);
1376   default:
1377     break;
1378   }
1379 
1380   // Fall back to target-independent instruction selection.
1381   return selectOperator(I, I->getOpcode());
1382 }
1383 
1384 FastISel *WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
1385                                       const TargetLibraryInfo *LibInfo) {
1386   return new WebAssemblyFastISel(FuncInfo, LibInfo);
1387 }
1388