1 //===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific support for the FastISel
11 /// class. Some of the target-specific code is generated by tablegen in the file
12 /// WebAssemblyGenFastISel.inc, which is #included here.
13 ///
14 /// TODO: kill flags
15 ///
16 //===----------------------------------------------------------------------===//
17 
18 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
19 #include "WebAssembly.h"
20 #include "WebAssemblyMachineFunctionInfo.h"
21 #include "WebAssemblySubtarget.h"
22 #include "WebAssemblyTargetMachine.h"
23 #include "llvm/Analysis/BranchProbabilityInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GetElementPtrTypeIterator.h"
34 #include "llvm/IR/GlobalAlias.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/IntrinsicInst.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/IR/PatternMatch.h"
40 
41 using namespace llvm;
42 using namespace PatternMatch;
43 
44 #define DEBUG_TYPE "wasm-fastisel"
45 
46 namespace {
47 
48 class WebAssemblyFastISel final : public FastISel {
49   // All possible address modes.
50   class Address {
51   public:
52     using BaseKind = enum { RegBase, FrameIndexBase };
53 
54   private:
55     BaseKind Kind = RegBase;
56     union {
57       unsigned Reg;
58       int FI;
59     } Base;
60 
61     int64_t Offset = 0;
62 
63     const GlobalValue *GV = nullptr;
64 
65   public:
66     // Innocuous defaults for our address.
67     Address() { Base.Reg = 0; }
68     void setKind(BaseKind K) {
69       assert(!isSet() && "Can't change kind with non-zero base");
70       Kind = K;
71     }
72     BaseKind getKind() const { return Kind; }
73     bool isRegBase() const { return Kind == RegBase; }
74     bool isFIBase() const { return Kind == FrameIndexBase; }
75     void setReg(unsigned Reg) {
76       assert(isRegBase() && "Invalid base register access!");
77       assert(Base.Reg == 0 && "Overwriting non-zero register");
78       Base.Reg = Reg;
79     }
80     unsigned getReg() const {
81       assert(isRegBase() && "Invalid base register access!");
82       return Base.Reg;
83     }
84     void setFI(unsigned FI) {
85       assert(isFIBase() && "Invalid base frame index access!");
86       assert(Base.FI == 0 && "Overwriting non-zero frame index");
87       Base.FI = FI;
88     }
89     unsigned getFI() const {
90       assert(isFIBase() && "Invalid base frame index access!");
91       return Base.FI;
92     }
93 
94     void setOffset(int64_t NewOffset) {
95       assert(NewOffset >= 0 && "Offsets must be non-negative");
96       Offset = NewOffset;
97     }
98     int64_t getOffset() const { return Offset; }
99     void setGlobalValue(const GlobalValue *G) { GV = G; }
100     const GlobalValue *getGlobalValue() const { return GV; }
101     bool isSet() const {
102       if (isRegBase()) {
103         return Base.Reg != 0;
104       } else {
105         return Base.FI != 0;
106       }
107     }
108   };
109 
110   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
111   /// right decision when generating code for different targets.
112   const WebAssemblySubtarget *Subtarget;
113   LLVMContext *Context;
114 
115 private:
116   // Utility helper routines
117   MVT::SimpleValueType getSimpleType(Type *Ty) {
118     EVT VT = TLI.getValueType(DL, Ty, /*HandleUnknown=*/true);
119     return VT.isSimple() ? VT.getSimpleVT().SimpleTy
120                          : MVT::INVALID_SIMPLE_VALUE_TYPE;
121   }
122   MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
123     switch (VT) {
124     case MVT::i1:
125     case MVT::i8:
126     case MVT::i16:
127       return MVT::i32;
128     case MVT::i32:
129     case MVT::i64:
130     case MVT::f32:
131     case MVT::f64:
132     case MVT::ExceptRef:
133       return VT;
134     case MVT::f16:
135       return MVT::f32;
136     case MVT::v16i8:
137     case MVT::v8i16:
138     case MVT::v4i32:
139     case MVT::v4f32:
140       if (Subtarget->hasSIMD128())
141         return VT;
142       break;
143     case MVT::v2i64:
144     case MVT::v2f64:
145       if (Subtarget->hasUnimplementedSIMD128())
146         return VT;
147       break;
148     default:
149       break;
150     }
151     return MVT::INVALID_SIMPLE_VALUE_TYPE;
152   }
153   bool computeAddress(const Value *Obj, Address &Addr);
154   void materializeLoadStoreOperands(Address &Addr);
155   void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
156                             MachineMemOperand *MMO);
157   unsigned maskI1Value(unsigned Reg, const Value *V);
158   unsigned getRegForI1Value(const Value *V, bool &Not);
159   unsigned zeroExtendToI32(unsigned Reg, const Value *V,
160                            MVT::SimpleValueType From);
161   unsigned signExtendToI32(unsigned Reg, const Value *V,
162                            MVT::SimpleValueType From);
163   unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
164                       MVT::SimpleValueType To);
165   unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
166                       MVT::SimpleValueType To);
167   unsigned getRegForUnsignedValue(const Value *V);
168   unsigned getRegForSignedValue(const Value *V);
169   unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
170   unsigned notValue(unsigned Reg);
171   unsigned copyValue(unsigned Reg);
172 
173   // Backend specific FastISel code.
174   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
175   unsigned fastMaterializeConstant(const Constant *C) override;
176   bool fastLowerArguments() override;
177 
178   // Selection routines.
179   bool selectCall(const Instruction *I);
180   bool selectSelect(const Instruction *I);
181   bool selectTrunc(const Instruction *I);
182   bool selectZExt(const Instruction *I);
183   bool selectSExt(const Instruction *I);
184   bool selectICmp(const Instruction *I);
185   bool selectFCmp(const Instruction *I);
186   bool selectBitCast(const Instruction *I);
187   bool selectLoad(const Instruction *I);
188   bool selectStore(const Instruction *I);
189   bool selectBr(const Instruction *I);
190   bool selectRet(const Instruction *I);
191   bool selectUnreachable(const Instruction *I);
192 
193 public:
194   // Backend specific FastISel code.
195   WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
196                       const TargetLibraryInfo *LibInfo)
197       : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
198     Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
199     Context = &FuncInfo.Fn->getContext();
200   }
201 
202   bool fastSelectInstruction(const Instruction *I) override;
203 
204 #include "WebAssemblyGenFastISel.inc"
205 };
206 
207 } // end anonymous namespace
208 
209 bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
210   const User *U = nullptr;
211   unsigned Opcode = Instruction::UserOp1;
212   if (const auto *I = dyn_cast<Instruction>(Obj)) {
213     // Don't walk into other basic blocks unless the object is an alloca from
214     // another block, otherwise it may not have a virtual register assigned.
215     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
216         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
217       Opcode = I->getOpcode();
218       U = I;
219     }
220   } else if (const auto *C = dyn_cast<ConstantExpr>(Obj)) {
221     Opcode = C->getOpcode();
222     U = C;
223   }
224 
225   if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
226     if (Ty->getAddressSpace() > 255)
227       // Fast instruction selection doesn't support the special
228       // address spaces.
229       return false;
230 
231   if (const auto *GV = dyn_cast<GlobalValue>(Obj)) {
232     if (TLI.isPositionIndependent())
233       return false;
234     if (Addr.getGlobalValue())
235       return false;
236     Addr.setGlobalValue(GV);
237     return true;
238   }
239 
240   switch (Opcode) {
241   default:
242     break;
243   case Instruction::BitCast: {
244     // Look through bitcasts.
245     return computeAddress(U->getOperand(0), Addr);
246   }
247   case Instruction::IntToPtr: {
248     // Look past no-op inttoptrs.
249     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
250         TLI.getPointerTy(DL))
251       return computeAddress(U->getOperand(0), Addr);
252     break;
253   }
254   case Instruction::PtrToInt: {
255     // Look past no-op ptrtoints.
256     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
257       return computeAddress(U->getOperand(0), Addr);
258     break;
259   }
260   case Instruction::GetElementPtr: {
261     Address SavedAddr = Addr;
262     uint64_t TmpOffset = Addr.getOffset();
263     // Non-inbounds geps can wrap; wasm's offsets can't.
264     if (!cast<GEPOperator>(U)->isInBounds())
265       goto unsupported_gep;
266     // Iterate through the GEP folding the constants into offsets where
267     // we can.
268     for (gep_type_iterator GTI = gep_type_begin(U), E = gep_type_end(U);
269          GTI != E; ++GTI) {
270       const Value *Op = GTI.getOperand();
271       if (StructType *STy = GTI.getStructTypeOrNull()) {
272         const StructLayout *SL = DL.getStructLayout(STy);
273         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
274         TmpOffset += SL->getElementOffset(Idx);
275       } else {
276         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
277         for (;;) {
278           if (const auto *CI = dyn_cast<ConstantInt>(Op)) {
279             // Constant-offset addressing.
280             TmpOffset += CI->getSExtValue() * S;
281             break;
282           }
283           if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
284             // An unscaled add of a register. Set it as the new base.
285             unsigned Reg = getRegForValue(Op);
286             if (Reg == 0)
287               return false;
288             Addr.setReg(Reg);
289             break;
290           }
291           if (canFoldAddIntoGEP(U, Op)) {
292             // A compatible add with a constant operand. Fold the constant.
293             auto *CI = cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
294             TmpOffset += CI->getSExtValue() * S;
295             // Iterate on the other operand.
296             Op = cast<AddOperator>(Op)->getOperand(0);
297             continue;
298           }
299           // Unsupported
300           goto unsupported_gep;
301         }
302       }
303     }
304     // Don't fold in negative offsets.
305     if (int64_t(TmpOffset) >= 0) {
306       // Try to grab the base operand now.
307       Addr.setOffset(TmpOffset);
308       if (computeAddress(U->getOperand(0), Addr))
309         return true;
310     }
311     // We failed, restore everything and try the other options.
312     Addr = SavedAddr;
313   unsupported_gep:
314     break;
315   }
316   case Instruction::Alloca: {
317     const auto *AI = cast<AllocaInst>(Obj);
318     DenseMap<const AllocaInst *, int>::iterator SI =
319         FuncInfo.StaticAllocaMap.find(AI);
320     if (SI != FuncInfo.StaticAllocaMap.end()) {
321       if (Addr.isSet()) {
322         return false;
323       }
324       Addr.setKind(Address::FrameIndexBase);
325       Addr.setFI(SI->second);
326       return true;
327     }
328     break;
329   }
330   case Instruction::Add: {
331     // Adds of constants are common and easy enough.
332     const Value *LHS = U->getOperand(0);
333     const Value *RHS = U->getOperand(1);
334 
335     if (isa<ConstantInt>(LHS))
336       std::swap(LHS, RHS);
337 
338     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
339       uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
340       if (int64_t(TmpOffset) >= 0) {
341         Addr.setOffset(TmpOffset);
342         return computeAddress(LHS, Addr);
343       }
344     }
345 
346     Address Backup = Addr;
347     if (computeAddress(LHS, Addr) && computeAddress(RHS, Addr))
348       return true;
349     Addr = Backup;
350 
351     break;
352   }
353   case Instruction::Sub: {
354     // Subs of constants are common and easy enough.
355     const Value *LHS = U->getOperand(0);
356     const Value *RHS = U->getOperand(1);
357 
358     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
359       int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
360       if (TmpOffset >= 0) {
361         Addr.setOffset(TmpOffset);
362         return computeAddress(LHS, Addr);
363       }
364     }
365     break;
366   }
367   }
368   if (Addr.isSet()) {
369     return false;
370   }
371   unsigned Reg = getRegForValue(Obj);
372   if (Reg == 0)
373     return false;
374   Addr.setReg(Reg);
375   return Addr.getReg() != 0;
376 }
377 
378 void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
379   if (Addr.isRegBase()) {
380     unsigned Reg = Addr.getReg();
381     if (Reg == 0) {
382       Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
383                                                    : &WebAssembly::I32RegClass);
384       unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
385                                             : WebAssembly::CONST_I32;
386       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
387           .addImm(0);
388       Addr.setReg(Reg);
389     }
390   }
391 }
392 
393 void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
394                                                const MachineInstrBuilder &MIB,
395                                                MachineMemOperand *MMO) {
396   // Set the alignment operand (this is rewritten in SetP2AlignOperands).
397   // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
398   MIB.addImm(0);
399 
400   if (const GlobalValue *GV = Addr.getGlobalValue())
401     MIB.addGlobalAddress(GV, Addr.getOffset());
402   else
403     MIB.addImm(Addr.getOffset());
404 
405   if (Addr.isRegBase())
406     MIB.addReg(Addr.getReg());
407   else
408     MIB.addFrameIndex(Addr.getFI());
409 
410   MIB.addMemOperand(MMO);
411 }
412 
413 unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
414   return zeroExtendToI32(Reg, V, MVT::i1);
415 }
416 
417 unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V, bool &Not) {
418   if (const auto *ICmp = dyn_cast<ICmpInst>(V))
419     if (const ConstantInt *C = dyn_cast<ConstantInt>(ICmp->getOperand(1)))
420       if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(32)) {
421         Not = ICmp->isTrueWhenEqual();
422         return getRegForValue(ICmp->getOperand(0));
423       }
424 
425   Value *NotV;
426   if (match(V, m_Not(m_Value(NotV))) && V->getType()->isIntegerTy(32)) {
427     Not = true;
428     return getRegForValue(NotV);
429   }
430 
431   Not = false;
432   unsigned Reg = getRegForValue(V);
433   if (Reg == 0)
434     return 0;
435   return maskI1Value(Reg, V);
436 }
437 
438 unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
439                                               MVT::SimpleValueType From) {
440   if (Reg == 0)
441     return 0;
442 
443   switch (From) {
444   case MVT::i1:
445     // If the value is naturally an i1, we don't need to mask it. We only know
446     // if a value is naturally an i1 if it is definitely lowered by FastISel,
447     // not a DAG ISel fallback.
448     if (V != nullptr && isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr())
449       return copyValue(Reg);
450     break;
451   case MVT::i8:
452   case MVT::i16:
453     break;
454   case MVT::i32:
455     return copyValue(Reg);
456   default:
457     return 0;
458   }
459 
460   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
461   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
462           TII.get(WebAssembly::CONST_I32), Imm)
463       .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));
464 
465   unsigned Result = createResultReg(&WebAssembly::I32RegClass);
466   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
467           TII.get(WebAssembly::AND_I32), Result)
468       .addReg(Reg)
469       .addReg(Imm);
470 
471   return Result;
472 }
473 
474 unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
475                                               MVT::SimpleValueType From) {
476   if (Reg == 0)
477     return 0;
478 
479   switch (From) {
480   case MVT::i1:
481   case MVT::i8:
482   case MVT::i16:
483     break;
484   case MVT::i32:
485     return copyValue(Reg);
486   default:
487     return 0;
488   }
489 
490   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
491   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
492           TII.get(WebAssembly::CONST_I32), Imm)
493       .addImm(32 - MVT(From).getSizeInBits());
494 
495   unsigned Left = createResultReg(&WebAssembly::I32RegClass);
496   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
497           TII.get(WebAssembly::SHL_I32), Left)
498       .addReg(Reg)
499       .addReg(Imm);
500 
501   unsigned Right = createResultReg(&WebAssembly::I32RegClass);
502   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
503           TII.get(WebAssembly::SHR_S_I32), Right)
504       .addReg(Left)
505       .addReg(Imm);
506 
507   return Right;
508 }
509 
510 unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
511                                          MVT::SimpleValueType From,
512                                          MVT::SimpleValueType To) {
513   if (To == MVT::i64) {
514     if (From == MVT::i64)
515       return copyValue(Reg);
516 
517     Reg = zeroExtendToI32(Reg, V, From);
518 
519     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
520     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
521             TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
522         .addReg(Reg);
523     return Result;
524   }
525 
526   return zeroExtendToI32(Reg, V, From);
527 }
528 
529 unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
530                                          MVT::SimpleValueType From,
531                                          MVT::SimpleValueType To) {
532   if (To == MVT::i64) {
533     if (From == MVT::i64)
534       return copyValue(Reg);
535 
536     Reg = signExtendToI32(Reg, V, From);
537 
538     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
539     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
540             TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
541         .addReg(Reg);
542     return Result;
543   }
544 
545   return signExtendToI32(Reg, V, From);
546 }
547 
548 unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
549   MVT::SimpleValueType From = getSimpleType(V->getType());
550   MVT::SimpleValueType To = getLegalType(From);
551   unsigned VReg = getRegForValue(V);
552   if (VReg == 0)
553     return 0;
554   return zeroExtend(VReg, V, From, To);
555 }
556 
557 unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
558   MVT::SimpleValueType From = getSimpleType(V->getType());
559   MVT::SimpleValueType To = getLegalType(From);
560   unsigned VReg = getRegForValue(V);
561   if (VReg == 0)
562     return 0;
563   return signExtend(VReg, V, From, To);
564 }
565 
566 unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
567                                                      bool IsSigned) {
568   return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
569 }
570 
571 unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
572   assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
573 
574   unsigned NotReg = createResultReg(&WebAssembly::I32RegClass);
575   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
576           TII.get(WebAssembly::EQZ_I32), NotReg)
577       .addReg(Reg);
578   return NotReg;
579 }
580 
581 unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
582   unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
583   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
584           ResultReg)
585       .addReg(Reg);
586   return ResultReg;
587 }
588 
589 unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
590   DenseMap<const AllocaInst *, int>::iterator SI =
591       FuncInfo.StaticAllocaMap.find(AI);
592 
593   if (SI != FuncInfo.StaticAllocaMap.end()) {
594     unsigned ResultReg =
595         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
596                                                : &WebAssembly::I32RegClass);
597     unsigned Opc =
598         Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
599     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
600         .addFrameIndex(SI->second);
601     return ResultReg;
602   }
603 
604   return 0;
605 }
606 
607 unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
608   if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
609     if (TLI.isPositionIndependent())
610       return 0;
611     unsigned ResultReg =
612         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
613                                                : &WebAssembly::I32RegClass);
614     unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
615                                           : WebAssembly::CONST_I32;
616     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
617         .addGlobalAddress(GV);
618     return ResultReg;
619   }
620 
621   // Let target-independent code handle it.
622   return 0;
623 }
624 
625 bool WebAssemblyFastISel::fastLowerArguments() {
626   if (!FuncInfo.CanLowerReturn)
627     return false;
628 
629   const Function *F = FuncInfo.Fn;
630   if (F->isVarArg())
631     return false;
632 
633   unsigned I = 0;
634   for (auto const &Arg : F->args()) {
635     const AttributeList &Attrs = F->getAttributes();
636     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
637         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
638         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
639         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
640         Attrs.hasParamAttribute(I, Attribute::Nest))
641       return false;
642 
643     Type *ArgTy = Arg.getType();
644     if (ArgTy->isStructTy() || ArgTy->isArrayTy())
645       return false;
646     if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
647       return false;
648 
649     unsigned Opc;
650     const TargetRegisterClass *RC;
651     switch (getSimpleType(ArgTy)) {
652     case MVT::i1:
653     case MVT::i8:
654     case MVT::i16:
655     case MVT::i32:
656       Opc = WebAssembly::ARGUMENT_i32;
657       RC = &WebAssembly::I32RegClass;
658       break;
659     case MVT::i64:
660       Opc = WebAssembly::ARGUMENT_i64;
661       RC = &WebAssembly::I64RegClass;
662       break;
663     case MVT::f32:
664       Opc = WebAssembly::ARGUMENT_f32;
665       RC = &WebAssembly::F32RegClass;
666       break;
667     case MVT::f64:
668       Opc = WebAssembly::ARGUMENT_f64;
669       RC = &WebAssembly::F64RegClass;
670       break;
671     case MVT::v16i8:
672       Opc = WebAssembly::ARGUMENT_v16i8;
673       RC = &WebAssembly::V128RegClass;
674       break;
675     case MVT::v8i16:
676       Opc = WebAssembly::ARGUMENT_v8i16;
677       RC = &WebAssembly::V128RegClass;
678       break;
679     case MVT::v4i32:
680       Opc = WebAssembly::ARGUMENT_v4i32;
681       RC = &WebAssembly::V128RegClass;
682       break;
683     case MVT::v2i64:
684       Opc = WebAssembly::ARGUMENT_v2i64;
685       RC = &WebAssembly::V128RegClass;
686       break;
687     case MVT::v4f32:
688       Opc = WebAssembly::ARGUMENT_v4f32;
689       RC = &WebAssembly::V128RegClass;
690       break;
691     case MVT::v2f64:
692       Opc = WebAssembly::ARGUMENT_v2f64;
693       RC = &WebAssembly::V128RegClass;
694       break;
695     case MVT::ExceptRef:
696       Opc = WebAssembly::ARGUMENT_ExceptRef;
697       RC = &WebAssembly::EXCEPT_REFRegClass;
698       break;
699     default:
700       return false;
701     }
702     unsigned ResultReg = createResultReg(RC);
703     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
704         .addImm(I);
705     updateValueMap(&Arg, ResultReg);
706 
707     ++I;
708   }
709 
710   MRI.addLiveIn(WebAssembly::ARGUMENTS);
711 
712   auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
713   for (auto const &Arg : F->args()) {
714     MVT::SimpleValueType ArgTy = getLegalType(getSimpleType(Arg.getType()));
715     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
716       MFI->clearParamsAndResults();
717       return false;
718     }
719     MFI->addParam(ArgTy);
720   }
721 
722   if (!F->getReturnType()->isVoidTy()) {
723     MVT::SimpleValueType RetTy =
724         getLegalType(getSimpleType(F->getReturnType()));
725     if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
726       MFI->clearParamsAndResults();
727       return false;
728     }
729     MFI->addResult(RetTy);
730   }
731 
732   return true;
733 }
734 
735 bool WebAssemblyFastISel::selectCall(const Instruction *I) {
736   const auto *Call = cast<CallInst>(I);
737 
738   if (Call->isMustTailCall() || Call->isInlineAsm() ||
739       Call->getFunctionType()->isVarArg())
740     return false;
741 
742   Function *Func = Call->getCalledFunction();
743   if (Func && Func->isIntrinsic())
744     return false;
745 
746   bool IsDirect = Func != nullptr;
747   if (!IsDirect && isa<ConstantExpr>(Call->getCalledValue()))
748     return false;
749 
750   FunctionType *FuncTy = Call->getFunctionType();
751   unsigned Opc;
752   bool IsVoid = FuncTy->getReturnType()->isVoidTy();
753   unsigned ResultReg;
754   if (IsVoid) {
755     Opc = IsDirect ? WebAssembly::CALL_VOID : WebAssembly::PCALL_INDIRECT_VOID;
756   } else {
757     if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
758       return false;
759 
760     MVT::SimpleValueType RetTy = getSimpleType(Call->getType());
761     switch (RetTy) {
762     case MVT::i1:
763     case MVT::i8:
764     case MVT::i16:
765     case MVT::i32:
766       Opc = IsDirect ? WebAssembly::CALL_I32 : WebAssembly::PCALL_INDIRECT_I32;
767       ResultReg = createResultReg(&WebAssembly::I32RegClass);
768       break;
769     case MVT::i64:
770       Opc = IsDirect ? WebAssembly::CALL_I64 : WebAssembly::PCALL_INDIRECT_I64;
771       ResultReg = createResultReg(&WebAssembly::I64RegClass);
772       break;
773     case MVT::f32:
774       Opc = IsDirect ? WebAssembly::CALL_F32 : WebAssembly::PCALL_INDIRECT_F32;
775       ResultReg = createResultReg(&WebAssembly::F32RegClass);
776       break;
777     case MVT::f64:
778       Opc = IsDirect ? WebAssembly::CALL_F64 : WebAssembly::PCALL_INDIRECT_F64;
779       ResultReg = createResultReg(&WebAssembly::F64RegClass);
780       break;
781     case MVT::v16i8:
782       Opc = IsDirect ? WebAssembly::CALL_v16i8
783                      : WebAssembly::PCALL_INDIRECT_v16i8;
784       ResultReg = createResultReg(&WebAssembly::V128RegClass);
785       break;
786     case MVT::v8i16:
787       Opc = IsDirect ? WebAssembly::CALL_v8i16
788                      : WebAssembly::PCALL_INDIRECT_v8i16;
789       ResultReg = createResultReg(&WebAssembly::V128RegClass);
790       break;
791     case MVT::v4i32:
792       Opc = IsDirect ? WebAssembly::CALL_v4i32
793                      : WebAssembly::PCALL_INDIRECT_v4i32;
794       ResultReg = createResultReg(&WebAssembly::V128RegClass);
795       break;
796     case MVT::v2i64:
797       Opc = IsDirect ? WebAssembly::CALL_v2i64
798                      : WebAssembly::PCALL_INDIRECT_v2i64;
799       ResultReg = createResultReg(&WebAssembly::V128RegClass);
800       break;
801     case MVT::v4f32:
802       Opc = IsDirect ? WebAssembly::CALL_v4f32
803                      : WebAssembly::PCALL_INDIRECT_v4f32;
804       ResultReg = createResultReg(&WebAssembly::V128RegClass);
805       break;
806     case MVT::v2f64:
807       Opc = IsDirect ? WebAssembly::CALL_v2f64
808                      : WebAssembly::PCALL_INDIRECT_v2f64;
809       ResultReg = createResultReg(&WebAssembly::V128RegClass);
810       break;
811     case MVT::ExceptRef:
812       Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
813                      : WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
814       ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
815       break;
816     default:
817       return false;
818     }
819   }
820 
821   SmallVector<unsigned, 8> Args;
822   for (unsigned I = 0, E = Call->getNumArgOperands(); I < E; ++I) {
823     Value *V = Call->getArgOperand(I);
824     MVT::SimpleValueType ArgTy = getSimpleType(V->getType());
825     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
826       return false;
827 
828     const AttributeList &Attrs = Call->getAttributes();
829     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
830         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
831         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
832         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
833         Attrs.hasParamAttribute(I, Attribute::Nest))
834       return false;
835 
836     unsigned Reg;
837 
838     if (Attrs.hasParamAttribute(I, Attribute::SExt))
839       Reg = getRegForSignedValue(V);
840     else if (Attrs.hasParamAttribute(I, Attribute::ZExt))
841       Reg = getRegForUnsignedValue(V);
842     else
843       Reg = getRegForValue(V);
844 
845     if (Reg == 0)
846       return false;
847 
848     Args.push_back(Reg);
849   }
850 
851   unsigned CalleeReg = 0;
852   if (!IsDirect) {
853     CalleeReg = getRegForValue(Call->getCalledValue());
854     if (!CalleeReg)
855       return false;
856   }
857 
858   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
859 
860   if (!IsVoid)
861     MIB.addReg(ResultReg, RegState::Define);
862 
863   if (IsDirect)
864     MIB.addGlobalAddress(Func);
865   else
866     MIB.addReg(CalleeReg);
867 
868   for (unsigned ArgReg : Args)
869     MIB.addReg(ArgReg);
870 
871   if (!IsVoid)
872     updateValueMap(Call, ResultReg);
873   return true;
874 }
875 
876 bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
877   const auto *Select = cast<SelectInst>(I);
878 
879   bool Not;
880   unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
881   if (CondReg == 0)
882     return false;
883 
884   unsigned TrueReg = getRegForValue(Select->getTrueValue());
885   if (TrueReg == 0)
886     return false;
887 
888   unsigned FalseReg = getRegForValue(Select->getFalseValue());
889   if (FalseReg == 0)
890     return false;
891 
892   if (Not)
893     std::swap(TrueReg, FalseReg);
894 
895   unsigned Opc;
896   const TargetRegisterClass *RC;
897   switch (getSimpleType(Select->getType())) {
898   case MVT::i1:
899   case MVT::i8:
900   case MVT::i16:
901   case MVT::i32:
902     Opc = WebAssembly::SELECT_I32;
903     RC = &WebAssembly::I32RegClass;
904     break;
905   case MVT::i64:
906     Opc = WebAssembly::SELECT_I64;
907     RC = &WebAssembly::I64RegClass;
908     break;
909   case MVT::f32:
910     Opc = WebAssembly::SELECT_F32;
911     RC = &WebAssembly::F32RegClass;
912     break;
913   case MVT::f64:
914     Opc = WebAssembly::SELECT_F64;
915     RC = &WebAssembly::F64RegClass;
916     break;
917   case MVT::ExceptRef:
918     Opc = WebAssembly::SELECT_EXCEPT_REF;
919     RC = &WebAssembly::EXCEPT_REFRegClass;
920     break;
921   default:
922     return false;
923   }
924 
925   unsigned ResultReg = createResultReg(RC);
926   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
927       .addReg(TrueReg)
928       .addReg(FalseReg)
929       .addReg(CondReg);
930 
931   updateValueMap(Select, ResultReg);
932   return true;
933 }
934 
935 bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
936   const auto *Trunc = cast<TruncInst>(I);
937 
938   unsigned Reg = getRegForValue(Trunc->getOperand(0));
939   if (Reg == 0)
940     return false;
941 
942   if (Trunc->getOperand(0)->getType()->isIntegerTy(64)) {
943     unsigned Result = createResultReg(&WebAssembly::I32RegClass);
944     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
945             TII.get(WebAssembly::I32_WRAP_I64), Result)
946         .addReg(Reg);
947     Reg = Result;
948   }
949 
950   updateValueMap(Trunc, Reg);
951   return true;
952 }
953 
954 bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
955   const auto *ZExt = cast<ZExtInst>(I);
956 
957   const Value *Op = ZExt->getOperand(0);
958   MVT::SimpleValueType From = getSimpleType(Op->getType());
959   MVT::SimpleValueType To = getLegalType(getSimpleType(ZExt->getType()));
960   unsigned In = getRegForValue(Op);
961   if (In == 0)
962     return false;
963   unsigned Reg = zeroExtend(In, Op, From, To);
964   if (Reg == 0)
965     return false;
966 
967   updateValueMap(ZExt, Reg);
968   return true;
969 }
970 
971 bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
972   const auto *SExt = cast<SExtInst>(I);
973 
974   const Value *Op = SExt->getOperand(0);
975   MVT::SimpleValueType From = getSimpleType(Op->getType());
976   MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType()));
977   unsigned In = getRegForValue(Op);
978   if (In == 0)
979     return false;
980   unsigned Reg = signExtend(In, Op, From, To);
981   if (Reg == 0)
982     return false;
983 
984   updateValueMap(SExt, Reg);
985   return true;
986 }
987 
988 bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
989   const auto *ICmp = cast<ICmpInst>(I);
990 
991   bool I32 = getSimpleType(ICmp->getOperand(0)->getType()) != MVT::i64;
992   unsigned Opc;
993   bool IsSigned = false;
994   switch (ICmp->getPredicate()) {
995   case ICmpInst::ICMP_EQ:
996     Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
997     break;
998   case ICmpInst::ICMP_NE:
999     Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
1000     break;
1001   case ICmpInst::ICMP_UGT:
1002     Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
1003     break;
1004   case ICmpInst::ICMP_UGE:
1005     Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
1006     break;
1007   case ICmpInst::ICMP_ULT:
1008     Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
1009     break;
1010   case ICmpInst::ICMP_ULE:
1011     Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
1012     break;
1013   case ICmpInst::ICMP_SGT:
1014     Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
1015     IsSigned = true;
1016     break;
1017   case ICmpInst::ICMP_SGE:
1018     Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
1019     IsSigned = true;
1020     break;
1021   case ICmpInst::ICMP_SLT:
1022     Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
1023     IsSigned = true;
1024     break;
1025   case ICmpInst::ICMP_SLE:
1026     Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
1027     IsSigned = true;
1028     break;
1029   default:
1030     return false;
1031   }
1032 
1033   unsigned LHS = getRegForPromotedValue(ICmp->getOperand(0), IsSigned);
1034   if (LHS == 0)
1035     return false;
1036 
1037   unsigned RHS = getRegForPromotedValue(ICmp->getOperand(1), IsSigned);
1038   if (RHS == 0)
1039     return false;
1040 
1041   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1042   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1043       .addReg(LHS)
1044       .addReg(RHS);
1045   updateValueMap(ICmp, ResultReg);
1046   return true;
1047 }
1048 
1049 bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
1050   const auto *FCmp = cast<FCmpInst>(I);
1051 
1052   unsigned LHS = getRegForValue(FCmp->getOperand(0));
1053   if (LHS == 0)
1054     return false;
1055 
1056   unsigned RHS = getRegForValue(FCmp->getOperand(1));
1057   if (RHS == 0)
1058     return false;
1059 
1060   bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64;
1061   unsigned Opc;
1062   bool Not = false;
1063   switch (FCmp->getPredicate()) {
1064   case FCmpInst::FCMP_OEQ:
1065     Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
1066     break;
1067   case FCmpInst::FCMP_UNE:
1068     Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
1069     break;
1070   case FCmpInst::FCMP_OGT:
1071     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1072     break;
1073   case FCmpInst::FCMP_OGE:
1074     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1075     break;
1076   case FCmpInst::FCMP_OLT:
1077     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1078     break;
1079   case FCmpInst::FCMP_OLE:
1080     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1081     break;
1082   case FCmpInst::FCMP_UGT:
1083     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1084     Not = true;
1085     break;
1086   case FCmpInst::FCMP_UGE:
1087     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1088     Not = true;
1089     break;
1090   case FCmpInst::FCMP_ULT:
1091     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1092     Not = true;
1093     break;
1094   case FCmpInst::FCMP_ULE:
1095     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1096     Not = true;
1097     break;
1098   default:
1099     return false;
1100   }
1101 
1102   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1103   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1104       .addReg(LHS)
1105       .addReg(RHS);
1106 
1107   if (Not)
1108     ResultReg = notValue(ResultReg);
1109 
1110   updateValueMap(FCmp, ResultReg);
1111   return true;
1112 }
1113 
1114 bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
1115   // Target-independent code can handle this, except it doesn't set the dead
1116   // flag on the ARGUMENTS clobber, so we have to do that manually in order
1117   // to satisfy code that expects this of isBitcast() instructions.
1118   EVT VT = TLI.getValueType(DL, I->getOperand(0)->getType());
1119   EVT RetVT = TLI.getValueType(DL, I->getType());
1120   if (!VT.isSimple() || !RetVT.isSimple())
1121     return false;
1122 
1123   unsigned In = getRegForValue(I->getOperand(0));
1124   if (In == 0)
1125     return false;
1126 
1127   if (VT == RetVT) {
1128     // No-op bitcast.
1129     updateValueMap(I, In);
1130     return true;
1131   }
1132 
1133   unsigned Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
1134                                         In, I->getOperand(0)->hasOneUse());
1135   if (!Reg)
1136     return false;
1137   MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
1138   --Iter;
1139   assert(Iter->isBitcast());
1140   Iter->setPhysRegsDeadExcept(ArrayRef<unsigned>(), TRI);
1141   updateValueMap(I, Reg);
1142   return true;
1143 }
1144 
1145 bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
1146   const auto *Load = cast<LoadInst>(I);
1147   if (Load->isAtomic())
1148     return false;
1149   if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
1150     return false;
1151 
1152   Address Addr;
1153   if (!computeAddress(Load->getPointerOperand(), Addr))
1154     return false;
1155 
1156   // TODO: Fold a following sign-/zero-extend into the load instruction.
1157 
1158   unsigned Opc;
1159   const TargetRegisterClass *RC;
1160   switch (getSimpleType(Load->getType())) {
1161   case MVT::i1:
1162   case MVT::i8:
1163     Opc = WebAssembly::LOAD8_U_I32;
1164     RC = &WebAssembly::I32RegClass;
1165     break;
1166   case MVT::i16:
1167     Opc = WebAssembly::LOAD16_U_I32;
1168     RC = &WebAssembly::I32RegClass;
1169     break;
1170   case MVT::i32:
1171     Opc = WebAssembly::LOAD_I32;
1172     RC = &WebAssembly::I32RegClass;
1173     break;
1174   case MVT::i64:
1175     Opc = WebAssembly::LOAD_I64;
1176     RC = &WebAssembly::I64RegClass;
1177     break;
1178   case MVT::f32:
1179     Opc = WebAssembly::LOAD_F32;
1180     RC = &WebAssembly::F32RegClass;
1181     break;
1182   case MVT::f64:
1183     Opc = WebAssembly::LOAD_F64;
1184     RC = &WebAssembly::F64RegClass;
1185     break;
1186   default:
1187     return false;
1188   }
1189 
1190   materializeLoadStoreOperands(Addr);
1191 
1192   unsigned ResultReg = createResultReg(RC);
1193   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1194                      ResultReg);
1195 
1196   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
1197 
1198   updateValueMap(Load, ResultReg);
1199   return true;
1200 }
1201 
1202 bool WebAssemblyFastISel::selectStore(const Instruction *I) {
1203   const auto *Store = cast<StoreInst>(I);
1204   if (Store->isAtomic())
1205     return false;
1206   if (!Subtarget->hasSIMD128() &&
1207       Store->getValueOperand()->getType()->isVectorTy())
1208     return false;
1209 
1210   Address Addr;
1211   if (!computeAddress(Store->getPointerOperand(), Addr))
1212     return false;
1213 
1214   unsigned Opc;
1215   bool VTIsi1 = false;
1216   switch (getSimpleType(Store->getValueOperand()->getType())) {
1217   case MVT::i1:
1218     VTIsi1 = true;
1219     LLVM_FALLTHROUGH;
1220   case MVT::i8:
1221     Opc = WebAssembly::STORE8_I32;
1222     break;
1223   case MVT::i16:
1224     Opc = WebAssembly::STORE16_I32;
1225     break;
1226   case MVT::i32:
1227     Opc = WebAssembly::STORE_I32;
1228     break;
1229   case MVT::i64:
1230     Opc = WebAssembly::STORE_I64;
1231     break;
1232   case MVT::f32:
1233     Opc = WebAssembly::STORE_F32;
1234     break;
1235   case MVT::f64:
1236     Opc = WebAssembly::STORE_F64;
1237     break;
1238   default:
1239     return false;
1240   }
1241 
1242   materializeLoadStoreOperands(Addr);
1243 
1244   unsigned ValueReg = getRegForValue(Store->getValueOperand());
1245   if (ValueReg == 0)
1246     return false;
1247   if (VTIsi1)
1248     ValueReg = maskI1Value(ValueReg, Store->getValueOperand());
1249 
1250   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1251 
1252   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Store));
1253 
1254   MIB.addReg(ValueReg);
1255   return true;
1256 }
1257 
1258 bool WebAssemblyFastISel::selectBr(const Instruction *I) {
1259   const auto *Br = cast<BranchInst>(I);
1260   if (Br->isUnconditional()) {
1261     MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
1262     fastEmitBranch(MSucc, Br->getDebugLoc());
1263     return true;
1264   }
1265 
1266   MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
1267   MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
1268 
1269   bool Not;
1270   unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
1271   if (CondReg == 0)
1272     return false;
1273 
1274   unsigned Opc = WebAssembly::BR_IF;
1275   if (Not)
1276     Opc = WebAssembly::BR_UNLESS;
1277 
1278   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1279       .addMBB(TBB)
1280       .addReg(CondReg);
1281 
1282   finishCondBranch(Br->getParent(), TBB, FBB);
1283   return true;
1284 }
1285 
1286 bool WebAssemblyFastISel::selectRet(const Instruction *I) {
1287   if (!FuncInfo.CanLowerReturn)
1288     return false;
1289 
1290   const auto *Ret = cast<ReturnInst>(I);
1291 
1292   if (Ret->getNumOperands() == 0) {
1293     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1294             TII.get(WebAssembly::RETURN_VOID));
1295     return true;
1296   }
1297 
1298   Value *RV = Ret->getOperand(0);
1299   if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
1300     return false;
1301 
1302   unsigned Opc;
1303   switch (getSimpleType(RV->getType())) {
1304   case MVT::i1:
1305   case MVT::i8:
1306   case MVT::i16:
1307   case MVT::i32:
1308     Opc = WebAssembly::RETURN_I32;
1309     break;
1310   case MVT::i64:
1311     Opc = WebAssembly::RETURN_I64;
1312     break;
1313   case MVT::f32:
1314     Opc = WebAssembly::RETURN_F32;
1315     break;
1316   case MVT::f64:
1317     Opc = WebAssembly::RETURN_F64;
1318     break;
1319   case MVT::v16i8:
1320     Opc = WebAssembly::RETURN_v16i8;
1321     break;
1322   case MVT::v8i16:
1323     Opc = WebAssembly::RETURN_v8i16;
1324     break;
1325   case MVT::v4i32:
1326     Opc = WebAssembly::RETURN_v4i32;
1327     break;
1328   case MVT::v2i64:
1329     Opc = WebAssembly::RETURN_v2i64;
1330     break;
1331   case MVT::v4f32:
1332     Opc = WebAssembly::RETURN_v4f32;
1333     break;
1334   case MVT::v2f64:
1335     Opc = WebAssembly::RETURN_v2f64;
1336     break;
1337   case MVT::ExceptRef:
1338     Opc = WebAssembly::RETURN_EXCEPT_REF;
1339     break;
1340   default:
1341     return false;
1342   }
1343 
1344   unsigned Reg;
1345   if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
1346     Reg = getRegForSignedValue(RV);
1347   else if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::ZExt))
1348     Reg = getRegForUnsignedValue(RV);
1349   else
1350     Reg = getRegForValue(RV);
1351 
1352   if (Reg == 0)
1353     return false;
1354 
1355   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)).addReg(Reg);
1356   return true;
1357 }
1358 
1359 bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
1360   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1361           TII.get(WebAssembly::UNREACHABLE));
1362   return true;
1363 }
1364 
1365 bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
1366   switch (I->getOpcode()) {
1367   case Instruction::Call:
1368     if (selectCall(I))
1369       return true;
1370     break;
1371   case Instruction::Select:
1372     return selectSelect(I);
1373   case Instruction::Trunc:
1374     return selectTrunc(I);
1375   case Instruction::ZExt:
1376     return selectZExt(I);
1377   case Instruction::SExt:
1378     return selectSExt(I);
1379   case Instruction::ICmp:
1380     return selectICmp(I);
1381   case Instruction::FCmp:
1382     return selectFCmp(I);
1383   case Instruction::BitCast:
1384     return selectBitCast(I);
1385   case Instruction::Load:
1386     return selectLoad(I);
1387   case Instruction::Store:
1388     return selectStore(I);
1389   case Instruction::Br:
1390     return selectBr(I);
1391   case Instruction::Ret:
1392     return selectRet(I);
1393   case Instruction::Unreachable:
1394     return selectUnreachable(I);
1395   default:
1396     break;
1397   }
1398 
1399   // Fall back to target-independent instruction selection.
1400   return selectOperator(I, I->getOpcode());
1401 }
1402 
1403 FastISel *WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
1404                                       const TargetLibraryInfo *LibInfo) {
1405   return new WebAssemblyFastISel(FuncInfo, LibInfo);
1406 }
1407