1 //===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific support for the FastISel
11 /// class. Some of the target-specific code is generated by tablegen in the file
12 /// WebAssemblyGenFastISel.inc, which is #included here.
13 ///
14 /// TODO: kill flags
15 ///
16 //===----------------------------------------------------------------------===//
17 
18 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
19 #include "WebAssembly.h"
20 #include "WebAssemblyMachineFunctionInfo.h"
21 #include "WebAssemblySubtarget.h"
22 #include "WebAssemblyTargetMachine.h"
23 #include "WebAssemblyUtilities.h"
24 #include "llvm/Analysis/BranchProbabilityInfo.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/GetElementPtrTypeIterator.h"
36 #include "llvm/IR/GlobalAlias.h"
37 #include "llvm/IR/GlobalVariable.h"
38 #include "llvm/IR/Instructions.h"
39 #include "llvm/IR/IntrinsicInst.h"
40 #include "llvm/IR/Operator.h"
41 #include "llvm/IR/PatternMatch.h"
42 
43 using namespace llvm;
44 using namespace PatternMatch;
45 
46 #define DEBUG_TYPE "wasm-fastisel"
47 
48 namespace {
49 
50 class WebAssemblyFastISel final : public FastISel {
51   // All possible address modes.
52   class Address {
53   public:
54     using BaseKind = enum { RegBase, FrameIndexBase };
55 
56   private:
57     BaseKind Kind = RegBase;
58     union {
59       unsigned Reg;
60       int FI;
61     } Base;
62 
63     // Whether the base has been determined yet
64     bool IsBaseSet = false;
65 
66     int64_t Offset = 0;
67 
68     const GlobalValue *GV = nullptr;
69 
70   public:
71     // Innocuous defaults for our address.
72     Address() { Base.Reg = 0; }
73     void setKind(BaseKind K) {
74       assert(!isSet() && "Can't change kind with non-zero base");
75       Kind = K;
76     }
77     BaseKind getKind() const { return Kind; }
78     bool isRegBase() const { return Kind == RegBase; }
79     bool isFIBase() const { return Kind == FrameIndexBase; }
80     void setReg(unsigned Reg) {
81       assert(isRegBase() && "Invalid base register access!");
82       assert(!IsBaseSet && "Base cannot be reset");
83       Base.Reg = Reg;
84       IsBaseSet = true;
85     }
86     unsigned getReg() const {
87       assert(isRegBase() && "Invalid base register access!");
88       return Base.Reg;
89     }
90     void setFI(unsigned FI) {
91       assert(isFIBase() && "Invalid base frame index access!");
92       assert(!IsBaseSet && "Base cannot be reset");
93       Base.FI = FI;
94       IsBaseSet = true;
95     }
96     unsigned getFI() const {
97       assert(isFIBase() && "Invalid base frame index access!");
98       return Base.FI;
99     }
100 
101     void setOffset(int64_t NewOffset) {
102       assert(NewOffset >= 0 && "Offsets must be non-negative");
103       Offset = NewOffset;
104     }
105     int64_t getOffset() const { return Offset; }
106     void setGlobalValue(const GlobalValue *G) { GV = G; }
107     const GlobalValue *getGlobalValue() const { return GV; }
108     bool isSet() const { return IsBaseSet; }
109   };
110 
111   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
112   /// right decision when generating code for different targets.
113   const WebAssemblySubtarget *Subtarget;
114   LLVMContext *Context;
115 
116 private:
117   // Utility helper routines
118   MVT::SimpleValueType getSimpleType(Type *Ty) {
119     EVT VT = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true);
120     return VT.isSimple() ? VT.getSimpleVT().SimpleTy
121                          : MVT::INVALID_SIMPLE_VALUE_TYPE;
122   }
123   MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
124     switch (VT) {
125     case MVT::i1:
126     case MVT::i8:
127     case MVT::i16:
128       return MVT::i32;
129     case MVT::i32:
130     case MVT::i64:
131     case MVT::f32:
132     case MVT::f64:
133     case MVT::funcref:
134     case MVT::externref:
135       return VT;
136     case MVT::f16:
137       return MVT::f32;
138     case MVT::v16i8:
139     case MVT::v8i16:
140     case MVT::v4i32:
141     case MVT::v4f32:
142       if (Subtarget->hasSIMD128())
143         return VT;
144       break;
145     case MVT::v2i64:
146     case MVT::v2f64:
147       if (Subtarget->hasUnimplementedSIMD128())
148         return VT;
149       break;
150     default:
151       break;
152     }
153     return MVT::INVALID_SIMPLE_VALUE_TYPE;
154   }
155   bool computeAddress(const Value *Obj, Address &Addr);
156   void materializeLoadStoreOperands(Address &Addr);
157   void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
158                             MachineMemOperand *MMO);
159   unsigned maskI1Value(unsigned Reg, const Value *V);
160   unsigned getRegForI1Value(const Value *V, bool &Not);
161   unsigned zeroExtendToI32(unsigned Reg, const Value *V,
162                            MVT::SimpleValueType From);
163   unsigned signExtendToI32(unsigned Reg, const Value *V,
164                            MVT::SimpleValueType From);
165   unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
166                       MVT::SimpleValueType To);
167   unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
168                       MVT::SimpleValueType To);
169   unsigned getRegForUnsignedValue(const Value *V);
170   unsigned getRegForSignedValue(const Value *V);
171   unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
172   unsigned notValue(unsigned Reg);
173   unsigned copyValue(unsigned Reg);
174 
175   // Backend specific FastISel code.
176   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
177   unsigned fastMaterializeConstant(const Constant *C) override;
178   bool fastLowerArguments() override;
179 
180   // Selection routines.
181   bool selectCall(const Instruction *I);
182   bool selectSelect(const Instruction *I);
183   bool selectTrunc(const Instruction *I);
184   bool selectZExt(const Instruction *I);
185   bool selectSExt(const Instruction *I);
186   bool selectICmp(const Instruction *I);
187   bool selectFCmp(const Instruction *I);
188   bool selectBitCast(const Instruction *I);
189   bool selectLoad(const Instruction *I);
190   bool selectStore(const Instruction *I);
191   bool selectBr(const Instruction *I);
192   bool selectRet(const Instruction *I);
193   bool selectUnreachable(const Instruction *I);
194 
195 public:
196   // Backend specific FastISel code.
197   WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
198                       const TargetLibraryInfo *LibInfo)
199       : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
200     Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
201     Context = &FuncInfo.Fn->getContext();
202   }
203 
204   bool fastSelectInstruction(const Instruction *I) override;
205 
206 #include "WebAssemblyGenFastISel.inc"
207 };
208 
209 } // end anonymous namespace
210 
211 bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
212   const User *U = nullptr;
213   unsigned Opcode = Instruction::UserOp1;
214   if (const auto *I = dyn_cast<Instruction>(Obj)) {
215     // Don't walk into other basic blocks unless the object is an alloca from
216     // another block, otherwise it may not have a virtual register assigned.
217     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
218         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
219       Opcode = I->getOpcode();
220       U = I;
221     }
222   } else if (const auto *C = dyn_cast<ConstantExpr>(Obj)) {
223     Opcode = C->getOpcode();
224     U = C;
225   }
226 
227   if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
228     if (Ty->getAddressSpace() > 255)
229       // Fast instruction selection doesn't support the special
230       // address spaces.
231       return false;
232 
233   if (const auto *GV = dyn_cast<GlobalValue>(Obj)) {
234     if (TLI.isPositionIndependent())
235       return false;
236     if (Addr.getGlobalValue())
237       return false;
238     if (GV->isThreadLocal())
239       return false;
240     Addr.setGlobalValue(GV);
241     return true;
242   }
243 
244   switch (Opcode) {
245   default:
246     break;
247   case Instruction::BitCast: {
248     // Look through bitcasts.
249     return computeAddress(U->getOperand(0), Addr);
250   }
251   case Instruction::IntToPtr: {
252     // Look past no-op inttoptrs.
253     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
254         TLI.getPointerTy(DL))
255       return computeAddress(U->getOperand(0), Addr);
256     break;
257   }
258   case Instruction::PtrToInt: {
259     // Look past no-op ptrtoints.
260     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
261       return computeAddress(U->getOperand(0), Addr);
262     break;
263   }
264   case Instruction::GetElementPtr: {
265     Address SavedAddr = Addr;
266     uint64_t TmpOffset = Addr.getOffset();
267     // Non-inbounds geps can wrap; wasm's offsets can't.
268     if (!cast<GEPOperator>(U)->isInBounds())
269       goto unsupported_gep;
270     // Iterate through the GEP folding the constants into offsets where
271     // we can.
272     for (gep_type_iterator GTI = gep_type_begin(U), E = gep_type_end(U);
273          GTI != E; ++GTI) {
274       const Value *Op = GTI.getOperand();
275       if (StructType *STy = GTI.getStructTypeOrNull()) {
276         const StructLayout *SL = DL.getStructLayout(STy);
277         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
278         TmpOffset += SL->getElementOffset(Idx);
279       } else {
280         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
281         for (;;) {
282           if (const auto *CI = dyn_cast<ConstantInt>(Op)) {
283             // Constant-offset addressing.
284             TmpOffset += CI->getSExtValue() * S;
285             break;
286           }
287           if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
288             // An unscaled add of a register. Set it as the new base.
289             unsigned Reg = getRegForValue(Op);
290             if (Reg == 0)
291               return false;
292             Addr.setReg(Reg);
293             break;
294           }
295           if (canFoldAddIntoGEP(U, Op)) {
296             // A compatible add with a constant operand. Fold the constant.
297             auto *CI = cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
298             TmpOffset += CI->getSExtValue() * S;
299             // Iterate on the other operand.
300             Op = cast<AddOperator>(Op)->getOperand(0);
301             continue;
302           }
303           // Unsupported
304           goto unsupported_gep;
305         }
306       }
307     }
308     // Don't fold in negative offsets.
309     if (int64_t(TmpOffset) >= 0) {
310       // Try to grab the base operand now.
311       Addr.setOffset(TmpOffset);
312       if (computeAddress(U->getOperand(0), Addr))
313         return true;
314     }
315     // We failed, restore everything and try the other options.
316     Addr = SavedAddr;
317   unsupported_gep:
318     break;
319   }
320   case Instruction::Alloca: {
321     const auto *AI = cast<AllocaInst>(Obj);
322     DenseMap<const AllocaInst *, int>::iterator SI =
323         FuncInfo.StaticAllocaMap.find(AI);
324     if (SI != FuncInfo.StaticAllocaMap.end()) {
325       if (Addr.isSet()) {
326         return false;
327       }
328       Addr.setKind(Address::FrameIndexBase);
329       Addr.setFI(SI->second);
330       return true;
331     }
332     break;
333   }
334   case Instruction::Add: {
335     // Adds of constants are common and easy enough.
336     const Value *LHS = U->getOperand(0);
337     const Value *RHS = U->getOperand(1);
338 
339     if (isa<ConstantInt>(LHS))
340       std::swap(LHS, RHS);
341 
342     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
343       uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
344       if (int64_t(TmpOffset) >= 0) {
345         Addr.setOffset(TmpOffset);
346         return computeAddress(LHS, Addr);
347       }
348     }
349 
350     Address Backup = Addr;
351     if (computeAddress(LHS, Addr) && computeAddress(RHS, Addr))
352       return true;
353     Addr = Backup;
354 
355     break;
356   }
357   case Instruction::Sub: {
358     // Subs of constants are common and easy enough.
359     const Value *LHS = U->getOperand(0);
360     const Value *RHS = U->getOperand(1);
361 
362     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
363       int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
364       if (TmpOffset >= 0) {
365         Addr.setOffset(TmpOffset);
366         return computeAddress(LHS, Addr);
367       }
368     }
369     break;
370   }
371   }
372   if (Addr.isSet()) {
373     return false;
374   }
375   unsigned Reg = getRegForValue(Obj);
376   if (Reg == 0)
377     return false;
378   Addr.setReg(Reg);
379   return Addr.getReg() != 0;
380 }
381 
382 void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
383   if (Addr.isRegBase()) {
384     unsigned Reg = Addr.getReg();
385     if (Reg == 0) {
386       Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
387                                                    : &WebAssembly::I32RegClass);
388       unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
389                                             : WebAssembly::CONST_I32;
390       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
391           .addImm(0);
392       Addr.setReg(Reg);
393     }
394   }
395 }
396 
397 void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
398                                                const MachineInstrBuilder &MIB,
399                                                MachineMemOperand *MMO) {
400   // Set the alignment operand (this is rewritten in SetP2AlignOperands).
401   // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
402   MIB.addImm(0);
403 
404   if (const GlobalValue *GV = Addr.getGlobalValue())
405     MIB.addGlobalAddress(GV, Addr.getOffset());
406   else
407     MIB.addImm(Addr.getOffset());
408 
409   if (Addr.isRegBase())
410     MIB.addReg(Addr.getReg());
411   else
412     MIB.addFrameIndex(Addr.getFI());
413 
414   MIB.addMemOperand(MMO);
415 }
416 
417 unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
418   return zeroExtendToI32(Reg, V, MVT::i1);
419 }
420 
421 unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V, bool &Not) {
422   if (const auto *ICmp = dyn_cast<ICmpInst>(V))
423     if (const ConstantInt *C = dyn_cast<ConstantInt>(ICmp->getOperand(1)))
424       if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(32)) {
425         Not = ICmp->isTrueWhenEqual();
426         return getRegForValue(ICmp->getOperand(0));
427       }
428 
429   Value *NotV;
430   if (match(V, m_Not(m_Value(NotV))) && V->getType()->isIntegerTy(32)) {
431     Not = true;
432     return getRegForValue(NotV);
433   }
434 
435   Not = false;
436   unsigned Reg = getRegForValue(V);
437   if (Reg == 0)
438     return 0;
439   return maskI1Value(Reg, V);
440 }
441 
442 unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
443                                               MVT::SimpleValueType From) {
444   if (Reg == 0)
445     return 0;
446 
447   switch (From) {
448   case MVT::i1:
449     // If the value is naturally an i1, we don't need to mask it. We only know
450     // if a value is naturally an i1 if it is definitely lowered by FastISel,
451     // not a DAG ISel fallback.
452     if (V != nullptr && isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr())
453       return copyValue(Reg);
454     break;
455   case MVT::i8:
456   case MVT::i16:
457     break;
458   case MVT::i32:
459     return copyValue(Reg);
460   default:
461     return 0;
462   }
463 
464   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
465   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
466           TII.get(WebAssembly::CONST_I32), Imm)
467       .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));
468 
469   unsigned Result = createResultReg(&WebAssembly::I32RegClass);
470   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
471           TII.get(WebAssembly::AND_I32), Result)
472       .addReg(Reg)
473       .addReg(Imm);
474 
475   return Result;
476 }
477 
478 unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
479                                               MVT::SimpleValueType From) {
480   if (Reg == 0)
481     return 0;
482 
483   switch (From) {
484   case MVT::i1:
485   case MVT::i8:
486   case MVT::i16:
487     break;
488   case MVT::i32:
489     return copyValue(Reg);
490   default:
491     return 0;
492   }
493 
494   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
495   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
496           TII.get(WebAssembly::CONST_I32), Imm)
497       .addImm(32 - MVT(From).getSizeInBits());
498 
499   unsigned Left = createResultReg(&WebAssembly::I32RegClass);
500   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
501           TII.get(WebAssembly::SHL_I32), Left)
502       .addReg(Reg)
503       .addReg(Imm);
504 
505   unsigned Right = createResultReg(&WebAssembly::I32RegClass);
506   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
507           TII.get(WebAssembly::SHR_S_I32), Right)
508       .addReg(Left)
509       .addReg(Imm);
510 
511   return Right;
512 }
513 
514 unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
515                                          MVT::SimpleValueType From,
516                                          MVT::SimpleValueType To) {
517   if (To == MVT::i64) {
518     if (From == MVT::i64)
519       return copyValue(Reg);
520 
521     Reg = zeroExtendToI32(Reg, V, From);
522 
523     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
524     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
525             TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
526         .addReg(Reg);
527     return Result;
528   }
529 
530   if (To == MVT::i32)
531     return zeroExtendToI32(Reg, V, From);
532 
533   return 0;
534 }
535 
536 unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
537                                          MVT::SimpleValueType From,
538                                          MVT::SimpleValueType To) {
539   if (To == MVT::i64) {
540     if (From == MVT::i64)
541       return copyValue(Reg);
542 
543     Reg = signExtendToI32(Reg, V, From);
544 
545     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
546     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
547             TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
548         .addReg(Reg);
549     return Result;
550   }
551 
552   if (To == MVT::i32)
553     return signExtendToI32(Reg, V, From);
554 
555   return 0;
556 }
557 
558 unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
559   MVT::SimpleValueType From = getSimpleType(V->getType());
560   MVT::SimpleValueType To = getLegalType(From);
561   unsigned VReg = getRegForValue(V);
562   if (VReg == 0)
563     return 0;
564   return zeroExtend(VReg, V, From, To);
565 }
566 
567 unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
568   MVT::SimpleValueType From = getSimpleType(V->getType());
569   MVT::SimpleValueType To = getLegalType(From);
570   unsigned VReg = getRegForValue(V);
571   if (VReg == 0)
572     return 0;
573   return signExtend(VReg, V, From, To);
574 }
575 
576 unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
577                                                      bool IsSigned) {
578   return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
579 }
580 
581 unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
582   assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
583 
584   unsigned NotReg = createResultReg(&WebAssembly::I32RegClass);
585   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
586           TII.get(WebAssembly::EQZ_I32), NotReg)
587       .addReg(Reg);
588   return NotReg;
589 }
590 
591 unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
592   unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
593   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
594           ResultReg)
595       .addReg(Reg);
596   return ResultReg;
597 }
598 
599 unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
600   DenseMap<const AllocaInst *, int>::iterator SI =
601       FuncInfo.StaticAllocaMap.find(AI);
602 
603   if (SI != FuncInfo.StaticAllocaMap.end()) {
604     unsigned ResultReg =
605         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
606                                                : &WebAssembly::I32RegClass);
607     unsigned Opc =
608         Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
609     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
610         .addFrameIndex(SI->second);
611     return ResultReg;
612   }
613 
614   return 0;
615 }
616 
617 unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
618   if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
619     if (TLI.isPositionIndependent())
620       return 0;
621     if (GV->isThreadLocal())
622       return 0;
623     unsigned ResultReg =
624         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
625                                                : &WebAssembly::I32RegClass);
626     unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
627                                           : WebAssembly::CONST_I32;
628     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
629         .addGlobalAddress(GV);
630     return ResultReg;
631   }
632 
633   // Let target-independent code handle it.
634   return 0;
635 }
636 
637 bool WebAssemblyFastISel::fastLowerArguments() {
638   if (!FuncInfo.CanLowerReturn)
639     return false;
640 
641   const Function *F = FuncInfo.Fn;
642   if (F->isVarArg())
643     return false;
644 
645   if (FuncInfo.Fn->getCallingConv() == CallingConv::Swift)
646     return false;
647 
648   unsigned I = 0;
649   for (auto const &Arg : F->args()) {
650     const AttributeList &Attrs = F->getAttributes();
651     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
652         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
653         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
654         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
655         Attrs.hasParamAttribute(I, Attribute::Nest))
656       return false;
657 
658     Type *ArgTy = Arg.getType();
659     if (ArgTy->isStructTy() || ArgTy->isArrayTy())
660       return false;
661     if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
662       return false;
663 
664     unsigned Opc;
665     const TargetRegisterClass *RC;
666     switch (getSimpleType(ArgTy)) {
667     case MVT::i1:
668     case MVT::i8:
669     case MVT::i16:
670     case MVT::i32:
671       Opc = WebAssembly::ARGUMENT_i32;
672       RC = &WebAssembly::I32RegClass;
673       break;
674     case MVT::i64:
675       Opc = WebAssembly::ARGUMENT_i64;
676       RC = &WebAssembly::I64RegClass;
677       break;
678     case MVT::f32:
679       Opc = WebAssembly::ARGUMENT_f32;
680       RC = &WebAssembly::F32RegClass;
681       break;
682     case MVT::f64:
683       Opc = WebAssembly::ARGUMENT_f64;
684       RC = &WebAssembly::F64RegClass;
685       break;
686     case MVT::v16i8:
687       Opc = WebAssembly::ARGUMENT_v16i8;
688       RC = &WebAssembly::V128RegClass;
689       break;
690     case MVT::v8i16:
691       Opc = WebAssembly::ARGUMENT_v8i16;
692       RC = &WebAssembly::V128RegClass;
693       break;
694     case MVT::v4i32:
695       Opc = WebAssembly::ARGUMENT_v4i32;
696       RC = &WebAssembly::V128RegClass;
697       break;
698     case MVT::v2i64:
699       Opc = WebAssembly::ARGUMENT_v2i64;
700       RC = &WebAssembly::V128RegClass;
701       break;
702     case MVT::v4f32:
703       Opc = WebAssembly::ARGUMENT_v4f32;
704       RC = &WebAssembly::V128RegClass;
705       break;
706     case MVT::v2f64:
707       Opc = WebAssembly::ARGUMENT_v2f64;
708       RC = &WebAssembly::V128RegClass;
709       break;
710     case MVT::funcref:
711       Opc = WebAssembly::ARGUMENT_funcref;
712       RC = &WebAssembly::FUNCREFRegClass;
713       break;
714     case MVT::externref:
715       Opc = WebAssembly::ARGUMENT_externref;
716       RC = &WebAssembly::EXTERNREFRegClass;
717       break;
718     default:
719       return false;
720     }
721     unsigned ResultReg = createResultReg(RC);
722     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
723         .addImm(I);
724     updateValueMap(&Arg, ResultReg);
725 
726     ++I;
727   }
728 
729   MRI.addLiveIn(WebAssembly::ARGUMENTS);
730 
731   auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
732   for (auto const &Arg : F->args()) {
733     MVT::SimpleValueType ArgTy = getLegalType(getSimpleType(Arg.getType()));
734     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
735       MFI->clearParamsAndResults();
736       return false;
737     }
738     MFI->addParam(ArgTy);
739   }
740 
741   if (!F->getReturnType()->isVoidTy()) {
742     MVT::SimpleValueType RetTy =
743         getLegalType(getSimpleType(F->getReturnType()));
744     if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
745       MFI->clearParamsAndResults();
746       return false;
747     }
748     MFI->addResult(RetTy);
749   }
750 
751   return true;
752 }
753 
754 bool WebAssemblyFastISel::selectCall(const Instruction *I) {
755   const auto *Call = cast<CallInst>(I);
756 
757   // TODO: Support tail calls in FastISel
758   if (Call->isMustTailCall() || Call->isInlineAsm() ||
759       Call->getFunctionType()->isVarArg())
760     return false;
761 
762   Function *Func = Call->getCalledFunction();
763   if (Func && Func->isIntrinsic())
764     return false;
765 
766   if (Call->getCallingConv() == CallingConv::Swift)
767     return false;
768 
769   bool IsDirect = Func != nullptr;
770   if (!IsDirect && isa<ConstantExpr>(Call->getCalledOperand()))
771     return false;
772 
773   FunctionType *FuncTy = Call->getFunctionType();
774   unsigned Opc = IsDirect ? WebAssembly::CALL : WebAssembly::CALL_INDIRECT;
775   bool IsVoid = FuncTy->getReturnType()->isVoidTy();
776   unsigned ResultReg;
777   if (!IsVoid) {
778     if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
779       return false;
780 
781     MVT::SimpleValueType RetTy = getSimpleType(Call->getType());
782     switch (RetTy) {
783     case MVT::i1:
784     case MVT::i8:
785     case MVT::i16:
786     case MVT::i32:
787       ResultReg = createResultReg(&WebAssembly::I32RegClass);
788       break;
789     case MVT::i64:
790       ResultReg = createResultReg(&WebAssembly::I64RegClass);
791       break;
792     case MVT::f32:
793       ResultReg = createResultReg(&WebAssembly::F32RegClass);
794       break;
795     case MVT::f64:
796       ResultReg = createResultReg(&WebAssembly::F64RegClass);
797       break;
798     case MVT::v16i8:
799       ResultReg = createResultReg(&WebAssembly::V128RegClass);
800       break;
801     case MVT::v8i16:
802       ResultReg = createResultReg(&WebAssembly::V128RegClass);
803       break;
804     case MVT::v4i32:
805       ResultReg = createResultReg(&WebAssembly::V128RegClass);
806       break;
807     case MVT::v2i64:
808       ResultReg = createResultReg(&WebAssembly::V128RegClass);
809       break;
810     case MVT::v4f32:
811       ResultReg = createResultReg(&WebAssembly::V128RegClass);
812       break;
813     case MVT::v2f64:
814       ResultReg = createResultReg(&WebAssembly::V128RegClass);
815       break;
816     case MVT::funcref:
817       ResultReg = createResultReg(&WebAssembly::FUNCREFRegClass);
818       break;
819     case MVT::externref:
820       ResultReg = createResultReg(&WebAssembly::EXTERNREFRegClass);
821       break;
822     default:
823       return false;
824     }
825   }
826 
827   SmallVector<unsigned, 8> Args;
828   for (unsigned I = 0, E = Call->getNumArgOperands(); I < E; ++I) {
829     Value *V = Call->getArgOperand(I);
830     MVT::SimpleValueType ArgTy = getSimpleType(V->getType());
831     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
832       return false;
833 
834     const AttributeList &Attrs = Call->getAttributes();
835     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
836         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
837         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
838         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
839         Attrs.hasParamAttribute(I, Attribute::Nest))
840       return false;
841 
842     unsigned Reg;
843 
844     if (Attrs.hasParamAttribute(I, Attribute::SExt))
845       Reg = getRegForSignedValue(V);
846     else if (Attrs.hasParamAttribute(I, Attribute::ZExt))
847       Reg = getRegForUnsignedValue(V);
848     else
849       Reg = getRegForValue(V);
850 
851     if (Reg == 0)
852       return false;
853 
854     Args.push_back(Reg);
855   }
856 
857   unsigned CalleeReg = 0;
858   if (!IsDirect) {
859     CalleeReg = getRegForValue(Call->getCalledOperand());
860     if (!CalleeReg)
861       return false;
862   }
863 
864   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
865 
866   if (!IsVoid)
867     MIB.addReg(ResultReg, RegState::Define);
868 
869   if (IsDirect) {
870     MIB.addGlobalAddress(Func);
871   } else {
872     // Placehoder for the type index.
873     MIB.addImm(0);
874     // The table into which this call_indirect indexes.
875     MIB.addSym(WebAssembly::getOrCreateFunctionTableSymbol(
876         MF->getMMI().getContext(), "__indirect_function_table"));
877   }
878 
879   for (unsigned ArgReg : Args)
880     MIB.addReg(ArgReg);
881 
882   if (!IsDirect)
883     MIB.addReg(CalleeReg);
884 
885   if (!IsVoid)
886     updateValueMap(Call, ResultReg);
887   return true;
888 }
889 
890 bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
891   const auto *Select = cast<SelectInst>(I);
892 
893   bool Not;
894   unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
895   if (CondReg == 0)
896     return false;
897 
898   unsigned TrueReg = getRegForValue(Select->getTrueValue());
899   if (TrueReg == 0)
900     return false;
901 
902   unsigned FalseReg = getRegForValue(Select->getFalseValue());
903   if (FalseReg == 0)
904     return false;
905 
906   if (Not)
907     std::swap(TrueReg, FalseReg);
908 
909   unsigned Opc;
910   const TargetRegisterClass *RC;
911   switch (getSimpleType(Select->getType())) {
912   case MVT::i1:
913   case MVT::i8:
914   case MVT::i16:
915   case MVT::i32:
916     Opc = WebAssembly::SELECT_I32;
917     RC = &WebAssembly::I32RegClass;
918     break;
919   case MVT::i64:
920     Opc = WebAssembly::SELECT_I64;
921     RC = &WebAssembly::I64RegClass;
922     break;
923   case MVT::f32:
924     Opc = WebAssembly::SELECT_F32;
925     RC = &WebAssembly::F32RegClass;
926     break;
927   case MVT::f64:
928     Opc = WebAssembly::SELECT_F64;
929     RC = &WebAssembly::F64RegClass;
930     break;
931   case MVT::funcref:
932     Opc = WebAssembly::SELECT_FUNCREF;
933     RC = &WebAssembly::FUNCREFRegClass;
934     break;
935   case MVT::externref:
936     Opc = WebAssembly::SELECT_EXTERNREF;
937     RC = &WebAssembly::EXTERNREFRegClass;
938     break;
939   default:
940     return false;
941   }
942 
943   unsigned ResultReg = createResultReg(RC);
944   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
945       .addReg(TrueReg)
946       .addReg(FalseReg)
947       .addReg(CondReg);
948 
949   updateValueMap(Select, ResultReg);
950   return true;
951 }
952 
953 bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
954   const auto *Trunc = cast<TruncInst>(I);
955 
956   unsigned Reg = getRegForValue(Trunc->getOperand(0));
957   if (Reg == 0)
958     return false;
959 
960   if (Trunc->getOperand(0)->getType()->isIntegerTy(64)) {
961     unsigned Result = createResultReg(&WebAssembly::I32RegClass);
962     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
963             TII.get(WebAssembly::I32_WRAP_I64), Result)
964         .addReg(Reg);
965     Reg = Result;
966   }
967 
968   updateValueMap(Trunc, Reg);
969   return true;
970 }
971 
972 bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
973   const auto *ZExt = cast<ZExtInst>(I);
974 
975   const Value *Op = ZExt->getOperand(0);
976   MVT::SimpleValueType From = getSimpleType(Op->getType());
977   MVT::SimpleValueType To = getLegalType(getSimpleType(ZExt->getType()));
978   unsigned In = getRegForValue(Op);
979   if (In == 0)
980     return false;
981   unsigned Reg = zeroExtend(In, Op, From, To);
982   if (Reg == 0)
983     return false;
984 
985   updateValueMap(ZExt, Reg);
986   return true;
987 }
988 
989 bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
990   const auto *SExt = cast<SExtInst>(I);
991 
992   const Value *Op = SExt->getOperand(0);
993   MVT::SimpleValueType From = getSimpleType(Op->getType());
994   MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType()));
995   unsigned In = getRegForValue(Op);
996   if (In == 0)
997     return false;
998   unsigned Reg = signExtend(In, Op, From, To);
999   if (Reg == 0)
1000     return false;
1001 
1002   updateValueMap(SExt, Reg);
1003   return true;
1004 }
1005 
1006 bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
1007   const auto *ICmp = cast<ICmpInst>(I);
1008 
1009   bool I32 = getSimpleType(ICmp->getOperand(0)->getType()) != MVT::i64;
1010   unsigned Opc;
1011   bool IsSigned = false;
1012   switch (ICmp->getPredicate()) {
1013   case ICmpInst::ICMP_EQ:
1014     Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
1015     break;
1016   case ICmpInst::ICMP_NE:
1017     Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
1018     break;
1019   case ICmpInst::ICMP_UGT:
1020     Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
1021     break;
1022   case ICmpInst::ICMP_UGE:
1023     Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
1024     break;
1025   case ICmpInst::ICMP_ULT:
1026     Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
1027     break;
1028   case ICmpInst::ICMP_ULE:
1029     Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
1030     break;
1031   case ICmpInst::ICMP_SGT:
1032     Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
1033     IsSigned = true;
1034     break;
1035   case ICmpInst::ICMP_SGE:
1036     Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
1037     IsSigned = true;
1038     break;
1039   case ICmpInst::ICMP_SLT:
1040     Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
1041     IsSigned = true;
1042     break;
1043   case ICmpInst::ICMP_SLE:
1044     Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
1045     IsSigned = true;
1046     break;
1047   default:
1048     return false;
1049   }
1050 
1051   unsigned LHS = getRegForPromotedValue(ICmp->getOperand(0), IsSigned);
1052   if (LHS == 0)
1053     return false;
1054 
1055   unsigned RHS = getRegForPromotedValue(ICmp->getOperand(1), IsSigned);
1056   if (RHS == 0)
1057     return false;
1058 
1059   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1060   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1061       .addReg(LHS)
1062       .addReg(RHS);
1063   updateValueMap(ICmp, ResultReg);
1064   return true;
1065 }
1066 
1067 bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
1068   const auto *FCmp = cast<FCmpInst>(I);
1069 
1070   unsigned LHS = getRegForValue(FCmp->getOperand(0));
1071   if (LHS == 0)
1072     return false;
1073 
1074   unsigned RHS = getRegForValue(FCmp->getOperand(1));
1075   if (RHS == 0)
1076     return false;
1077 
1078   bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64;
1079   unsigned Opc;
1080   bool Not = false;
1081   switch (FCmp->getPredicate()) {
1082   case FCmpInst::FCMP_OEQ:
1083     Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
1084     break;
1085   case FCmpInst::FCMP_UNE:
1086     Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
1087     break;
1088   case FCmpInst::FCMP_OGT:
1089     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1090     break;
1091   case FCmpInst::FCMP_OGE:
1092     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1093     break;
1094   case FCmpInst::FCMP_OLT:
1095     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1096     break;
1097   case FCmpInst::FCMP_OLE:
1098     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1099     break;
1100   case FCmpInst::FCMP_UGT:
1101     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1102     Not = true;
1103     break;
1104   case FCmpInst::FCMP_UGE:
1105     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1106     Not = true;
1107     break;
1108   case FCmpInst::FCMP_ULT:
1109     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1110     Not = true;
1111     break;
1112   case FCmpInst::FCMP_ULE:
1113     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1114     Not = true;
1115     break;
1116   default:
1117     return false;
1118   }
1119 
1120   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1121   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1122       .addReg(LHS)
1123       .addReg(RHS);
1124 
1125   if (Not)
1126     ResultReg = notValue(ResultReg);
1127 
1128   updateValueMap(FCmp, ResultReg);
1129   return true;
1130 }
1131 
1132 bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
1133   // Target-independent code can handle this, except it doesn't set the dead
1134   // flag on the ARGUMENTS clobber, so we have to do that manually in order
1135   // to satisfy code that expects this of isBitcast() instructions.
1136   EVT VT = TLI.getValueType(DL, I->getOperand(0)->getType());
1137   EVT RetVT = TLI.getValueType(DL, I->getType());
1138   if (!VT.isSimple() || !RetVT.isSimple())
1139     return false;
1140 
1141   unsigned In = getRegForValue(I->getOperand(0));
1142   if (In == 0)
1143     return false;
1144 
1145   if (VT == RetVT) {
1146     // No-op bitcast.
1147     updateValueMap(I, In);
1148     return true;
1149   }
1150 
1151   Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
1152                                         In, I->getOperand(0)->hasOneUse());
1153   if (!Reg)
1154     return false;
1155   MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
1156   --Iter;
1157   assert(Iter->isBitcast());
1158   Iter->setPhysRegsDeadExcept(ArrayRef<Register>(), TRI);
1159   updateValueMap(I, Reg);
1160   return true;
1161 }
1162 
1163 bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
1164   const auto *Load = cast<LoadInst>(I);
1165   if (Load->isAtomic())
1166     return false;
1167   if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
1168     return false;
1169 
1170   Address Addr;
1171   if (!computeAddress(Load->getPointerOperand(), Addr))
1172     return false;
1173 
1174   // TODO: Fold a following sign-/zero-extend into the load instruction.
1175 
1176   unsigned Opc;
1177   const TargetRegisterClass *RC;
1178   bool A64 = Subtarget->hasAddr64();
1179   switch (getSimpleType(Load->getType())) {
1180   case MVT::i1:
1181   case MVT::i8:
1182     Opc = A64 ? WebAssembly::LOAD8_U_I32_A64 : WebAssembly::LOAD8_U_I32_A32;
1183     RC = &WebAssembly::I32RegClass;
1184     break;
1185   case MVT::i16:
1186     Opc = A64 ? WebAssembly::LOAD16_U_I32_A64 : WebAssembly::LOAD16_U_I32_A32;
1187     RC = &WebAssembly::I32RegClass;
1188     break;
1189   case MVT::i32:
1190     Opc = A64 ? WebAssembly::LOAD_I32_A64 : WebAssembly::LOAD_I32_A32;
1191     RC = &WebAssembly::I32RegClass;
1192     break;
1193   case MVT::i64:
1194     Opc = A64 ? WebAssembly::LOAD_I64_A64 : WebAssembly::LOAD_I64_A32;
1195     RC = &WebAssembly::I64RegClass;
1196     break;
1197   case MVT::f32:
1198     Opc = A64 ? WebAssembly::LOAD_F32_A64 : WebAssembly::LOAD_F32_A32;
1199     RC = &WebAssembly::F32RegClass;
1200     break;
1201   case MVT::f64:
1202     Opc = A64 ? WebAssembly::LOAD_F64_A64 : WebAssembly::LOAD_F64_A32;
1203     RC = &WebAssembly::F64RegClass;
1204     break;
1205   default:
1206     return false;
1207   }
1208 
1209   materializeLoadStoreOperands(Addr);
1210 
1211   unsigned ResultReg = createResultReg(RC);
1212   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1213                      ResultReg);
1214 
1215   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
1216 
1217   updateValueMap(Load, ResultReg);
1218   return true;
1219 }
1220 
1221 bool WebAssemblyFastISel::selectStore(const Instruction *I) {
1222   const auto *Store = cast<StoreInst>(I);
1223   if (Store->isAtomic())
1224     return false;
1225   if (!Subtarget->hasSIMD128() &&
1226       Store->getValueOperand()->getType()->isVectorTy())
1227     return false;
1228 
1229   Address Addr;
1230   if (!computeAddress(Store->getPointerOperand(), Addr))
1231     return false;
1232 
1233   unsigned Opc;
1234   bool VTIsi1 = false;
1235   bool A64 = Subtarget->hasAddr64();
1236   switch (getSimpleType(Store->getValueOperand()->getType())) {
1237   case MVT::i1:
1238     VTIsi1 = true;
1239     LLVM_FALLTHROUGH;
1240   case MVT::i8:
1241     Opc = A64 ? WebAssembly::STORE8_I32_A64 : WebAssembly::STORE8_I32_A32;
1242     break;
1243   case MVT::i16:
1244     Opc = A64 ? WebAssembly::STORE16_I32_A64 : WebAssembly::STORE16_I32_A32;
1245     break;
1246   case MVT::i32:
1247     Opc = A64 ? WebAssembly::STORE_I32_A64 : WebAssembly::STORE_I32_A32;
1248     break;
1249   case MVT::i64:
1250     Opc = A64 ? WebAssembly::STORE_I64_A64 : WebAssembly::STORE_I64_A32;
1251     break;
1252   case MVT::f32:
1253     Opc = A64 ? WebAssembly::STORE_F32_A64 : WebAssembly::STORE_F32_A32;
1254     break;
1255   case MVT::f64:
1256     Opc = A64 ? WebAssembly::STORE_F64_A64 : WebAssembly::STORE_F64_A32;
1257     break;
1258   default:
1259     return false;
1260   }
1261 
1262   materializeLoadStoreOperands(Addr);
1263 
1264   unsigned ValueReg = getRegForValue(Store->getValueOperand());
1265   if (ValueReg == 0)
1266     return false;
1267   if (VTIsi1)
1268     ValueReg = maskI1Value(ValueReg, Store->getValueOperand());
1269 
1270   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1271 
1272   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Store));
1273 
1274   MIB.addReg(ValueReg);
1275   return true;
1276 }
1277 
1278 bool WebAssemblyFastISel::selectBr(const Instruction *I) {
1279   const auto *Br = cast<BranchInst>(I);
1280   if (Br->isUnconditional()) {
1281     MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
1282     fastEmitBranch(MSucc, Br->getDebugLoc());
1283     return true;
1284   }
1285 
1286   MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
1287   MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
1288 
1289   bool Not;
1290   unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
1291   if (CondReg == 0)
1292     return false;
1293 
1294   unsigned Opc = WebAssembly::BR_IF;
1295   if (Not)
1296     Opc = WebAssembly::BR_UNLESS;
1297 
1298   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1299       .addMBB(TBB)
1300       .addReg(CondReg);
1301 
1302   finishCondBranch(Br->getParent(), TBB, FBB);
1303   return true;
1304 }
1305 
1306 bool WebAssemblyFastISel::selectRet(const Instruction *I) {
1307   if (!FuncInfo.CanLowerReturn)
1308     return false;
1309 
1310   const auto *Ret = cast<ReturnInst>(I);
1311 
1312   if (Ret->getNumOperands() == 0) {
1313     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1314             TII.get(WebAssembly::RETURN));
1315     return true;
1316   }
1317 
1318   // TODO: support multiple return in FastISel
1319   if (Ret->getNumOperands() > 1)
1320     return false;
1321 
1322   Value *RV = Ret->getOperand(0);
1323   if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
1324     return false;
1325 
1326   switch (getSimpleType(RV->getType())) {
1327   case MVT::i1:
1328   case MVT::i8:
1329   case MVT::i16:
1330   case MVT::i32:
1331   case MVT::i64:
1332   case MVT::f32:
1333   case MVT::f64:
1334   case MVT::v16i8:
1335   case MVT::v8i16:
1336   case MVT::v4i32:
1337   case MVT::v2i64:
1338   case MVT::v4f32:
1339   case MVT::v2f64:
1340   case MVT::funcref:
1341   case MVT::externref:
1342     break;
1343   default:
1344     return false;
1345   }
1346 
1347   unsigned Reg;
1348   if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
1349     Reg = getRegForSignedValue(RV);
1350   else if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::ZExt))
1351     Reg = getRegForUnsignedValue(RV);
1352   else
1353     Reg = getRegForValue(RV);
1354 
1355   if (Reg == 0)
1356     return false;
1357 
1358   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1359           TII.get(WebAssembly::RETURN))
1360       .addReg(Reg);
1361   return true;
1362 }
1363 
1364 bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
1365   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1366           TII.get(WebAssembly::UNREACHABLE));
1367   return true;
1368 }
1369 
1370 bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
1371   switch (I->getOpcode()) {
1372   case Instruction::Call:
1373     if (selectCall(I))
1374       return true;
1375     break;
1376   case Instruction::Select:
1377     return selectSelect(I);
1378   case Instruction::Trunc:
1379     return selectTrunc(I);
1380   case Instruction::ZExt:
1381     return selectZExt(I);
1382   case Instruction::SExt:
1383     return selectSExt(I);
1384   case Instruction::ICmp:
1385     return selectICmp(I);
1386   case Instruction::FCmp:
1387     return selectFCmp(I);
1388   case Instruction::BitCast:
1389     return selectBitCast(I);
1390   case Instruction::Load:
1391     return selectLoad(I);
1392   case Instruction::Store:
1393     return selectStore(I);
1394   case Instruction::Br:
1395     return selectBr(I);
1396   case Instruction::Ret:
1397     return selectRet(I);
1398   case Instruction::Unreachable:
1399     return selectUnreachable(I);
1400   default:
1401     break;
1402   }
1403 
1404   // Fall back to target-independent instruction selection.
1405   return selectOperator(I, I->getOpcode());
1406 }
1407 
1408 FastISel *WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
1409                                       const TargetLibraryInfo *LibInfo) {
1410   return new WebAssemblyFastISel(FuncInfo, LibInfo);
1411 }
1412