1 //===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific support for the FastISel
11 /// class. Some of the target-specific code is generated by tablegen in the file
12 /// WebAssemblyGenFastISel.inc, which is #included here.
13 ///
14 /// TODO: kill flags
15 ///
16 //===----------------------------------------------------------------------===//
17 
18 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
19 #include "WebAssembly.h"
20 #include "WebAssemblyMachineFunctionInfo.h"
21 #include "WebAssemblySubtarget.h"
22 #include "WebAssemblyTargetMachine.h"
23 #include "llvm/Analysis/BranchProbabilityInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GetElementPtrTypeIterator.h"
34 #include "llvm/IR/GlobalAlias.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/IntrinsicInst.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/IR/PatternMatch.h"
40 
41 using namespace llvm;
42 using namespace PatternMatch;
43 
44 #define DEBUG_TYPE "wasm-fastisel"
45 
46 namespace {
47 
48 class WebAssemblyFastISel final : public FastISel {
49   // All possible address modes.
50   class Address {
51   public:
52     using BaseKind = enum { RegBase, FrameIndexBase };
53 
54   private:
55     BaseKind Kind = RegBase;
56     union {
57       unsigned Reg;
58       int FI;
59     } Base;
60 
61     // Whether the base has been determined yet
62     bool IsBaseSet = false;
63 
64     int64_t Offset = 0;
65 
66     const GlobalValue *GV = nullptr;
67 
68   public:
69     // Innocuous defaults for our address.
70     Address() { Base.Reg = 0; }
71     void setKind(BaseKind K) {
72       assert(!isSet() && "Can't change kind with non-zero base");
73       Kind = K;
74     }
75     BaseKind getKind() const { return Kind; }
76     bool isRegBase() const { return Kind == RegBase; }
77     bool isFIBase() const { return Kind == FrameIndexBase; }
78     void setReg(unsigned Reg) {
79       assert(isRegBase() && "Invalid base register access!");
80       assert(!IsBaseSet && "Base cannot be reset");
81       Base.Reg = Reg;
82       IsBaseSet = true;
83     }
84     unsigned getReg() const {
85       assert(isRegBase() && "Invalid base register access!");
86       return Base.Reg;
87     }
88     void setFI(unsigned FI) {
89       assert(isFIBase() && "Invalid base frame index access!");
90       assert(!IsBaseSet && "Base cannot be reset");
91       Base.FI = FI;
92       IsBaseSet = true;
93     }
94     unsigned getFI() const {
95       assert(isFIBase() && "Invalid base frame index access!");
96       return Base.FI;
97     }
98 
99     void setOffset(int64_t NewOffset) {
100       assert(NewOffset >= 0 && "Offsets must be non-negative");
101       Offset = NewOffset;
102     }
103     int64_t getOffset() const { return Offset; }
104     void setGlobalValue(const GlobalValue *G) { GV = G; }
105     const GlobalValue *getGlobalValue() const { return GV; }
106     bool isSet() const { return IsBaseSet; }
107   };
108 
109   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
110   /// right decision when generating code for different targets.
111   const WebAssemblySubtarget *Subtarget;
112   LLVMContext *Context;
113 
114 private:
115   // Utility helper routines
116   MVT::SimpleValueType getSimpleType(Type *Ty) {
117     EVT VT = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true);
118     return VT.isSimple() ? VT.getSimpleVT().SimpleTy
119                          : MVT::INVALID_SIMPLE_VALUE_TYPE;
120   }
121   MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
122     switch (VT) {
123     case MVT::i1:
124     case MVT::i8:
125     case MVT::i16:
126       return MVT::i32;
127     case MVT::i32:
128     case MVT::i64:
129     case MVT::f32:
130     case MVT::f64:
131     case MVT::exnref:
132     case MVT::funcref:
133     case MVT::externref:
134       return VT;
135     case MVT::f16:
136       return MVT::f32;
137     case MVT::v16i8:
138     case MVT::v8i16:
139     case MVT::v4i32:
140     case MVT::v4f32:
141       if (Subtarget->hasSIMD128())
142         return VT;
143       break;
144     case MVT::v2i64:
145     case MVT::v2f64:
146       if (Subtarget->hasUnimplementedSIMD128())
147         return VT;
148       break;
149     default:
150       break;
151     }
152     return MVT::INVALID_SIMPLE_VALUE_TYPE;
153   }
154   bool computeAddress(const Value *Obj, Address &Addr);
155   void materializeLoadStoreOperands(Address &Addr);
156   void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
157                             MachineMemOperand *MMO);
158   unsigned maskI1Value(unsigned Reg, const Value *V);
159   unsigned getRegForI1Value(const Value *V, bool &Not);
160   unsigned zeroExtendToI32(unsigned Reg, const Value *V,
161                            MVT::SimpleValueType From);
162   unsigned signExtendToI32(unsigned Reg, const Value *V,
163                            MVT::SimpleValueType From);
164   unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
165                       MVT::SimpleValueType To);
166   unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
167                       MVT::SimpleValueType To);
168   unsigned getRegForUnsignedValue(const Value *V);
169   unsigned getRegForSignedValue(const Value *V);
170   unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
171   unsigned notValue(unsigned Reg);
172   unsigned copyValue(unsigned Reg);
173 
174   // Backend specific FastISel code.
175   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
176   unsigned fastMaterializeConstant(const Constant *C) override;
177   bool fastLowerArguments() override;
178 
179   // Selection routines.
180   bool selectCall(const Instruction *I);
181   bool selectSelect(const Instruction *I);
182   bool selectTrunc(const Instruction *I);
183   bool selectZExt(const Instruction *I);
184   bool selectSExt(const Instruction *I);
185   bool selectICmp(const Instruction *I);
186   bool selectFCmp(const Instruction *I);
187   bool selectBitCast(const Instruction *I);
188   bool selectLoad(const Instruction *I);
189   bool selectStore(const Instruction *I);
190   bool selectBr(const Instruction *I);
191   bool selectRet(const Instruction *I);
192   bool selectUnreachable(const Instruction *I);
193 
194 public:
195   // Backend specific FastISel code.
196   WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
197                       const TargetLibraryInfo *LibInfo)
198       : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
199     Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
200     Context = &FuncInfo.Fn->getContext();
201   }
202 
203   bool fastSelectInstruction(const Instruction *I) override;
204 
205 #include "WebAssemblyGenFastISel.inc"
206 };
207 
208 } // end anonymous namespace
209 
210 bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
211   const User *U = nullptr;
212   unsigned Opcode = Instruction::UserOp1;
213   if (const auto *I = dyn_cast<Instruction>(Obj)) {
214     // Don't walk into other basic blocks unless the object is an alloca from
215     // another block, otherwise it may not have a virtual register assigned.
216     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
217         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
218       Opcode = I->getOpcode();
219       U = I;
220     }
221   } else if (const auto *C = dyn_cast<ConstantExpr>(Obj)) {
222     Opcode = C->getOpcode();
223     U = C;
224   }
225 
226   if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
227     if (Ty->getAddressSpace() > 255)
228       // Fast instruction selection doesn't support the special
229       // address spaces.
230       return false;
231 
232   if (const auto *GV = dyn_cast<GlobalValue>(Obj)) {
233     if (TLI.isPositionIndependent())
234       return false;
235     if (Addr.getGlobalValue())
236       return false;
237     if (GV->isThreadLocal())
238       return false;
239     Addr.setGlobalValue(GV);
240     return true;
241   }
242 
243   switch (Opcode) {
244   default:
245     break;
246   case Instruction::BitCast: {
247     // Look through bitcasts.
248     return computeAddress(U->getOperand(0), Addr);
249   }
250   case Instruction::IntToPtr: {
251     // Look past no-op inttoptrs.
252     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
253         TLI.getPointerTy(DL))
254       return computeAddress(U->getOperand(0), Addr);
255     break;
256   }
257   case Instruction::PtrToInt: {
258     // Look past no-op ptrtoints.
259     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
260       return computeAddress(U->getOperand(0), Addr);
261     break;
262   }
263   case Instruction::GetElementPtr: {
264     Address SavedAddr = Addr;
265     uint64_t TmpOffset = Addr.getOffset();
266     // Non-inbounds geps can wrap; wasm's offsets can't.
267     if (!cast<GEPOperator>(U)->isInBounds())
268       goto unsupported_gep;
269     // Iterate through the GEP folding the constants into offsets where
270     // we can.
271     for (gep_type_iterator GTI = gep_type_begin(U), E = gep_type_end(U);
272          GTI != E; ++GTI) {
273       const Value *Op = GTI.getOperand();
274       if (StructType *STy = GTI.getStructTypeOrNull()) {
275         const StructLayout *SL = DL.getStructLayout(STy);
276         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
277         TmpOffset += SL->getElementOffset(Idx);
278       } else {
279         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
280         for (;;) {
281           if (const auto *CI = dyn_cast<ConstantInt>(Op)) {
282             // Constant-offset addressing.
283             TmpOffset += CI->getSExtValue() * S;
284             break;
285           }
286           if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
287             // An unscaled add of a register. Set it as the new base.
288             unsigned Reg = getRegForValue(Op);
289             if (Reg == 0)
290               return false;
291             Addr.setReg(Reg);
292             break;
293           }
294           if (canFoldAddIntoGEP(U, Op)) {
295             // A compatible add with a constant operand. Fold the constant.
296             auto *CI = cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
297             TmpOffset += CI->getSExtValue() * S;
298             // Iterate on the other operand.
299             Op = cast<AddOperator>(Op)->getOperand(0);
300             continue;
301           }
302           // Unsupported
303           goto unsupported_gep;
304         }
305       }
306     }
307     // Don't fold in negative offsets.
308     if (int64_t(TmpOffset) >= 0) {
309       // Try to grab the base operand now.
310       Addr.setOffset(TmpOffset);
311       if (computeAddress(U->getOperand(0), Addr))
312         return true;
313     }
314     // We failed, restore everything and try the other options.
315     Addr = SavedAddr;
316   unsupported_gep:
317     break;
318   }
319   case Instruction::Alloca: {
320     const auto *AI = cast<AllocaInst>(Obj);
321     DenseMap<const AllocaInst *, int>::iterator SI =
322         FuncInfo.StaticAllocaMap.find(AI);
323     if (SI != FuncInfo.StaticAllocaMap.end()) {
324       if (Addr.isSet()) {
325         return false;
326       }
327       Addr.setKind(Address::FrameIndexBase);
328       Addr.setFI(SI->second);
329       return true;
330     }
331     break;
332   }
333   case Instruction::Add: {
334     // Adds of constants are common and easy enough.
335     const Value *LHS = U->getOperand(0);
336     const Value *RHS = U->getOperand(1);
337 
338     if (isa<ConstantInt>(LHS))
339       std::swap(LHS, RHS);
340 
341     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
342       uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
343       if (int64_t(TmpOffset) >= 0) {
344         Addr.setOffset(TmpOffset);
345         return computeAddress(LHS, Addr);
346       }
347     }
348 
349     Address Backup = Addr;
350     if (computeAddress(LHS, Addr) && computeAddress(RHS, Addr))
351       return true;
352     Addr = Backup;
353 
354     break;
355   }
356   case Instruction::Sub: {
357     // Subs of constants are common and easy enough.
358     const Value *LHS = U->getOperand(0);
359     const Value *RHS = U->getOperand(1);
360 
361     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
362       int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
363       if (TmpOffset >= 0) {
364         Addr.setOffset(TmpOffset);
365         return computeAddress(LHS, Addr);
366       }
367     }
368     break;
369   }
370   }
371   if (Addr.isSet()) {
372     return false;
373   }
374   unsigned Reg = getRegForValue(Obj);
375   if (Reg == 0)
376     return false;
377   Addr.setReg(Reg);
378   return Addr.getReg() != 0;
379 }
380 
381 void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
382   if (Addr.isRegBase()) {
383     unsigned Reg = Addr.getReg();
384     if (Reg == 0) {
385       Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
386                                                    : &WebAssembly::I32RegClass);
387       unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
388                                             : WebAssembly::CONST_I32;
389       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
390           .addImm(0);
391       Addr.setReg(Reg);
392     }
393   }
394 }
395 
396 void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
397                                                const MachineInstrBuilder &MIB,
398                                                MachineMemOperand *MMO) {
399   // Set the alignment operand (this is rewritten in SetP2AlignOperands).
400   // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
401   MIB.addImm(0);
402 
403   if (const GlobalValue *GV = Addr.getGlobalValue())
404     MIB.addGlobalAddress(GV, Addr.getOffset());
405   else
406     MIB.addImm(Addr.getOffset());
407 
408   if (Addr.isRegBase())
409     MIB.addReg(Addr.getReg());
410   else
411     MIB.addFrameIndex(Addr.getFI());
412 
413   MIB.addMemOperand(MMO);
414 }
415 
416 unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
417   return zeroExtendToI32(Reg, V, MVT::i1);
418 }
419 
420 unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V, bool &Not) {
421   if (const auto *ICmp = dyn_cast<ICmpInst>(V))
422     if (const ConstantInt *C = dyn_cast<ConstantInt>(ICmp->getOperand(1)))
423       if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(32)) {
424         Not = ICmp->isTrueWhenEqual();
425         return getRegForValue(ICmp->getOperand(0));
426       }
427 
428   Value *NotV;
429   if (match(V, m_Not(m_Value(NotV))) && V->getType()->isIntegerTy(32)) {
430     Not = true;
431     return getRegForValue(NotV);
432   }
433 
434   Not = false;
435   unsigned Reg = getRegForValue(V);
436   if (Reg == 0)
437     return 0;
438   return maskI1Value(Reg, V);
439 }
440 
441 unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
442                                               MVT::SimpleValueType From) {
443   if (Reg == 0)
444     return 0;
445 
446   switch (From) {
447   case MVT::i1:
448     // If the value is naturally an i1, we don't need to mask it. We only know
449     // if a value is naturally an i1 if it is definitely lowered by FastISel,
450     // not a DAG ISel fallback.
451     if (V != nullptr && isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr())
452       return copyValue(Reg);
453     break;
454   case MVT::i8:
455   case MVT::i16:
456     break;
457   case MVT::i32:
458     return copyValue(Reg);
459   default:
460     return 0;
461   }
462 
463   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
464   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
465           TII.get(WebAssembly::CONST_I32), Imm)
466       .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));
467 
468   unsigned Result = createResultReg(&WebAssembly::I32RegClass);
469   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
470           TII.get(WebAssembly::AND_I32), Result)
471       .addReg(Reg)
472       .addReg(Imm);
473 
474   return Result;
475 }
476 
477 unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
478                                               MVT::SimpleValueType From) {
479   if (Reg == 0)
480     return 0;
481 
482   switch (From) {
483   case MVT::i1:
484   case MVT::i8:
485   case MVT::i16:
486     break;
487   case MVT::i32:
488     return copyValue(Reg);
489   default:
490     return 0;
491   }
492 
493   unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
494   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
495           TII.get(WebAssembly::CONST_I32), Imm)
496       .addImm(32 - MVT(From).getSizeInBits());
497 
498   unsigned Left = createResultReg(&WebAssembly::I32RegClass);
499   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
500           TII.get(WebAssembly::SHL_I32), Left)
501       .addReg(Reg)
502       .addReg(Imm);
503 
504   unsigned Right = createResultReg(&WebAssembly::I32RegClass);
505   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
506           TII.get(WebAssembly::SHR_S_I32), Right)
507       .addReg(Left)
508       .addReg(Imm);
509 
510   return Right;
511 }
512 
513 unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
514                                          MVT::SimpleValueType From,
515                                          MVT::SimpleValueType To) {
516   if (To == MVT::i64) {
517     if (From == MVT::i64)
518       return copyValue(Reg);
519 
520     Reg = zeroExtendToI32(Reg, V, From);
521 
522     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
523     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
524             TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
525         .addReg(Reg);
526     return Result;
527   }
528 
529   if (To == MVT::i32)
530     return zeroExtendToI32(Reg, V, From);
531 
532   return 0;
533 }
534 
535 unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
536                                          MVT::SimpleValueType From,
537                                          MVT::SimpleValueType To) {
538   if (To == MVT::i64) {
539     if (From == MVT::i64)
540       return copyValue(Reg);
541 
542     Reg = signExtendToI32(Reg, V, From);
543 
544     unsigned Result = createResultReg(&WebAssembly::I64RegClass);
545     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
546             TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
547         .addReg(Reg);
548     return Result;
549   }
550 
551   if (To == MVT::i32)
552     return signExtendToI32(Reg, V, From);
553 
554   return 0;
555 }
556 
557 unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
558   MVT::SimpleValueType From = getSimpleType(V->getType());
559   MVT::SimpleValueType To = getLegalType(From);
560   unsigned VReg = getRegForValue(V);
561   if (VReg == 0)
562     return 0;
563   return zeroExtend(VReg, V, From, To);
564 }
565 
566 unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
567   MVT::SimpleValueType From = getSimpleType(V->getType());
568   MVT::SimpleValueType To = getLegalType(From);
569   unsigned VReg = getRegForValue(V);
570   if (VReg == 0)
571     return 0;
572   return signExtend(VReg, V, From, To);
573 }
574 
575 unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
576                                                      bool IsSigned) {
577   return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
578 }
579 
580 unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
581   assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
582 
583   unsigned NotReg = createResultReg(&WebAssembly::I32RegClass);
584   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
585           TII.get(WebAssembly::EQZ_I32), NotReg)
586       .addReg(Reg);
587   return NotReg;
588 }
589 
590 unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
591   unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
592   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
593           ResultReg)
594       .addReg(Reg);
595   return ResultReg;
596 }
597 
598 unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
599   DenseMap<const AllocaInst *, int>::iterator SI =
600       FuncInfo.StaticAllocaMap.find(AI);
601 
602   if (SI != FuncInfo.StaticAllocaMap.end()) {
603     unsigned ResultReg =
604         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
605                                                : &WebAssembly::I32RegClass);
606     unsigned Opc =
607         Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
608     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
609         .addFrameIndex(SI->second);
610     return ResultReg;
611   }
612 
613   return 0;
614 }
615 
616 unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
617   if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
618     if (TLI.isPositionIndependent())
619       return 0;
620     if (GV->isThreadLocal())
621       return 0;
622     unsigned ResultReg =
623         createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
624                                                : &WebAssembly::I32RegClass);
625     unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
626                                           : WebAssembly::CONST_I32;
627     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
628         .addGlobalAddress(GV);
629     return ResultReg;
630   }
631 
632   // Let target-independent code handle it.
633   return 0;
634 }
635 
636 bool WebAssemblyFastISel::fastLowerArguments() {
637   if (!FuncInfo.CanLowerReturn)
638     return false;
639 
640   const Function *F = FuncInfo.Fn;
641   if (F->isVarArg())
642     return false;
643 
644   if (FuncInfo.Fn->getCallingConv() == CallingConv::Swift)
645     return false;
646 
647   unsigned I = 0;
648   for (auto const &Arg : F->args()) {
649     const AttributeList &Attrs = F->getAttributes();
650     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
651         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
652         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
653         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
654         Attrs.hasParamAttribute(I, Attribute::Nest))
655       return false;
656 
657     Type *ArgTy = Arg.getType();
658     if (ArgTy->isStructTy() || ArgTy->isArrayTy())
659       return false;
660     if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
661       return false;
662 
663     unsigned Opc;
664     const TargetRegisterClass *RC;
665     switch (getSimpleType(ArgTy)) {
666     case MVT::i1:
667     case MVT::i8:
668     case MVT::i16:
669     case MVT::i32:
670       Opc = WebAssembly::ARGUMENT_i32;
671       RC = &WebAssembly::I32RegClass;
672       break;
673     case MVT::i64:
674       Opc = WebAssembly::ARGUMENT_i64;
675       RC = &WebAssembly::I64RegClass;
676       break;
677     case MVT::f32:
678       Opc = WebAssembly::ARGUMENT_f32;
679       RC = &WebAssembly::F32RegClass;
680       break;
681     case MVT::f64:
682       Opc = WebAssembly::ARGUMENT_f64;
683       RC = &WebAssembly::F64RegClass;
684       break;
685     case MVT::v16i8:
686       Opc = WebAssembly::ARGUMENT_v16i8;
687       RC = &WebAssembly::V128RegClass;
688       break;
689     case MVT::v8i16:
690       Opc = WebAssembly::ARGUMENT_v8i16;
691       RC = &WebAssembly::V128RegClass;
692       break;
693     case MVT::v4i32:
694       Opc = WebAssembly::ARGUMENT_v4i32;
695       RC = &WebAssembly::V128RegClass;
696       break;
697     case MVT::v2i64:
698       Opc = WebAssembly::ARGUMENT_v2i64;
699       RC = &WebAssembly::V128RegClass;
700       break;
701     case MVT::v4f32:
702       Opc = WebAssembly::ARGUMENT_v4f32;
703       RC = &WebAssembly::V128RegClass;
704       break;
705     case MVT::v2f64:
706       Opc = WebAssembly::ARGUMENT_v2f64;
707       RC = &WebAssembly::V128RegClass;
708       break;
709     case MVT::exnref:
710       Opc = WebAssembly::ARGUMENT_exnref;
711       RC = &WebAssembly::EXNREFRegClass;
712       break;
713     default:
714       return false;
715     }
716     unsigned ResultReg = createResultReg(RC);
717     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
718         .addImm(I);
719     updateValueMap(&Arg, ResultReg);
720 
721     ++I;
722   }
723 
724   MRI.addLiveIn(WebAssembly::ARGUMENTS);
725 
726   auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
727   for (auto const &Arg : F->args()) {
728     MVT::SimpleValueType ArgTy = getLegalType(getSimpleType(Arg.getType()));
729     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
730       MFI->clearParamsAndResults();
731       return false;
732     }
733     MFI->addParam(ArgTy);
734   }
735 
736   if (!F->getReturnType()->isVoidTy()) {
737     MVT::SimpleValueType RetTy =
738         getLegalType(getSimpleType(F->getReturnType()));
739     if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
740       MFI->clearParamsAndResults();
741       return false;
742     }
743     MFI->addResult(RetTy);
744   }
745 
746   return true;
747 }
748 
749 bool WebAssemblyFastISel::selectCall(const Instruction *I) {
750   const auto *Call = cast<CallInst>(I);
751 
752   // TODO: Support tail calls in FastISel
753   if (Call->isMustTailCall() || Call->isInlineAsm() ||
754       Call->getFunctionType()->isVarArg())
755     return false;
756 
757   Function *Func = Call->getCalledFunction();
758   if (Func && Func->isIntrinsic())
759     return false;
760 
761   if (Call->getCallingConv() == CallingConv::Swift)
762     return false;
763 
764   bool IsDirect = Func != nullptr;
765   if (!IsDirect && isa<ConstantExpr>(Call->getCalledOperand()))
766     return false;
767 
768   FunctionType *FuncTy = Call->getFunctionType();
769   unsigned Opc = IsDirect ? WebAssembly::CALL : WebAssembly::CALL_INDIRECT;
770   bool IsVoid = FuncTy->getReturnType()->isVoidTy();
771   unsigned ResultReg;
772   if (!IsVoid) {
773     if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
774       return false;
775 
776     MVT::SimpleValueType RetTy = getSimpleType(Call->getType());
777     switch (RetTy) {
778     case MVT::i1:
779     case MVT::i8:
780     case MVT::i16:
781     case MVT::i32:
782       ResultReg = createResultReg(&WebAssembly::I32RegClass);
783       break;
784     case MVT::i64:
785       ResultReg = createResultReg(&WebAssembly::I64RegClass);
786       break;
787     case MVT::f32:
788       ResultReg = createResultReg(&WebAssembly::F32RegClass);
789       break;
790     case MVT::f64:
791       ResultReg = createResultReg(&WebAssembly::F64RegClass);
792       break;
793     case MVT::v16i8:
794       ResultReg = createResultReg(&WebAssembly::V128RegClass);
795       break;
796     case MVT::v8i16:
797       ResultReg = createResultReg(&WebAssembly::V128RegClass);
798       break;
799     case MVT::v4i32:
800       ResultReg = createResultReg(&WebAssembly::V128RegClass);
801       break;
802     case MVT::v2i64:
803       ResultReg = createResultReg(&WebAssembly::V128RegClass);
804       break;
805     case MVT::v4f32:
806       ResultReg = createResultReg(&WebAssembly::V128RegClass);
807       break;
808     case MVT::v2f64:
809       ResultReg = createResultReg(&WebAssembly::V128RegClass);
810       break;
811     case MVT::exnref:
812       ResultReg = createResultReg(&WebAssembly::EXNREFRegClass);
813       break;
814     case MVT::funcref:
815       ResultReg = createResultReg(&WebAssembly::FUNCREFRegClass);
816       break;
817     case MVT::externref:
818       ResultReg = createResultReg(&WebAssembly::EXTERNREFRegClass);
819       break;
820     default:
821       return false;
822     }
823   }
824 
825   SmallVector<unsigned, 8> Args;
826   for (unsigned I = 0, E = Call->getNumArgOperands(); I < E; ++I) {
827     Value *V = Call->getArgOperand(I);
828     MVT::SimpleValueType ArgTy = getSimpleType(V->getType());
829     if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
830       return false;
831 
832     const AttributeList &Attrs = Call->getAttributes();
833     if (Attrs.hasParamAttribute(I, Attribute::ByVal) ||
834         Attrs.hasParamAttribute(I, Attribute::SwiftSelf) ||
835         Attrs.hasParamAttribute(I, Attribute::SwiftError) ||
836         Attrs.hasParamAttribute(I, Attribute::InAlloca) ||
837         Attrs.hasParamAttribute(I, Attribute::Nest))
838       return false;
839 
840     unsigned Reg;
841 
842     if (Attrs.hasParamAttribute(I, Attribute::SExt))
843       Reg = getRegForSignedValue(V);
844     else if (Attrs.hasParamAttribute(I, Attribute::ZExt))
845       Reg = getRegForUnsignedValue(V);
846     else
847       Reg = getRegForValue(V);
848 
849     if (Reg == 0)
850       return false;
851 
852     Args.push_back(Reg);
853   }
854 
855   unsigned CalleeReg = 0;
856   if (!IsDirect) {
857     CalleeReg = getRegForValue(Call->getCalledOperand());
858     if (!CalleeReg)
859       return false;
860   }
861 
862   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
863 
864   if (!IsVoid)
865     MIB.addReg(ResultReg, RegState::Define);
866 
867   if (IsDirect) {
868     MIB.addGlobalAddress(Func);
869   } else {
870     // Add placeholders for the type index and immediate flags
871     MIB.addImm(0);
872     MIB.addImm(0);
873   }
874 
875   for (unsigned ArgReg : Args)
876     MIB.addReg(ArgReg);
877 
878   if (!IsDirect)
879     MIB.addReg(CalleeReg);
880 
881   if (!IsVoid)
882     updateValueMap(Call, ResultReg);
883   return true;
884 }
885 
886 bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
887   const auto *Select = cast<SelectInst>(I);
888 
889   bool Not;
890   unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
891   if (CondReg == 0)
892     return false;
893 
894   unsigned TrueReg = getRegForValue(Select->getTrueValue());
895   if (TrueReg == 0)
896     return false;
897 
898   unsigned FalseReg = getRegForValue(Select->getFalseValue());
899   if (FalseReg == 0)
900     return false;
901 
902   if (Not)
903     std::swap(TrueReg, FalseReg);
904 
905   unsigned Opc;
906   const TargetRegisterClass *RC;
907   switch (getSimpleType(Select->getType())) {
908   case MVT::i1:
909   case MVT::i8:
910   case MVT::i16:
911   case MVT::i32:
912     Opc = WebAssembly::SELECT_I32;
913     RC = &WebAssembly::I32RegClass;
914     break;
915   case MVT::i64:
916     Opc = WebAssembly::SELECT_I64;
917     RC = &WebAssembly::I64RegClass;
918     break;
919   case MVT::f32:
920     Opc = WebAssembly::SELECT_F32;
921     RC = &WebAssembly::F32RegClass;
922     break;
923   case MVT::f64:
924     Opc = WebAssembly::SELECT_F64;
925     RC = &WebAssembly::F64RegClass;
926     break;
927   case MVT::exnref:
928     Opc = WebAssembly::SELECT_EXNREF;
929     RC = &WebAssembly::EXNREFRegClass;
930     break;
931   default:
932     return false;
933   }
934 
935   unsigned ResultReg = createResultReg(RC);
936   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
937       .addReg(TrueReg)
938       .addReg(FalseReg)
939       .addReg(CondReg);
940 
941   updateValueMap(Select, ResultReg);
942   return true;
943 }
944 
945 bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
946   const auto *Trunc = cast<TruncInst>(I);
947 
948   unsigned Reg = getRegForValue(Trunc->getOperand(0));
949   if (Reg == 0)
950     return false;
951 
952   if (Trunc->getOperand(0)->getType()->isIntegerTy(64)) {
953     unsigned Result = createResultReg(&WebAssembly::I32RegClass);
954     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
955             TII.get(WebAssembly::I32_WRAP_I64), Result)
956         .addReg(Reg);
957     Reg = Result;
958   }
959 
960   updateValueMap(Trunc, Reg);
961   return true;
962 }
963 
964 bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
965   const auto *ZExt = cast<ZExtInst>(I);
966 
967   const Value *Op = ZExt->getOperand(0);
968   MVT::SimpleValueType From = getSimpleType(Op->getType());
969   MVT::SimpleValueType To = getLegalType(getSimpleType(ZExt->getType()));
970   unsigned In = getRegForValue(Op);
971   if (In == 0)
972     return false;
973   unsigned Reg = zeroExtend(In, Op, From, To);
974   if (Reg == 0)
975     return false;
976 
977   updateValueMap(ZExt, Reg);
978   return true;
979 }
980 
981 bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
982   const auto *SExt = cast<SExtInst>(I);
983 
984   const Value *Op = SExt->getOperand(0);
985   MVT::SimpleValueType From = getSimpleType(Op->getType());
986   MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType()));
987   unsigned In = getRegForValue(Op);
988   if (In == 0)
989     return false;
990   unsigned Reg = signExtend(In, Op, From, To);
991   if (Reg == 0)
992     return false;
993 
994   updateValueMap(SExt, Reg);
995   return true;
996 }
997 
998 bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
999   const auto *ICmp = cast<ICmpInst>(I);
1000 
1001   bool I32 = getSimpleType(ICmp->getOperand(0)->getType()) != MVT::i64;
1002   unsigned Opc;
1003   bool IsSigned = false;
1004   switch (ICmp->getPredicate()) {
1005   case ICmpInst::ICMP_EQ:
1006     Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
1007     break;
1008   case ICmpInst::ICMP_NE:
1009     Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
1010     break;
1011   case ICmpInst::ICMP_UGT:
1012     Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
1013     break;
1014   case ICmpInst::ICMP_UGE:
1015     Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
1016     break;
1017   case ICmpInst::ICMP_ULT:
1018     Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
1019     break;
1020   case ICmpInst::ICMP_ULE:
1021     Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
1022     break;
1023   case ICmpInst::ICMP_SGT:
1024     Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
1025     IsSigned = true;
1026     break;
1027   case ICmpInst::ICMP_SGE:
1028     Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
1029     IsSigned = true;
1030     break;
1031   case ICmpInst::ICMP_SLT:
1032     Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
1033     IsSigned = true;
1034     break;
1035   case ICmpInst::ICMP_SLE:
1036     Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
1037     IsSigned = true;
1038     break;
1039   default:
1040     return false;
1041   }
1042 
1043   unsigned LHS = getRegForPromotedValue(ICmp->getOperand(0), IsSigned);
1044   if (LHS == 0)
1045     return false;
1046 
1047   unsigned RHS = getRegForPromotedValue(ICmp->getOperand(1), IsSigned);
1048   if (RHS == 0)
1049     return false;
1050 
1051   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1052   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1053       .addReg(LHS)
1054       .addReg(RHS);
1055   updateValueMap(ICmp, ResultReg);
1056   return true;
1057 }
1058 
1059 bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
1060   const auto *FCmp = cast<FCmpInst>(I);
1061 
1062   unsigned LHS = getRegForValue(FCmp->getOperand(0));
1063   if (LHS == 0)
1064     return false;
1065 
1066   unsigned RHS = getRegForValue(FCmp->getOperand(1));
1067   if (RHS == 0)
1068     return false;
1069 
1070   bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64;
1071   unsigned Opc;
1072   bool Not = false;
1073   switch (FCmp->getPredicate()) {
1074   case FCmpInst::FCMP_OEQ:
1075     Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
1076     break;
1077   case FCmpInst::FCMP_UNE:
1078     Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
1079     break;
1080   case FCmpInst::FCMP_OGT:
1081     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1082     break;
1083   case FCmpInst::FCMP_OGE:
1084     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1085     break;
1086   case FCmpInst::FCMP_OLT:
1087     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1088     break;
1089   case FCmpInst::FCMP_OLE:
1090     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1091     break;
1092   case FCmpInst::FCMP_UGT:
1093     Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
1094     Not = true;
1095     break;
1096   case FCmpInst::FCMP_UGE:
1097     Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
1098     Not = true;
1099     break;
1100   case FCmpInst::FCMP_ULT:
1101     Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
1102     Not = true;
1103     break;
1104   case FCmpInst::FCMP_ULE:
1105     Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
1106     Not = true;
1107     break;
1108   default:
1109     return false;
1110   }
1111 
1112   unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
1113   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1114       .addReg(LHS)
1115       .addReg(RHS);
1116 
1117   if (Not)
1118     ResultReg = notValue(ResultReg);
1119 
1120   updateValueMap(FCmp, ResultReg);
1121   return true;
1122 }
1123 
1124 bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
1125   // Target-independent code can handle this, except it doesn't set the dead
1126   // flag on the ARGUMENTS clobber, so we have to do that manually in order
1127   // to satisfy code that expects this of isBitcast() instructions.
1128   EVT VT = TLI.getValueType(DL, I->getOperand(0)->getType());
1129   EVT RetVT = TLI.getValueType(DL, I->getType());
1130   if (!VT.isSimple() || !RetVT.isSimple())
1131     return false;
1132 
1133   unsigned In = getRegForValue(I->getOperand(0));
1134   if (In == 0)
1135     return false;
1136 
1137   if (VT == RetVT) {
1138     // No-op bitcast.
1139     updateValueMap(I, In);
1140     return true;
1141   }
1142 
1143   Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
1144                                         In, I->getOperand(0)->hasOneUse());
1145   if (!Reg)
1146     return false;
1147   MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
1148   --Iter;
1149   assert(Iter->isBitcast());
1150   Iter->setPhysRegsDeadExcept(ArrayRef<Register>(), TRI);
1151   updateValueMap(I, Reg);
1152   return true;
1153 }
1154 
1155 bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
1156   const auto *Load = cast<LoadInst>(I);
1157   if (Load->isAtomic())
1158     return false;
1159   if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
1160     return false;
1161 
1162   Address Addr;
1163   if (!computeAddress(Load->getPointerOperand(), Addr))
1164     return false;
1165 
1166   // TODO: Fold a following sign-/zero-extend into the load instruction.
1167 
1168   unsigned Opc;
1169   const TargetRegisterClass *RC;
1170   bool A64 = Subtarget->hasAddr64();
1171   switch (getSimpleType(Load->getType())) {
1172   case MVT::i1:
1173   case MVT::i8:
1174     Opc = A64 ? WebAssembly::LOAD8_U_I32_A64 : WebAssembly::LOAD8_U_I32_A32;
1175     RC = &WebAssembly::I32RegClass;
1176     break;
1177   case MVT::i16:
1178     Opc = A64 ? WebAssembly::LOAD16_U_I32_A64 : WebAssembly::LOAD16_U_I32_A32;
1179     RC = &WebAssembly::I32RegClass;
1180     break;
1181   case MVT::i32:
1182     Opc = A64 ? WebAssembly::LOAD_I32_A64 : WebAssembly::LOAD_I32_A32;
1183     RC = &WebAssembly::I32RegClass;
1184     break;
1185   case MVT::i64:
1186     Opc = A64 ? WebAssembly::LOAD_I64_A64 : WebAssembly::LOAD_I64_A32;
1187     RC = &WebAssembly::I64RegClass;
1188     break;
1189   case MVT::f32:
1190     Opc = A64 ? WebAssembly::LOAD_F32_A64 : WebAssembly::LOAD_F32_A32;
1191     RC = &WebAssembly::F32RegClass;
1192     break;
1193   case MVT::f64:
1194     Opc = A64 ? WebAssembly::LOAD_F64_A64 : WebAssembly::LOAD_F64_A32;
1195     RC = &WebAssembly::F64RegClass;
1196     break;
1197   default:
1198     return false;
1199   }
1200 
1201   materializeLoadStoreOperands(Addr);
1202 
1203   unsigned ResultReg = createResultReg(RC);
1204   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1205                      ResultReg);
1206 
1207   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
1208 
1209   updateValueMap(Load, ResultReg);
1210   return true;
1211 }
1212 
1213 bool WebAssemblyFastISel::selectStore(const Instruction *I) {
1214   const auto *Store = cast<StoreInst>(I);
1215   if (Store->isAtomic())
1216     return false;
1217   if (!Subtarget->hasSIMD128() &&
1218       Store->getValueOperand()->getType()->isVectorTy())
1219     return false;
1220 
1221   Address Addr;
1222   if (!computeAddress(Store->getPointerOperand(), Addr))
1223     return false;
1224 
1225   unsigned Opc;
1226   bool VTIsi1 = false;
1227   bool A64 = Subtarget->hasAddr64();
1228   switch (getSimpleType(Store->getValueOperand()->getType())) {
1229   case MVT::i1:
1230     VTIsi1 = true;
1231     LLVM_FALLTHROUGH;
1232   case MVT::i8:
1233     Opc = A64 ? WebAssembly::STORE8_I32_A64 : WebAssembly::STORE8_I32_A32;
1234     break;
1235   case MVT::i16:
1236     Opc = A64 ? WebAssembly::STORE16_I32_A64 : WebAssembly::STORE16_I32_A32;
1237     break;
1238   case MVT::i32:
1239     Opc = A64 ? WebAssembly::STORE_I32_A64 : WebAssembly::STORE_I32_A32;
1240     break;
1241   case MVT::i64:
1242     Opc = A64 ? WebAssembly::STORE_I64_A64 : WebAssembly::STORE_I64_A32;
1243     break;
1244   case MVT::f32:
1245     Opc = A64 ? WebAssembly::STORE_F32_A64 : WebAssembly::STORE_F32_A32;
1246     break;
1247   case MVT::f64:
1248     Opc = A64 ? WebAssembly::STORE_F64_A64 : WebAssembly::STORE_F64_A32;
1249     break;
1250   default:
1251     return false;
1252   }
1253 
1254   materializeLoadStoreOperands(Addr);
1255 
1256   unsigned ValueReg = getRegForValue(Store->getValueOperand());
1257   if (ValueReg == 0)
1258     return false;
1259   if (VTIsi1)
1260     ValueReg = maskI1Value(ValueReg, Store->getValueOperand());
1261 
1262   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1263 
1264   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Store));
1265 
1266   MIB.addReg(ValueReg);
1267   return true;
1268 }
1269 
1270 bool WebAssemblyFastISel::selectBr(const Instruction *I) {
1271   const auto *Br = cast<BranchInst>(I);
1272   if (Br->isUnconditional()) {
1273     MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
1274     fastEmitBranch(MSucc, Br->getDebugLoc());
1275     return true;
1276   }
1277 
1278   MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
1279   MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
1280 
1281   bool Not;
1282   unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
1283   if (CondReg == 0)
1284     return false;
1285 
1286   unsigned Opc = WebAssembly::BR_IF;
1287   if (Not)
1288     Opc = WebAssembly::BR_UNLESS;
1289 
1290   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1291       .addMBB(TBB)
1292       .addReg(CondReg);
1293 
1294   finishCondBranch(Br->getParent(), TBB, FBB);
1295   return true;
1296 }
1297 
1298 bool WebAssemblyFastISel::selectRet(const Instruction *I) {
1299   if (!FuncInfo.CanLowerReturn)
1300     return false;
1301 
1302   const auto *Ret = cast<ReturnInst>(I);
1303 
1304   if (Ret->getNumOperands() == 0) {
1305     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1306             TII.get(WebAssembly::RETURN));
1307     return true;
1308   }
1309 
1310   // TODO: support multiple return in FastISel
1311   if (Ret->getNumOperands() > 1)
1312     return false;
1313 
1314   Value *RV = Ret->getOperand(0);
1315   if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
1316     return false;
1317 
1318   switch (getSimpleType(RV->getType())) {
1319   case MVT::i1:
1320   case MVT::i8:
1321   case MVT::i16:
1322   case MVT::i32:
1323   case MVT::i64:
1324   case MVT::f32:
1325   case MVT::f64:
1326   case MVT::v16i8:
1327   case MVT::v8i16:
1328   case MVT::v4i32:
1329   case MVT::v2i64:
1330   case MVT::v4f32:
1331   case MVT::v2f64:
1332   case MVT::exnref:
1333     break;
1334   default:
1335     return false;
1336   }
1337 
1338   unsigned Reg;
1339   if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
1340     Reg = getRegForSignedValue(RV);
1341   else if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::ZExt))
1342     Reg = getRegForUnsignedValue(RV);
1343   else
1344     Reg = getRegForValue(RV);
1345 
1346   if (Reg == 0)
1347     return false;
1348 
1349   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1350           TII.get(WebAssembly::RETURN))
1351       .addReg(Reg);
1352   return true;
1353 }
1354 
1355 bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
1356   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1357           TII.get(WebAssembly::UNREACHABLE));
1358   return true;
1359 }
1360 
1361 bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
1362   switch (I->getOpcode()) {
1363   case Instruction::Call:
1364     if (selectCall(I))
1365       return true;
1366     break;
1367   case Instruction::Select:
1368     return selectSelect(I);
1369   case Instruction::Trunc:
1370     return selectTrunc(I);
1371   case Instruction::ZExt:
1372     return selectZExt(I);
1373   case Instruction::SExt:
1374     return selectSExt(I);
1375   case Instruction::ICmp:
1376     return selectICmp(I);
1377   case Instruction::FCmp:
1378     return selectFCmp(I);
1379   case Instruction::BitCast:
1380     return selectBitCast(I);
1381   case Instruction::Load:
1382     return selectLoad(I);
1383   case Instruction::Store:
1384     return selectStore(I);
1385   case Instruction::Br:
1386     return selectBr(I);
1387   case Instruction::Ret:
1388     return selectRet(I);
1389   case Instruction::Unreachable:
1390     return selectUnreachable(I);
1391   default:
1392     break;
1393   }
1394 
1395   // Fall back to target-independent instruction selection.
1396   return selectOperator(I, I->getOpcode());
1397 }
1398 
1399 FastISel *WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
1400                                       const TargetLibraryInfo *LibInfo) {
1401   return new WebAssemblyFastISel(FuncInfo, LibInfo);
1402 }
1403