1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file provides WebAssembly-specific target descriptions. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 17 #include "../WebAssemblySubtarget.h" 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCInstrInfo; 28 class MCObjectTargetWriter; 29 class MVT; 30 class Triple; 31 32 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 33 34 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 35 36 std::unique_ptr<MCObjectTargetWriter> 37 createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten); 38 39 namespace WebAssembly { 40 enum OperandType { 41 /// Basic block label in a branch construct. 42 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 43 /// Local index. 44 OPERAND_LOCAL, 45 /// Global index. 46 OPERAND_GLOBAL, 47 /// 32-bit integer immediates. 48 OPERAND_I32IMM, 49 /// 64-bit integer immediates. 50 OPERAND_I64IMM, 51 /// 32-bit floating-point immediates. 52 OPERAND_F32IMM, 53 /// 64-bit floating-point immediates. 54 OPERAND_F64IMM, 55 /// 8-bit vector lane immediate 56 OPERAND_VEC_I8IMM, 57 /// 16-bit vector lane immediate 58 OPERAND_VEC_I16IMM, 59 /// 32-bit vector lane immediate 60 OPERAND_VEC_I32IMM, 61 /// 64-bit vector lane immediate 62 OPERAND_VEC_I64IMM, 63 /// 32-bit unsigned function indices. 64 OPERAND_FUNCTION32, 65 /// 32-bit unsigned memory offsets. 66 OPERAND_OFFSET32, 67 /// 64-bit unsigned memory offsets. 68 OPERAND_OFFSET64, 69 /// p2align immediate for load and store address alignment. 70 OPERAND_P2ALIGN, 71 /// signature immediate for block/loop. 72 OPERAND_SIGNATURE, 73 /// type signature immediate for call_indirect. 74 OPERAND_TYPEINDEX, 75 /// Event index. 76 OPERAND_EVENT, 77 /// A list of branch targets for br_list. 78 OPERAND_BRLIST, 79 }; 80 } // end namespace WebAssembly 81 82 namespace WebAssemblyII { 83 84 /// Target Operand Flag enum. 85 enum TOF { 86 MO_NO_FLAG = 0, 87 88 // On a symbol operand this indicates that the immediate is a wasm global 89 // index. The value of the wasm global will be set to the symbol address at 90 // runtime. This adds a level of indirection similar to the GOT on native 91 // platforms. 92 MO_GOT, 93 94 // On a symbol operand this indicates that the immediate is the symbol 95 // address relative the __memory_base wasm global. 96 // Only applicable to data symbols. 97 MO_MEMORY_BASE_REL, 98 99 // On a symbol operand this indicates that the immediate is the symbol 100 // address relative the __table_base wasm global. 101 // Only applicable to function symbols. 102 MO_TABLE_BASE_REL, 103 }; 104 105 } // end namespace WebAssemblyII 106 107 } // end namespace llvm 108 109 // Defines symbolic names for WebAssembly registers. This defines a mapping from 110 // register name to register number. 111 // 112 #define GET_REGINFO_ENUM 113 #include "WebAssemblyGenRegisterInfo.inc" 114 115 // Defines symbolic names for the WebAssembly instructions. 116 // 117 #define GET_INSTRINFO_ENUM 118 #include "WebAssemblyGenInstrInfo.inc" 119 120 namespace llvm { 121 namespace WebAssembly { 122 123 /// Used as immediate MachineOperands for block signatures 124 enum class BlockType : unsigned { 125 Invalid = 0x00, 126 Void = 0x40, 127 I32 = unsigned(wasm::ValType::I32), 128 I64 = unsigned(wasm::ValType::I64), 129 F32 = unsigned(wasm::ValType::F32), 130 F64 = unsigned(wasm::ValType::F64), 131 V128 = unsigned(wasm::ValType::V128), 132 Exnref = unsigned(wasm::ValType::EXNREF), 133 // Multivalue blocks (and other non-void blocks) are only emitted when the 134 // blocks will never be exited and are at the ends of functions (see 135 // WebAssemblyCFGStackify::fixEndsAtEndOfFunction). They also are never made 136 // to pop values off the stack, so the exact multivalue signature can always 137 // be inferred from the return type of the parent function in MCInstLower. 138 Multivalue = 0xffff, 139 }; 140 141 /// Instruction opcodes emitted via means other than CodeGen. 142 static const unsigned Nop = 0x01; 143 static const unsigned End = 0x0b; 144 145 wasm::ValType toValType(const MVT &Ty); 146 147 /// Return the default p2align value for a load or store with the given opcode. 148 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { 149 switch (Opc) { 150 #define WASM_LOAD_STORE(NAME) \ 151 case WebAssembly::NAME##_A32: \ 152 case WebAssembly::NAME##_A64: \ 153 case WebAssembly::NAME##_A32_S: \ 154 case WebAssembly::NAME##_A64_S: 155 WASM_LOAD_STORE(LOAD8_S_I32) 156 WASM_LOAD_STORE(LOAD8_U_I32) 157 WASM_LOAD_STORE(LOAD8_S_I64) 158 WASM_LOAD_STORE(LOAD8_U_I64) 159 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32) 160 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64) 161 WASM_LOAD_STORE(STORE8_I32) 162 WASM_LOAD_STORE(STORE8_I64) 163 WASM_LOAD_STORE(ATOMIC_STORE8_I32) 164 WASM_LOAD_STORE(ATOMIC_STORE8_I64) 165 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32) 166 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64) 167 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32) 168 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64) 169 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32) 170 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64) 171 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32) 172 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64) 173 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32) 174 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64) 175 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32) 176 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64) 177 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32) 178 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64) 179 WASM_LOAD_STORE(LOAD_SPLAT_v8x16) 180 return 0; 181 WASM_LOAD_STORE(LOAD16_S_I32) 182 WASM_LOAD_STORE(LOAD16_U_I32) 183 WASM_LOAD_STORE(LOAD16_S_I64) 184 WASM_LOAD_STORE(LOAD16_U_I64) 185 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32) 186 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64) 187 WASM_LOAD_STORE(STORE16_I32) 188 WASM_LOAD_STORE(STORE16_I64) 189 WASM_LOAD_STORE(ATOMIC_STORE16_I32) 190 WASM_LOAD_STORE(ATOMIC_STORE16_I64) 191 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32) 192 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64) 193 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32) 194 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64) 195 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32) 196 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64) 197 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32) 198 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64) 199 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32) 200 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64) 201 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32) 202 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64) 203 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32) 204 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64) 205 WASM_LOAD_STORE(LOAD_SPLAT_v16x8) 206 return 1; 207 WASM_LOAD_STORE(LOAD_I32) 208 WASM_LOAD_STORE(LOAD_F32) 209 WASM_LOAD_STORE(STORE_I32) 210 WASM_LOAD_STORE(STORE_F32) 211 WASM_LOAD_STORE(LOAD32_S_I64) 212 WASM_LOAD_STORE(LOAD32_U_I64) 213 WASM_LOAD_STORE(STORE32_I64) 214 WASM_LOAD_STORE(ATOMIC_LOAD_I32) 215 WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64) 216 WASM_LOAD_STORE(ATOMIC_STORE_I32) 217 WASM_LOAD_STORE(ATOMIC_STORE32_I64) 218 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32) 219 WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64) 220 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32) 221 WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64) 222 WASM_LOAD_STORE(ATOMIC_RMW_AND_I32) 223 WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64) 224 WASM_LOAD_STORE(ATOMIC_RMW_OR_I32) 225 WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64) 226 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32) 227 WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64) 228 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32) 229 WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64) 230 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32) 231 WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64) 232 WASM_LOAD_STORE(ATOMIC_NOTIFY) 233 WASM_LOAD_STORE(ATOMIC_WAIT_I32) 234 WASM_LOAD_STORE(LOAD_SPLAT_v32x4) 235 WASM_LOAD_STORE(LOAD_ZERO_v4i32) 236 return 2; 237 WASM_LOAD_STORE(LOAD_I64) 238 WASM_LOAD_STORE(LOAD_F64) 239 WASM_LOAD_STORE(STORE_I64) 240 WASM_LOAD_STORE(STORE_F64) 241 WASM_LOAD_STORE(ATOMIC_LOAD_I64) 242 WASM_LOAD_STORE(ATOMIC_STORE_I64) 243 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64) 244 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64) 245 WASM_LOAD_STORE(ATOMIC_RMW_AND_I64) 246 WASM_LOAD_STORE(ATOMIC_RMW_OR_I64) 247 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64) 248 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64) 249 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64) 250 WASM_LOAD_STORE(ATOMIC_WAIT_I64) 251 WASM_LOAD_STORE(LOAD_SPLAT_v64x2) 252 WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16) 253 WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16) 254 WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32) 255 WASM_LOAD_STORE(LOAD_EXTEND_U_v4i32) 256 WASM_LOAD_STORE(LOAD_EXTEND_S_v2i64) 257 WASM_LOAD_STORE(LOAD_EXTEND_U_v2i64) 258 WASM_LOAD_STORE(LOAD_ZERO_v2i64) 259 return 3; 260 WASM_LOAD_STORE(LOAD_V128) 261 WASM_LOAD_STORE(STORE_V128) 262 return 4; 263 default: 264 return -1; 265 } 266 #undef WASM_LOAD_STORE 267 } 268 269 inline unsigned GetDefaultP2Align(unsigned Opc) { 270 auto Align = GetDefaultP2AlignAny(Opc); 271 if (Align == -1U) { 272 llvm_unreachable("Only loads and stores have p2align values"); 273 } 274 return Align; 275 } 276 277 inline bool isArgument(unsigned Opc) { 278 switch (Opc) { 279 case WebAssembly::ARGUMENT_i32: 280 case WebAssembly::ARGUMENT_i32_S: 281 case WebAssembly::ARGUMENT_i64: 282 case WebAssembly::ARGUMENT_i64_S: 283 case WebAssembly::ARGUMENT_f32: 284 case WebAssembly::ARGUMENT_f32_S: 285 case WebAssembly::ARGUMENT_f64: 286 case WebAssembly::ARGUMENT_f64_S: 287 case WebAssembly::ARGUMENT_v16i8: 288 case WebAssembly::ARGUMENT_v16i8_S: 289 case WebAssembly::ARGUMENT_v8i16: 290 case WebAssembly::ARGUMENT_v8i16_S: 291 case WebAssembly::ARGUMENT_v4i32: 292 case WebAssembly::ARGUMENT_v4i32_S: 293 case WebAssembly::ARGUMENT_v2i64: 294 case WebAssembly::ARGUMENT_v2i64_S: 295 case WebAssembly::ARGUMENT_v4f32: 296 case WebAssembly::ARGUMENT_v4f32_S: 297 case WebAssembly::ARGUMENT_v2f64: 298 case WebAssembly::ARGUMENT_v2f64_S: 299 case WebAssembly::ARGUMENT_exnref: 300 case WebAssembly::ARGUMENT_exnref_S: 301 return true; 302 default: 303 return false; 304 } 305 } 306 307 inline bool isCopy(unsigned Opc) { 308 switch (Opc) { 309 case WebAssembly::COPY_I32: 310 case WebAssembly::COPY_I32_S: 311 case WebAssembly::COPY_I64: 312 case WebAssembly::COPY_I64_S: 313 case WebAssembly::COPY_F32: 314 case WebAssembly::COPY_F32_S: 315 case WebAssembly::COPY_F64: 316 case WebAssembly::COPY_F64_S: 317 case WebAssembly::COPY_V128: 318 case WebAssembly::COPY_V128_S: 319 case WebAssembly::COPY_EXNREF: 320 case WebAssembly::COPY_EXNREF_S: 321 return true; 322 default: 323 return false; 324 } 325 } 326 327 inline bool isTee(unsigned Opc) { 328 switch (Opc) { 329 case WebAssembly::TEE_I32: 330 case WebAssembly::TEE_I32_S: 331 case WebAssembly::TEE_I64: 332 case WebAssembly::TEE_I64_S: 333 case WebAssembly::TEE_F32: 334 case WebAssembly::TEE_F32_S: 335 case WebAssembly::TEE_F64: 336 case WebAssembly::TEE_F64_S: 337 case WebAssembly::TEE_V128: 338 case WebAssembly::TEE_V128_S: 339 case WebAssembly::TEE_EXNREF: 340 case WebAssembly::TEE_EXNREF_S: 341 return true; 342 default: 343 return false; 344 } 345 } 346 347 inline bool isCallDirect(unsigned Opc) { 348 switch (Opc) { 349 case WebAssembly::CALL: 350 case WebAssembly::CALL_S: 351 case WebAssembly::RET_CALL: 352 case WebAssembly::RET_CALL_S: 353 return true; 354 default: 355 return false; 356 } 357 } 358 359 inline bool isCallIndirect(unsigned Opc) { 360 switch (Opc) { 361 case WebAssembly::CALL_INDIRECT: 362 case WebAssembly::CALL_INDIRECT_S: 363 case WebAssembly::RET_CALL_INDIRECT: 364 case WebAssembly::RET_CALL_INDIRECT_S: 365 return true; 366 default: 367 return false; 368 } 369 } 370 371 inline bool isBrTable(const MachineInstr &MI) { 372 switch (MI.getOpcode()) { 373 case WebAssembly::BR_TABLE_I32: 374 case WebAssembly::BR_TABLE_I32_S: 375 case WebAssembly::BR_TABLE_I64: 376 case WebAssembly::BR_TABLE_I64_S: 377 return true; 378 default: 379 return false; 380 } 381 } 382 383 inline bool isMarker(unsigned Opc) { 384 switch (Opc) { 385 case WebAssembly::BLOCK: 386 case WebAssembly::BLOCK_S: 387 case WebAssembly::END_BLOCK: 388 case WebAssembly::END_BLOCK_S: 389 case WebAssembly::LOOP: 390 case WebAssembly::LOOP_S: 391 case WebAssembly::END_LOOP: 392 case WebAssembly::END_LOOP_S: 393 case WebAssembly::TRY: 394 case WebAssembly::TRY_S: 395 case WebAssembly::END_TRY: 396 case WebAssembly::END_TRY_S: 397 return true; 398 default: 399 return false; 400 } 401 } 402 403 } // end namespace WebAssembly 404 } // end namespace llvm 405 406 #endif 407