1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file provides WebAssembly-specific target descriptions. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 17 #include "../WebAssemblySubtarget.h" 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCInstrInfo; 28 class MCObjectTargetWriter; 29 class MVT; 30 class Triple; 31 32 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 33 34 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 35 36 std::unique_ptr<MCObjectTargetWriter> 37 createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten); 38 39 namespace WebAssembly { 40 enum OperandType { 41 /// Basic block label in a branch construct. 42 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 43 /// Local index. 44 OPERAND_LOCAL, 45 /// Global index. 46 OPERAND_GLOBAL, 47 /// 32-bit integer immediates. 48 OPERAND_I32IMM, 49 /// 64-bit integer immediates. 50 OPERAND_I64IMM, 51 /// 32-bit floating-point immediates. 52 OPERAND_F32IMM, 53 /// 64-bit floating-point immediates. 54 OPERAND_F64IMM, 55 /// 8-bit vector lane immediate 56 OPERAND_VEC_I8IMM, 57 /// 16-bit vector lane immediate 58 OPERAND_VEC_I16IMM, 59 /// 32-bit vector lane immediate 60 OPERAND_VEC_I32IMM, 61 /// 64-bit vector lane immediate 62 OPERAND_VEC_I64IMM, 63 /// 32-bit unsigned function indices. 64 OPERAND_FUNCTION32, 65 /// 32-bit unsigned memory offsets. 66 OPERAND_OFFSET32, 67 /// p2align immediate for load and store address alignment. 68 OPERAND_P2ALIGN, 69 /// signature immediate for block/loop. 70 OPERAND_SIGNATURE, 71 /// type signature immediate for call_indirect. 72 OPERAND_TYPEINDEX, 73 /// Event index. 74 OPERAND_EVENT, 75 /// A list of branch targets for br_list. 76 OPERAND_BRLIST, 77 }; 78 } // end namespace WebAssembly 79 80 namespace WebAssemblyII { 81 82 /// Target Operand Flag enum. 83 enum TOF { 84 MO_NO_FLAG = 0, 85 86 // On a symbol operand this indicates that the immediate is a wasm global 87 // index. The value of the wasm global will be set to the symbol address at 88 // runtime. This adds a level of indirection similar to the GOT on native 89 // platforms. 90 MO_GOT, 91 92 // On a symbol operand this indicates that the immediate is the symbol 93 // address relative the __memory_base wasm global. 94 // Only applicable to data symbols. 95 MO_MEMORY_BASE_REL, 96 97 // On a symbol operand this indicates that the immediate is the symbol 98 // address relative the __table_base wasm global. 99 // Only applicable to function symbols. 100 MO_TABLE_BASE_REL, 101 }; 102 103 } // end namespace WebAssemblyII 104 105 } // end namespace llvm 106 107 // Defines symbolic names for WebAssembly registers. This defines a mapping from 108 // register name to register number. 109 // 110 #define GET_REGINFO_ENUM 111 #include "WebAssemblyGenRegisterInfo.inc" 112 113 // Defines symbolic names for the WebAssembly instructions. 114 // 115 #define GET_INSTRINFO_ENUM 116 #include "WebAssemblyGenInstrInfo.inc" 117 118 namespace llvm { 119 namespace WebAssembly { 120 121 /// Used as immediate MachineOperands for block signatures 122 enum class BlockType : unsigned { 123 Invalid = 0x00, 124 Void = 0x40, 125 I32 = unsigned(wasm::ValType::I32), 126 I64 = unsigned(wasm::ValType::I64), 127 F32 = unsigned(wasm::ValType::F32), 128 F64 = unsigned(wasm::ValType::F64), 129 V128 = unsigned(wasm::ValType::V128), 130 Exnref = unsigned(wasm::ValType::EXNREF), 131 // Multivalue blocks (and other non-void blocks) are only emitted when the 132 // blocks will never be exited and are at the ends of functions (see 133 // WebAssemblyCFGStackify::fixEndsAtEndOfFunction). They also are never made 134 // to pop values off the stack, so the exact multivalue signature can always 135 // be inferred from the return type of the parent function in MCInstLower. 136 Multivalue = 0xffff, 137 }; 138 139 /// Instruction opcodes emitted via means other than CodeGen. 140 static const unsigned Nop = 0x01; 141 static const unsigned End = 0x0b; 142 143 wasm::ValType toValType(const MVT &Ty); 144 145 /// Return the default p2align value for a load or store with the given opcode. 146 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { 147 switch (Opc) { 148 case WebAssembly::LOAD8_S_I32: 149 case WebAssembly::LOAD8_S_I32_S: 150 case WebAssembly::LOAD8_U_I32: 151 case WebAssembly::LOAD8_U_I32_S: 152 case WebAssembly::LOAD8_S_I64: 153 case WebAssembly::LOAD8_S_I64_S: 154 case WebAssembly::LOAD8_U_I64: 155 case WebAssembly::LOAD8_U_I64_S: 156 case WebAssembly::ATOMIC_LOAD8_U_I32: 157 case WebAssembly::ATOMIC_LOAD8_U_I32_S: 158 case WebAssembly::ATOMIC_LOAD8_U_I64: 159 case WebAssembly::ATOMIC_LOAD8_U_I64_S: 160 case WebAssembly::STORE8_I32: 161 case WebAssembly::STORE8_I32_S: 162 case WebAssembly::STORE8_I64: 163 case WebAssembly::STORE8_I64_S: 164 case WebAssembly::ATOMIC_STORE8_I32: 165 case WebAssembly::ATOMIC_STORE8_I32_S: 166 case WebAssembly::ATOMIC_STORE8_I64: 167 case WebAssembly::ATOMIC_STORE8_I64_S: 168 case WebAssembly::ATOMIC_RMW8_U_ADD_I32: 169 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S: 170 case WebAssembly::ATOMIC_RMW8_U_ADD_I64: 171 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S: 172 case WebAssembly::ATOMIC_RMW8_U_SUB_I32: 173 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S: 174 case WebAssembly::ATOMIC_RMW8_U_SUB_I64: 175 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S: 176 case WebAssembly::ATOMIC_RMW8_U_AND_I32: 177 case WebAssembly::ATOMIC_RMW8_U_AND_I32_S: 178 case WebAssembly::ATOMIC_RMW8_U_AND_I64: 179 case WebAssembly::ATOMIC_RMW8_U_AND_I64_S: 180 case WebAssembly::ATOMIC_RMW8_U_OR_I32: 181 case WebAssembly::ATOMIC_RMW8_U_OR_I32_S: 182 case WebAssembly::ATOMIC_RMW8_U_OR_I64: 183 case WebAssembly::ATOMIC_RMW8_U_OR_I64_S: 184 case WebAssembly::ATOMIC_RMW8_U_XOR_I32: 185 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S: 186 case WebAssembly::ATOMIC_RMW8_U_XOR_I64: 187 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S: 188 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32: 189 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S: 190 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64: 191 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S: 192 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32: 193 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S: 194 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64: 195 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S: 196 case WebAssembly::LOAD_SPLAT_v8x16: 197 case WebAssembly::LOAD_SPLAT_v8x16_S: 198 return 0; 199 case WebAssembly::LOAD16_S_I32: 200 case WebAssembly::LOAD16_S_I32_S: 201 case WebAssembly::LOAD16_U_I32: 202 case WebAssembly::LOAD16_U_I32_S: 203 case WebAssembly::LOAD16_S_I64: 204 case WebAssembly::LOAD16_S_I64_S: 205 case WebAssembly::LOAD16_U_I64: 206 case WebAssembly::LOAD16_U_I64_S: 207 case WebAssembly::ATOMIC_LOAD16_U_I32: 208 case WebAssembly::ATOMIC_LOAD16_U_I32_S: 209 case WebAssembly::ATOMIC_LOAD16_U_I64: 210 case WebAssembly::ATOMIC_LOAD16_U_I64_S: 211 case WebAssembly::STORE16_I32: 212 case WebAssembly::STORE16_I32_S: 213 case WebAssembly::STORE16_I64: 214 case WebAssembly::STORE16_I64_S: 215 case WebAssembly::ATOMIC_STORE16_I32: 216 case WebAssembly::ATOMIC_STORE16_I32_S: 217 case WebAssembly::ATOMIC_STORE16_I64: 218 case WebAssembly::ATOMIC_STORE16_I64_S: 219 case WebAssembly::ATOMIC_RMW16_U_ADD_I32: 220 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S: 221 case WebAssembly::ATOMIC_RMW16_U_ADD_I64: 222 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S: 223 case WebAssembly::ATOMIC_RMW16_U_SUB_I32: 224 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S: 225 case WebAssembly::ATOMIC_RMW16_U_SUB_I64: 226 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S: 227 case WebAssembly::ATOMIC_RMW16_U_AND_I32: 228 case WebAssembly::ATOMIC_RMW16_U_AND_I32_S: 229 case WebAssembly::ATOMIC_RMW16_U_AND_I64: 230 case WebAssembly::ATOMIC_RMW16_U_AND_I64_S: 231 case WebAssembly::ATOMIC_RMW16_U_OR_I32: 232 case WebAssembly::ATOMIC_RMW16_U_OR_I32_S: 233 case WebAssembly::ATOMIC_RMW16_U_OR_I64: 234 case WebAssembly::ATOMIC_RMW16_U_OR_I64_S: 235 case WebAssembly::ATOMIC_RMW16_U_XOR_I32: 236 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S: 237 case WebAssembly::ATOMIC_RMW16_U_XOR_I64: 238 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S: 239 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32: 240 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S: 241 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64: 242 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S: 243 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32: 244 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S: 245 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64: 246 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S: 247 case WebAssembly::LOAD_SPLAT_v16x8: 248 case WebAssembly::LOAD_SPLAT_v16x8_S: 249 return 1; 250 case WebAssembly::LOAD_I32: 251 case WebAssembly::LOAD_I32_S: 252 case WebAssembly::LOAD_F32: 253 case WebAssembly::LOAD_F32_S: 254 case WebAssembly::STORE_I32: 255 case WebAssembly::STORE_I32_S: 256 case WebAssembly::STORE_F32: 257 case WebAssembly::STORE_F32_S: 258 case WebAssembly::LOAD32_S_I64: 259 case WebAssembly::LOAD32_S_I64_S: 260 case WebAssembly::LOAD32_U_I64: 261 case WebAssembly::LOAD32_U_I64_S: 262 case WebAssembly::STORE32_I64: 263 case WebAssembly::STORE32_I64_S: 264 case WebAssembly::ATOMIC_LOAD_I32: 265 case WebAssembly::ATOMIC_LOAD_I32_S: 266 case WebAssembly::ATOMIC_LOAD32_U_I64: 267 case WebAssembly::ATOMIC_LOAD32_U_I64_S: 268 case WebAssembly::ATOMIC_STORE_I32: 269 case WebAssembly::ATOMIC_STORE_I32_S: 270 case WebAssembly::ATOMIC_STORE32_I64: 271 case WebAssembly::ATOMIC_STORE32_I64_S: 272 case WebAssembly::ATOMIC_RMW_ADD_I32: 273 case WebAssembly::ATOMIC_RMW_ADD_I32_S: 274 case WebAssembly::ATOMIC_RMW32_U_ADD_I64: 275 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S: 276 case WebAssembly::ATOMIC_RMW_SUB_I32: 277 case WebAssembly::ATOMIC_RMW_SUB_I32_S: 278 case WebAssembly::ATOMIC_RMW32_U_SUB_I64: 279 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S: 280 case WebAssembly::ATOMIC_RMW_AND_I32: 281 case WebAssembly::ATOMIC_RMW_AND_I32_S: 282 case WebAssembly::ATOMIC_RMW32_U_AND_I64: 283 case WebAssembly::ATOMIC_RMW32_U_AND_I64_S: 284 case WebAssembly::ATOMIC_RMW_OR_I32: 285 case WebAssembly::ATOMIC_RMW_OR_I32_S: 286 case WebAssembly::ATOMIC_RMW32_U_OR_I64: 287 case WebAssembly::ATOMIC_RMW32_U_OR_I64_S: 288 case WebAssembly::ATOMIC_RMW_XOR_I32: 289 case WebAssembly::ATOMIC_RMW_XOR_I32_S: 290 case WebAssembly::ATOMIC_RMW32_U_XOR_I64: 291 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S: 292 case WebAssembly::ATOMIC_RMW_XCHG_I32: 293 case WebAssembly::ATOMIC_RMW_XCHG_I32_S: 294 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64: 295 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S: 296 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32: 297 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S: 298 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64: 299 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S: 300 case WebAssembly::ATOMIC_NOTIFY: 301 case WebAssembly::ATOMIC_NOTIFY_S: 302 case WebAssembly::ATOMIC_WAIT_I32: 303 case WebAssembly::ATOMIC_WAIT_I32_S: 304 case WebAssembly::LOAD_SPLAT_v32x4: 305 case WebAssembly::LOAD_SPLAT_v32x4_S: 306 return 2; 307 case WebAssembly::LOAD_I64: 308 case WebAssembly::LOAD_I64_S: 309 case WebAssembly::LOAD_F64: 310 case WebAssembly::LOAD_F64_S: 311 case WebAssembly::STORE_I64: 312 case WebAssembly::STORE_I64_S: 313 case WebAssembly::STORE_F64: 314 case WebAssembly::STORE_F64_S: 315 case WebAssembly::ATOMIC_LOAD_I64: 316 case WebAssembly::ATOMIC_LOAD_I64_S: 317 case WebAssembly::ATOMIC_STORE_I64: 318 case WebAssembly::ATOMIC_STORE_I64_S: 319 case WebAssembly::ATOMIC_RMW_ADD_I64: 320 case WebAssembly::ATOMIC_RMW_ADD_I64_S: 321 case WebAssembly::ATOMIC_RMW_SUB_I64: 322 case WebAssembly::ATOMIC_RMW_SUB_I64_S: 323 case WebAssembly::ATOMIC_RMW_AND_I64: 324 case WebAssembly::ATOMIC_RMW_AND_I64_S: 325 case WebAssembly::ATOMIC_RMW_OR_I64: 326 case WebAssembly::ATOMIC_RMW_OR_I64_S: 327 case WebAssembly::ATOMIC_RMW_XOR_I64: 328 case WebAssembly::ATOMIC_RMW_XOR_I64_S: 329 case WebAssembly::ATOMIC_RMW_XCHG_I64: 330 case WebAssembly::ATOMIC_RMW_XCHG_I64_S: 331 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64: 332 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S: 333 case WebAssembly::ATOMIC_WAIT_I64: 334 case WebAssembly::ATOMIC_WAIT_I64_S: 335 case WebAssembly::LOAD_SPLAT_v64x2: 336 case WebAssembly::LOAD_SPLAT_v64x2_S: 337 case WebAssembly::LOAD_EXTEND_S_v8i16: 338 case WebAssembly::LOAD_EXTEND_S_v8i16_S: 339 case WebAssembly::LOAD_EXTEND_U_v8i16: 340 case WebAssembly::LOAD_EXTEND_U_v8i16_S: 341 case WebAssembly::LOAD_EXTEND_S_v4i32: 342 case WebAssembly::LOAD_EXTEND_S_v4i32_S: 343 case WebAssembly::LOAD_EXTEND_U_v4i32: 344 case WebAssembly::LOAD_EXTEND_U_v4i32_S: 345 case WebAssembly::LOAD_EXTEND_S_v2i64: 346 case WebAssembly::LOAD_EXTEND_S_v2i64_S: 347 case WebAssembly::LOAD_EXTEND_U_v2i64: 348 case WebAssembly::LOAD_EXTEND_U_v2i64_S: 349 return 3; 350 case WebAssembly::LOAD_V128: 351 case WebAssembly::LOAD_V128_S: 352 case WebAssembly::STORE_V128: 353 case WebAssembly::STORE_V128_S: 354 return 4; 355 default: 356 return -1; 357 } 358 } 359 360 inline unsigned GetDefaultP2Align(unsigned Opc) { 361 auto Align = GetDefaultP2AlignAny(Opc); 362 if (Align == -1U) { 363 llvm_unreachable("Only loads and stores have p2align values"); 364 } 365 return Align; 366 } 367 368 inline bool isArgument(unsigned Opc) { 369 switch (Opc) { 370 case WebAssembly::ARGUMENT_i32: 371 case WebAssembly::ARGUMENT_i32_S: 372 case WebAssembly::ARGUMENT_i64: 373 case WebAssembly::ARGUMENT_i64_S: 374 case WebAssembly::ARGUMENT_f32: 375 case WebAssembly::ARGUMENT_f32_S: 376 case WebAssembly::ARGUMENT_f64: 377 case WebAssembly::ARGUMENT_f64_S: 378 case WebAssembly::ARGUMENT_v16i8: 379 case WebAssembly::ARGUMENT_v16i8_S: 380 case WebAssembly::ARGUMENT_v8i16: 381 case WebAssembly::ARGUMENT_v8i16_S: 382 case WebAssembly::ARGUMENT_v4i32: 383 case WebAssembly::ARGUMENT_v4i32_S: 384 case WebAssembly::ARGUMENT_v2i64: 385 case WebAssembly::ARGUMENT_v2i64_S: 386 case WebAssembly::ARGUMENT_v4f32: 387 case WebAssembly::ARGUMENT_v4f32_S: 388 case WebAssembly::ARGUMENT_v2f64: 389 case WebAssembly::ARGUMENT_v2f64_S: 390 case WebAssembly::ARGUMENT_exnref: 391 case WebAssembly::ARGUMENT_exnref_S: 392 return true; 393 default: 394 return false; 395 } 396 } 397 398 inline bool isCopy(unsigned Opc) { 399 switch (Opc) { 400 case WebAssembly::COPY_I32: 401 case WebAssembly::COPY_I32_S: 402 case WebAssembly::COPY_I64: 403 case WebAssembly::COPY_I64_S: 404 case WebAssembly::COPY_F32: 405 case WebAssembly::COPY_F32_S: 406 case WebAssembly::COPY_F64: 407 case WebAssembly::COPY_F64_S: 408 case WebAssembly::COPY_V128: 409 case WebAssembly::COPY_V128_S: 410 case WebAssembly::COPY_EXNREF: 411 case WebAssembly::COPY_EXNREF_S: 412 return true; 413 default: 414 return false; 415 } 416 } 417 418 inline bool isTee(unsigned Opc) { 419 switch (Opc) { 420 case WebAssembly::TEE_I32: 421 case WebAssembly::TEE_I32_S: 422 case WebAssembly::TEE_I64: 423 case WebAssembly::TEE_I64_S: 424 case WebAssembly::TEE_F32: 425 case WebAssembly::TEE_F32_S: 426 case WebAssembly::TEE_F64: 427 case WebAssembly::TEE_F64_S: 428 case WebAssembly::TEE_V128: 429 case WebAssembly::TEE_V128_S: 430 case WebAssembly::TEE_EXNREF: 431 case WebAssembly::TEE_EXNREF_S: 432 return true; 433 default: 434 return false; 435 } 436 } 437 438 inline bool isCallDirect(unsigned Opc) { 439 switch (Opc) { 440 case WebAssembly::CALL: 441 case WebAssembly::CALL_S: 442 case WebAssembly::RET_CALL: 443 case WebAssembly::RET_CALL_S: 444 return true; 445 default: 446 return false; 447 } 448 } 449 450 inline bool isCallIndirect(unsigned Opc) { 451 switch (Opc) { 452 case WebAssembly::CALL_INDIRECT: 453 case WebAssembly::CALL_INDIRECT_S: 454 case WebAssembly::RET_CALL_INDIRECT: 455 case WebAssembly::RET_CALL_INDIRECT_S: 456 return true; 457 default: 458 return false; 459 } 460 } 461 462 inline bool isBrTable(const MachineInstr &MI) { 463 switch (MI.getOpcode()) { 464 case WebAssembly::BR_TABLE_I32: 465 case WebAssembly::BR_TABLE_I32_S: 466 case WebAssembly::BR_TABLE_I64: 467 case WebAssembly::BR_TABLE_I64_S: 468 return true; 469 default: 470 return false; 471 } 472 } 473 474 inline bool isMarker(unsigned Opc) { 475 switch (Opc) { 476 case WebAssembly::BLOCK: 477 case WebAssembly::BLOCK_S: 478 case WebAssembly::END_BLOCK: 479 case WebAssembly::END_BLOCK_S: 480 case WebAssembly::LOOP: 481 case WebAssembly::LOOP_S: 482 case WebAssembly::END_LOOP: 483 case WebAssembly::END_LOOP_S: 484 case WebAssembly::TRY: 485 case WebAssembly::TRY_S: 486 case WebAssembly::END_TRY: 487 case WebAssembly::END_TRY_S: 488 return true; 489 default: 490 return false; 491 } 492 } 493 494 } // end namespace WebAssembly 495 } // end namespace llvm 496 497 #endif 498