1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file provides WebAssembly-specific target descriptions. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 17 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCContext; 28 class MCInstrInfo; 29 class MCObjectTargetWriter; 30 class MCSubtargetInfo; 31 class MVT; 32 class Target; 33 class Triple; 34 class raw_pwrite_stream; 35 36 Target &getTheWebAssemblyTarget32(); 37 Target &getTheWebAssemblyTarget64(); 38 39 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 40 41 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 42 43 std::unique_ptr<MCObjectTargetWriter> 44 createWebAssemblyWasmObjectWriter(bool Is64Bit); 45 46 namespace WebAssembly { 47 enum OperandType { 48 /// Basic block label in a branch construct. 49 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 50 /// Local index. 51 OPERAND_LOCAL, 52 /// Global index. 53 OPERAND_GLOBAL, 54 /// 32-bit integer immediates. 55 OPERAND_I32IMM, 56 /// 64-bit integer immediates. 57 OPERAND_I64IMM, 58 /// 32-bit floating-point immediates. 59 OPERAND_F32IMM, 60 /// 64-bit floating-point immediates. 61 OPERAND_F64IMM, 62 /// 8-bit vector lane immediate 63 OPERAND_VEC_I8IMM, 64 /// 16-bit vector lane immediate 65 OPERAND_VEC_I16IMM, 66 /// 32-bit vector lane immediate 67 OPERAND_VEC_I32IMM, 68 /// 64-bit vector lane immediate 69 OPERAND_VEC_I64IMM, 70 /// 32-bit unsigned function indices. 71 OPERAND_FUNCTION32, 72 /// 32-bit unsigned memory offsets. 73 OPERAND_OFFSET32, 74 /// p2align immediate for load and store address alignment. 75 OPERAND_P2ALIGN, 76 /// signature immediate for block/loop. 77 OPERAND_SIGNATURE, 78 /// type signature immediate for call_indirect. 79 OPERAND_TYPEINDEX, 80 /// Event index. 81 OPERAND_EVENT, 82 }; 83 } // end namespace WebAssembly 84 85 namespace WebAssemblyII { 86 enum { 87 // For variadic instructions, this flag indicates whether an operand 88 // in the variable_ops range is an immediate value. 89 VariableOpIsImmediate = (1 << 0), 90 // For immediate values in the variable_ops range, this flag indicates 91 // whether the value represents a control-flow label. 92 VariableOpImmediateIsLabel = (1 << 1) 93 }; 94 95 /// Target Operand Flag enum. 96 enum TOF { 97 MO_NO_FLAG = 0, 98 99 // Flags to indicate the type of the symbol being referenced 100 MO_SYMBOL_FUNCTION = 0x1, 101 MO_SYMBOL_GLOBAL = 0x2, 102 MO_SYMBOL_EVENT = 0x4, 103 MO_SYMBOL_MASK = 0x7, 104 }; 105 } // end namespace WebAssemblyII 106 107 } // end namespace llvm 108 109 // Defines symbolic names for WebAssembly registers. This defines a mapping from 110 // register name to register number. 111 // 112 #define GET_REGINFO_ENUM 113 #include "WebAssemblyGenRegisterInfo.inc" 114 115 // Defines symbolic names for the WebAssembly instructions. 116 // 117 #define GET_INSTRINFO_ENUM 118 #include "WebAssemblyGenInstrInfo.inc" 119 120 #define GET_SUBTARGETINFO_ENUM 121 #include "WebAssemblyGenSubtargetInfo.inc" 122 123 namespace llvm { 124 namespace WebAssembly { 125 126 /// Return the default p2align value for a load or store with the given opcode. 127 inline unsigned GetDefaultP2Align(unsigned Opcode) { 128 switch (Opcode) { 129 case WebAssembly::LOAD8_S_I32: 130 case WebAssembly::LOAD8_S_I32_S: 131 case WebAssembly::LOAD8_U_I32: 132 case WebAssembly::LOAD8_U_I32_S: 133 case WebAssembly::LOAD8_S_I64: 134 case WebAssembly::LOAD8_S_I64_S: 135 case WebAssembly::LOAD8_U_I64: 136 case WebAssembly::LOAD8_U_I64_S: 137 case WebAssembly::ATOMIC_LOAD8_U_I32: 138 case WebAssembly::ATOMIC_LOAD8_U_I32_S: 139 case WebAssembly::ATOMIC_LOAD8_U_I64: 140 case WebAssembly::ATOMIC_LOAD8_U_I64_S: 141 case WebAssembly::STORE8_I32: 142 case WebAssembly::STORE8_I32_S: 143 case WebAssembly::STORE8_I64: 144 case WebAssembly::STORE8_I64_S: 145 case WebAssembly::ATOMIC_STORE8_I32: 146 case WebAssembly::ATOMIC_STORE8_I32_S: 147 case WebAssembly::ATOMIC_STORE8_I64: 148 case WebAssembly::ATOMIC_STORE8_I64_S: 149 case WebAssembly::ATOMIC_RMW8_U_ADD_I32: 150 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S: 151 case WebAssembly::ATOMIC_RMW8_U_ADD_I64: 152 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S: 153 case WebAssembly::ATOMIC_RMW8_U_SUB_I32: 154 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S: 155 case WebAssembly::ATOMIC_RMW8_U_SUB_I64: 156 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S: 157 case WebAssembly::ATOMIC_RMW8_U_AND_I32: 158 case WebAssembly::ATOMIC_RMW8_U_AND_I32_S: 159 case WebAssembly::ATOMIC_RMW8_U_AND_I64: 160 case WebAssembly::ATOMIC_RMW8_U_AND_I64_S: 161 case WebAssembly::ATOMIC_RMW8_U_OR_I32: 162 case WebAssembly::ATOMIC_RMW8_U_OR_I32_S: 163 case WebAssembly::ATOMIC_RMW8_U_OR_I64: 164 case WebAssembly::ATOMIC_RMW8_U_OR_I64_S: 165 case WebAssembly::ATOMIC_RMW8_U_XOR_I32: 166 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S: 167 case WebAssembly::ATOMIC_RMW8_U_XOR_I64: 168 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S: 169 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32: 170 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S: 171 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64: 172 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S: 173 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32: 174 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S: 175 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64: 176 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S: 177 return 0; 178 case WebAssembly::LOAD16_S_I32: 179 case WebAssembly::LOAD16_S_I32_S: 180 case WebAssembly::LOAD16_U_I32: 181 case WebAssembly::LOAD16_U_I32_S: 182 case WebAssembly::LOAD16_S_I64: 183 case WebAssembly::LOAD16_S_I64_S: 184 case WebAssembly::LOAD16_U_I64: 185 case WebAssembly::LOAD16_U_I64_S: 186 case WebAssembly::ATOMIC_LOAD16_U_I32: 187 case WebAssembly::ATOMIC_LOAD16_U_I32_S: 188 case WebAssembly::ATOMIC_LOAD16_U_I64: 189 case WebAssembly::ATOMIC_LOAD16_U_I64_S: 190 case WebAssembly::STORE16_I32: 191 case WebAssembly::STORE16_I32_S: 192 case WebAssembly::STORE16_I64: 193 case WebAssembly::STORE16_I64_S: 194 case WebAssembly::ATOMIC_STORE16_I32: 195 case WebAssembly::ATOMIC_STORE16_I32_S: 196 case WebAssembly::ATOMIC_STORE16_I64: 197 case WebAssembly::ATOMIC_STORE16_I64_S: 198 case WebAssembly::ATOMIC_RMW16_U_ADD_I32: 199 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S: 200 case WebAssembly::ATOMIC_RMW16_U_ADD_I64: 201 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S: 202 case WebAssembly::ATOMIC_RMW16_U_SUB_I32: 203 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S: 204 case WebAssembly::ATOMIC_RMW16_U_SUB_I64: 205 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S: 206 case WebAssembly::ATOMIC_RMW16_U_AND_I32: 207 case WebAssembly::ATOMIC_RMW16_U_AND_I32_S: 208 case WebAssembly::ATOMIC_RMW16_U_AND_I64: 209 case WebAssembly::ATOMIC_RMW16_U_AND_I64_S: 210 case WebAssembly::ATOMIC_RMW16_U_OR_I32: 211 case WebAssembly::ATOMIC_RMW16_U_OR_I32_S: 212 case WebAssembly::ATOMIC_RMW16_U_OR_I64: 213 case WebAssembly::ATOMIC_RMW16_U_OR_I64_S: 214 case WebAssembly::ATOMIC_RMW16_U_XOR_I32: 215 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S: 216 case WebAssembly::ATOMIC_RMW16_U_XOR_I64: 217 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S: 218 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32: 219 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S: 220 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64: 221 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S: 222 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32: 223 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S: 224 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64: 225 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S: 226 return 1; 227 case WebAssembly::LOAD_I32: 228 case WebAssembly::LOAD_I32_S: 229 case WebAssembly::LOAD_F32: 230 case WebAssembly::LOAD_F32_S: 231 case WebAssembly::STORE_I32: 232 case WebAssembly::STORE_I32_S: 233 case WebAssembly::STORE_F32: 234 case WebAssembly::STORE_F32_S: 235 case WebAssembly::LOAD32_S_I64: 236 case WebAssembly::LOAD32_S_I64_S: 237 case WebAssembly::LOAD32_U_I64: 238 case WebAssembly::LOAD32_U_I64_S: 239 case WebAssembly::STORE32_I64: 240 case WebAssembly::STORE32_I64_S: 241 case WebAssembly::ATOMIC_LOAD_I32: 242 case WebAssembly::ATOMIC_LOAD_I32_S: 243 case WebAssembly::ATOMIC_LOAD32_U_I64: 244 case WebAssembly::ATOMIC_LOAD32_U_I64_S: 245 case WebAssembly::ATOMIC_STORE_I32: 246 case WebAssembly::ATOMIC_STORE_I32_S: 247 case WebAssembly::ATOMIC_STORE32_I64: 248 case WebAssembly::ATOMIC_STORE32_I64_S: 249 case WebAssembly::ATOMIC_RMW_ADD_I32: 250 case WebAssembly::ATOMIC_RMW_ADD_I32_S: 251 case WebAssembly::ATOMIC_RMW32_U_ADD_I64: 252 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S: 253 case WebAssembly::ATOMIC_RMW_SUB_I32: 254 case WebAssembly::ATOMIC_RMW_SUB_I32_S: 255 case WebAssembly::ATOMIC_RMW32_U_SUB_I64: 256 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S: 257 case WebAssembly::ATOMIC_RMW_AND_I32: 258 case WebAssembly::ATOMIC_RMW_AND_I32_S: 259 case WebAssembly::ATOMIC_RMW32_U_AND_I64: 260 case WebAssembly::ATOMIC_RMW32_U_AND_I64_S: 261 case WebAssembly::ATOMIC_RMW_OR_I32: 262 case WebAssembly::ATOMIC_RMW_OR_I32_S: 263 case WebAssembly::ATOMIC_RMW32_U_OR_I64: 264 case WebAssembly::ATOMIC_RMW32_U_OR_I64_S: 265 case WebAssembly::ATOMIC_RMW_XOR_I32: 266 case WebAssembly::ATOMIC_RMW_XOR_I32_S: 267 case WebAssembly::ATOMIC_RMW32_U_XOR_I64: 268 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S: 269 case WebAssembly::ATOMIC_RMW_XCHG_I32: 270 case WebAssembly::ATOMIC_RMW_XCHG_I32_S: 271 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64: 272 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S: 273 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32: 274 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S: 275 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64: 276 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S: 277 case WebAssembly::ATOMIC_NOTIFY: 278 case WebAssembly::ATOMIC_NOTIFY_S: 279 case WebAssembly::ATOMIC_WAIT_I32: 280 case WebAssembly::ATOMIC_WAIT_I32_S: 281 return 2; 282 case WebAssembly::LOAD_I64: 283 case WebAssembly::LOAD_I64_S: 284 case WebAssembly::LOAD_F64: 285 case WebAssembly::LOAD_F64_S: 286 case WebAssembly::STORE_I64: 287 case WebAssembly::STORE_I64_S: 288 case WebAssembly::STORE_F64: 289 case WebAssembly::STORE_F64_S: 290 case WebAssembly::ATOMIC_LOAD_I64: 291 case WebAssembly::ATOMIC_LOAD_I64_S: 292 case WebAssembly::ATOMIC_STORE_I64: 293 case WebAssembly::ATOMIC_STORE_I64_S: 294 case WebAssembly::ATOMIC_RMW_ADD_I64: 295 case WebAssembly::ATOMIC_RMW_ADD_I64_S: 296 case WebAssembly::ATOMIC_RMW_SUB_I64: 297 case WebAssembly::ATOMIC_RMW_SUB_I64_S: 298 case WebAssembly::ATOMIC_RMW_AND_I64: 299 case WebAssembly::ATOMIC_RMW_AND_I64_S: 300 case WebAssembly::ATOMIC_RMW_OR_I64: 301 case WebAssembly::ATOMIC_RMW_OR_I64_S: 302 case WebAssembly::ATOMIC_RMW_XOR_I64: 303 case WebAssembly::ATOMIC_RMW_XOR_I64_S: 304 case WebAssembly::ATOMIC_RMW_XCHG_I64: 305 case WebAssembly::ATOMIC_RMW_XCHG_I64_S: 306 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64: 307 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S: 308 case WebAssembly::ATOMIC_WAIT_I64: 309 case WebAssembly::ATOMIC_WAIT_I64_S: 310 return 3; 311 case WebAssembly::LOAD_v16i8: 312 case WebAssembly::LOAD_v16i8_S: 313 case WebAssembly::LOAD_v8i16: 314 case WebAssembly::LOAD_v8i16_S: 315 case WebAssembly::LOAD_v4i32: 316 case WebAssembly::LOAD_v4i32_S: 317 case WebAssembly::LOAD_v2i64: 318 case WebAssembly::LOAD_v2i64_S: 319 case WebAssembly::LOAD_v4f32: 320 case WebAssembly::LOAD_v4f32_S: 321 case WebAssembly::LOAD_v2f64: 322 case WebAssembly::LOAD_v2f64_S: 323 case WebAssembly::STORE_v16i8: 324 case WebAssembly::STORE_v16i8_S: 325 case WebAssembly::STORE_v8i16: 326 case WebAssembly::STORE_v8i16_S: 327 case WebAssembly::STORE_v4i32: 328 case WebAssembly::STORE_v4i32_S: 329 case WebAssembly::STORE_v2i64: 330 case WebAssembly::STORE_v2i64_S: 331 case WebAssembly::STORE_v4f32: 332 case WebAssembly::STORE_v4f32_S: 333 case WebAssembly::STORE_v2f64: 334 case WebAssembly::STORE_v2f64_S: 335 return 4; 336 default: 337 llvm_unreachable("Only loads and stores have p2align values"); 338 } 339 } 340 341 /// The operand number of the load or store address in load/store instructions. 342 static const unsigned LoadAddressOperandNo = 3; 343 static const unsigned StoreAddressOperandNo = 2; 344 345 /// The operand number of the load or store p2align in load/store instructions. 346 static const unsigned LoadP2AlignOperandNo = 1; 347 static const unsigned StoreP2AlignOperandNo = 0; 348 349 /// This is used to indicate block signatures. 350 enum class ExprType : unsigned { 351 Void = 0x40, 352 I32 = 0x7F, 353 I64 = 0x7E, 354 F32 = 0x7D, 355 F64 = 0x7C, 356 V128 = 0x7B, 357 ExceptRef = 0x68 358 }; 359 360 /// Instruction opcodes emitted via means other than CodeGen. 361 static const unsigned Nop = 0x01; 362 static const unsigned End = 0x0b; 363 364 wasm::ValType toValType(const MVT &Ty); 365 366 } // end namespace WebAssembly 367 } // end namespace llvm 368 369 #endif 370