1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file provides WebAssembly-specific target descriptions. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 17 #include "../WebAssemblySubtarget.h" 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCInstrInfo; 28 class MCObjectTargetWriter; 29 class MVT; 30 class Triple; 31 32 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 33 34 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 35 36 std::unique_ptr<MCObjectTargetWriter> 37 createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten); 38 39 namespace WebAssembly { 40 enum OperandType { 41 /// Basic block label in a branch construct. 42 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 43 /// Local index. 44 OPERAND_LOCAL, 45 /// Global index. 46 OPERAND_GLOBAL, 47 /// 32-bit integer immediates. 48 OPERAND_I32IMM, 49 /// 64-bit integer immediates. 50 OPERAND_I64IMM, 51 /// 32-bit floating-point immediates. 52 OPERAND_F32IMM, 53 /// 64-bit floating-point immediates. 54 OPERAND_F64IMM, 55 /// 8-bit vector lane immediate 56 OPERAND_VEC_I8IMM, 57 /// 16-bit vector lane immediate 58 OPERAND_VEC_I16IMM, 59 /// 32-bit vector lane immediate 60 OPERAND_VEC_I32IMM, 61 /// 64-bit vector lane immediate 62 OPERAND_VEC_I64IMM, 63 /// 32-bit unsigned function indices. 64 OPERAND_FUNCTION32, 65 /// 32-bit unsigned memory offsets. 66 OPERAND_OFFSET32, 67 /// 64-bit unsigned memory offsets. 68 OPERAND_OFFSET64, 69 /// p2align immediate for load and store address alignment. 70 OPERAND_P2ALIGN, 71 /// signature immediate for block/loop. 72 OPERAND_SIGNATURE, 73 /// type signature immediate for call_indirect. 74 OPERAND_TYPEINDEX, 75 /// Event index. 76 OPERAND_EVENT, 77 /// A list of branch targets for br_list. 78 OPERAND_BRLIST, 79 /// 32-bit unsigned table number. 80 OPERAND_TABLE, 81 /// heap type immediate for ref.null. 82 OPERAND_HEAPTYPE, 83 }; 84 } // end namespace WebAssembly 85 86 namespace WebAssemblyII { 87 88 /// Target Operand Flag enum. 89 enum TOF { 90 MO_NO_FLAG = 0, 91 92 // On a symbol operand this indicates that the immediate is a wasm global 93 // index. The value of the wasm global will be set to the symbol address at 94 // runtime. This adds a level of indirection similar to the GOT on native 95 // platforms. 96 MO_GOT, 97 98 // On a symbol operand this indicates that the immediate is the symbol 99 // address relative the __memory_base wasm global. 100 // Only applicable to data symbols. 101 MO_MEMORY_BASE_REL, 102 103 // On a symbol operand this indicates that the immediate is the symbol 104 // address relative the __tls_base wasm global. 105 // Only applicable to data symbols. 106 MO_TLS_BASE_REL, 107 108 // On a symbol operand this indicates that the immediate is the symbol 109 // address relative the __table_base wasm global. 110 // Only applicable to function symbols. 111 MO_TABLE_BASE_REL, 112 }; 113 114 } // end namespace WebAssemblyII 115 116 } // end namespace llvm 117 118 // Defines symbolic names for WebAssembly registers. This defines a mapping from 119 // register name to register number. 120 // 121 #define GET_REGINFO_ENUM 122 #include "WebAssemblyGenRegisterInfo.inc" 123 124 // Defines symbolic names for the WebAssembly instructions. 125 // 126 #define GET_INSTRINFO_ENUM 127 #include "WebAssemblyGenInstrInfo.inc" 128 129 namespace llvm { 130 namespace WebAssembly { 131 132 /// Used as immediate MachineOperands for block signatures 133 enum class BlockType : unsigned { 134 Invalid = 0x00, 135 Void = 0x40, 136 I32 = unsigned(wasm::ValType::I32), 137 I64 = unsigned(wasm::ValType::I64), 138 F32 = unsigned(wasm::ValType::F32), 139 F64 = unsigned(wasm::ValType::F64), 140 V128 = unsigned(wasm::ValType::V128), 141 Exnref = unsigned(wasm::ValType::EXNREF), 142 // Multivalue blocks (and other non-void blocks) are only emitted when the 143 // blocks will never be exited and are at the ends of functions (see 144 // WebAssemblyCFGStackify::fixEndsAtEndOfFunction). They also are never made 145 // to pop values off the stack, so the exact multivalue signature can always 146 // be inferred from the return type of the parent function in MCInstLower. 147 Multivalue = 0xffff, 148 }; 149 150 /// Used as immediate MachineOperands for heap types, e.g. for ref.null. 151 enum class HeapType : unsigned { 152 Invalid = 0x00, 153 Externref = unsigned(wasm::ValType::EXTERNREF), 154 Funcref = unsigned(wasm::ValType::FUNCREF), 155 }; 156 157 /// Instruction opcodes emitted via means other than CodeGen. 158 static const unsigned Nop = 0x01; 159 static const unsigned End = 0x0b; 160 161 wasm::ValType toValType(const MVT &Ty); 162 163 /// Return the default p2align value for a load or store with the given opcode. 164 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { 165 switch (Opc) { 166 #define WASM_LOAD_STORE(NAME) \ 167 case WebAssembly::NAME##_A32: \ 168 case WebAssembly::NAME##_A64: \ 169 case WebAssembly::NAME##_A32_S: \ 170 case WebAssembly::NAME##_A64_S: 171 WASM_LOAD_STORE(LOAD8_S_I32) 172 WASM_LOAD_STORE(LOAD8_U_I32) 173 WASM_LOAD_STORE(LOAD8_S_I64) 174 WASM_LOAD_STORE(LOAD8_U_I64) 175 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32) 176 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64) 177 WASM_LOAD_STORE(STORE8_I32) 178 WASM_LOAD_STORE(STORE8_I64) 179 WASM_LOAD_STORE(ATOMIC_STORE8_I32) 180 WASM_LOAD_STORE(ATOMIC_STORE8_I64) 181 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32) 182 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64) 183 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32) 184 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64) 185 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32) 186 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64) 187 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32) 188 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64) 189 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32) 190 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64) 191 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32) 192 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64) 193 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32) 194 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64) 195 WASM_LOAD_STORE(LOAD_SPLAT_v8x16) 196 WASM_LOAD_STORE(LOAD_LANE_v16i8) 197 WASM_LOAD_STORE(STORE_LANE_v16i8) 198 return 0; 199 WASM_LOAD_STORE(LOAD16_S_I32) 200 WASM_LOAD_STORE(LOAD16_U_I32) 201 WASM_LOAD_STORE(LOAD16_S_I64) 202 WASM_LOAD_STORE(LOAD16_U_I64) 203 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32) 204 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64) 205 WASM_LOAD_STORE(STORE16_I32) 206 WASM_LOAD_STORE(STORE16_I64) 207 WASM_LOAD_STORE(ATOMIC_STORE16_I32) 208 WASM_LOAD_STORE(ATOMIC_STORE16_I64) 209 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32) 210 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64) 211 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32) 212 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64) 213 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32) 214 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64) 215 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32) 216 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64) 217 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32) 218 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64) 219 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32) 220 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64) 221 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32) 222 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64) 223 WASM_LOAD_STORE(LOAD_SPLAT_v16x8) 224 WASM_LOAD_STORE(LOAD_LANE_v8i16) 225 WASM_LOAD_STORE(STORE_LANE_v8i16) 226 return 1; 227 WASM_LOAD_STORE(LOAD_I32) 228 WASM_LOAD_STORE(LOAD_F32) 229 WASM_LOAD_STORE(STORE_I32) 230 WASM_LOAD_STORE(STORE_F32) 231 WASM_LOAD_STORE(LOAD32_S_I64) 232 WASM_LOAD_STORE(LOAD32_U_I64) 233 WASM_LOAD_STORE(STORE32_I64) 234 WASM_LOAD_STORE(ATOMIC_LOAD_I32) 235 WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64) 236 WASM_LOAD_STORE(ATOMIC_STORE_I32) 237 WASM_LOAD_STORE(ATOMIC_STORE32_I64) 238 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32) 239 WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64) 240 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32) 241 WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64) 242 WASM_LOAD_STORE(ATOMIC_RMW_AND_I32) 243 WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64) 244 WASM_LOAD_STORE(ATOMIC_RMW_OR_I32) 245 WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64) 246 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32) 247 WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64) 248 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32) 249 WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64) 250 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32) 251 WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64) 252 WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY) 253 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32) 254 WASM_LOAD_STORE(LOAD_SPLAT_v32x4) 255 WASM_LOAD_STORE(LOAD_ZERO_v4i32) 256 WASM_LOAD_STORE(LOAD_LANE_v4i32) 257 WASM_LOAD_STORE(STORE_LANE_v4i32) 258 return 2; 259 WASM_LOAD_STORE(LOAD_I64) 260 WASM_LOAD_STORE(LOAD_F64) 261 WASM_LOAD_STORE(STORE_I64) 262 WASM_LOAD_STORE(STORE_F64) 263 WASM_LOAD_STORE(ATOMIC_LOAD_I64) 264 WASM_LOAD_STORE(ATOMIC_STORE_I64) 265 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64) 266 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64) 267 WASM_LOAD_STORE(ATOMIC_RMW_AND_I64) 268 WASM_LOAD_STORE(ATOMIC_RMW_OR_I64) 269 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64) 270 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64) 271 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64) 272 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64) 273 WASM_LOAD_STORE(LOAD_SPLAT_v64x2) 274 WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16) 275 WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16) 276 WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32) 277 WASM_LOAD_STORE(LOAD_EXTEND_U_v4i32) 278 WASM_LOAD_STORE(LOAD_EXTEND_S_v2i64) 279 WASM_LOAD_STORE(LOAD_EXTEND_U_v2i64) 280 WASM_LOAD_STORE(LOAD_ZERO_v2i64) 281 WASM_LOAD_STORE(LOAD_LANE_v2i64) 282 WASM_LOAD_STORE(STORE_LANE_v2i64) 283 return 3; 284 WASM_LOAD_STORE(LOAD_V128) 285 WASM_LOAD_STORE(STORE_V128) 286 return 4; 287 default: 288 return -1; 289 } 290 #undef WASM_LOAD_STORE 291 } 292 293 inline unsigned GetDefaultP2Align(unsigned Opc) { 294 auto Align = GetDefaultP2AlignAny(Opc); 295 if (Align == -1U) { 296 llvm_unreachable("Only loads and stores have p2align values"); 297 } 298 return Align; 299 } 300 301 inline bool isArgument(unsigned Opc) { 302 switch (Opc) { 303 case WebAssembly::ARGUMENT_i32: 304 case WebAssembly::ARGUMENT_i32_S: 305 case WebAssembly::ARGUMENT_i64: 306 case WebAssembly::ARGUMENT_i64_S: 307 case WebAssembly::ARGUMENT_f32: 308 case WebAssembly::ARGUMENT_f32_S: 309 case WebAssembly::ARGUMENT_f64: 310 case WebAssembly::ARGUMENT_f64_S: 311 case WebAssembly::ARGUMENT_v16i8: 312 case WebAssembly::ARGUMENT_v16i8_S: 313 case WebAssembly::ARGUMENT_v8i16: 314 case WebAssembly::ARGUMENT_v8i16_S: 315 case WebAssembly::ARGUMENT_v4i32: 316 case WebAssembly::ARGUMENT_v4i32_S: 317 case WebAssembly::ARGUMENT_v2i64: 318 case WebAssembly::ARGUMENT_v2i64_S: 319 case WebAssembly::ARGUMENT_v4f32: 320 case WebAssembly::ARGUMENT_v4f32_S: 321 case WebAssembly::ARGUMENT_v2f64: 322 case WebAssembly::ARGUMENT_v2f64_S: 323 case WebAssembly::ARGUMENT_exnref: 324 case WebAssembly::ARGUMENT_exnref_S: 325 return true; 326 default: 327 return false; 328 } 329 } 330 331 inline bool isCopy(unsigned Opc) { 332 switch (Opc) { 333 case WebAssembly::COPY_I32: 334 case WebAssembly::COPY_I32_S: 335 case WebAssembly::COPY_I64: 336 case WebAssembly::COPY_I64_S: 337 case WebAssembly::COPY_F32: 338 case WebAssembly::COPY_F32_S: 339 case WebAssembly::COPY_F64: 340 case WebAssembly::COPY_F64_S: 341 case WebAssembly::COPY_V128: 342 case WebAssembly::COPY_V128_S: 343 case WebAssembly::COPY_EXNREF: 344 case WebAssembly::COPY_EXNREF_S: 345 return true; 346 default: 347 return false; 348 } 349 } 350 351 inline bool isTee(unsigned Opc) { 352 switch (Opc) { 353 case WebAssembly::TEE_I32: 354 case WebAssembly::TEE_I32_S: 355 case WebAssembly::TEE_I64: 356 case WebAssembly::TEE_I64_S: 357 case WebAssembly::TEE_F32: 358 case WebAssembly::TEE_F32_S: 359 case WebAssembly::TEE_F64: 360 case WebAssembly::TEE_F64_S: 361 case WebAssembly::TEE_V128: 362 case WebAssembly::TEE_V128_S: 363 case WebAssembly::TEE_EXNREF: 364 case WebAssembly::TEE_EXNREF_S: 365 return true; 366 default: 367 return false; 368 } 369 } 370 371 inline bool isCallDirect(unsigned Opc) { 372 switch (Opc) { 373 case WebAssembly::CALL: 374 case WebAssembly::CALL_S: 375 case WebAssembly::RET_CALL: 376 case WebAssembly::RET_CALL_S: 377 return true; 378 default: 379 return false; 380 } 381 } 382 383 inline bool isCallIndirect(unsigned Opc) { 384 switch (Opc) { 385 case WebAssembly::CALL_INDIRECT: 386 case WebAssembly::CALL_INDIRECT_S: 387 case WebAssembly::RET_CALL_INDIRECT: 388 case WebAssembly::RET_CALL_INDIRECT_S: 389 return true; 390 default: 391 return false; 392 } 393 } 394 395 inline bool isBrTable(const MachineInstr &MI) { 396 switch (MI.getOpcode()) { 397 case WebAssembly::BR_TABLE_I32: 398 case WebAssembly::BR_TABLE_I32_S: 399 case WebAssembly::BR_TABLE_I64: 400 case WebAssembly::BR_TABLE_I64_S: 401 return true; 402 default: 403 return false; 404 } 405 } 406 407 inline bool isMarker(unsigned Opc) { 408 switch (Opc) { 409 case WebAssembly::BLOCK: 410 case WebAssembly::BLOCK_S: 411 case WebAssembly::END_BLOCK: 412 case WebAssembly::END_BLOCK_S: 413 case WebAssembly::LOOP: 414 case WebAssembly::LOOP_S: 415 case WebAssembly::END_LOOP: 416 case WebAssembly::END_LOOP_S: 417 case WebAssembly::TRY: 418 case WebAssembly::TRY_S: 419 case WebAssembly::END_TRY: 420 case WebAssembly::END_TRY_S: 421 return true; 422 default: 423 return false; 424 } 425 } 426 427 } // end namespace WebAssembly 428 } // end namespace llvm 429 430 #endif 431