1 //===-- VETargetMachine.cpp - Define TargetMachine for VE -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "VETargetMachine.h"
13 #include "TargetInfo/VETargetInfo.h"
14 #include "VE.h"
15 #include "VETargetTransformInfo.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "ve"
25 
26 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() {
27   // Register the target.
28   RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
29 }
30 
31 static std::string computeDataLayout(const Triple &T) {
32   // Aurora VE is little endian
33   std::string Ret = "e";
34 
35   // Use ELF mangling
36   Ret += "-m:e";
37 
38   // Alignments for 64 bit integers.
39   Ret += "-i64:64";
40 
41   // VE supports 32 bit and 64 bits integer on registers
42   Ret += "-n32:64";
43 
44   // Stack alignment is 128 bits
45   Ret += "-S128";
46 
47   // Vector alignments are 64 bits
48   // Need to define all of them.  Otherwise, each alignment becomes
49   // the size of each data by default.
50   Ret += "-v64:64:64"; // for v2f32
51   Ret += "-v128:64:64";
52   Ret += "-v256:64:64";
53   Ret += "-v512:64:64";
54   Ret += "-v1024:64:64";
55   Ret += "-v2048:64:64";
56   Ret += "-v4096:64:64";
57   Ret += "-v8192:64:64";
58   Ret += "-v16384:64:64"; // for v256f64
59 
60   return Ret;
61 }
62 
63 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
64   if (!RM.hasValue())
65     return Reloc::Static;
66   return *RM;
67 }
68 
69 class VEELFTargetObjectFile : public TargetLoweringObjectFileELF {
70   void Initialize(MCContext &Ctx, const TargetMachine &TM) override {
71     TargetLoweringObjectFileELF::Initialize(Ctx, TM);
72     InitializeELF(TM.Options.UseInitArray);
73   }
74 };
75 
76 static std::unique_ptr<TargetLoweringObjectFile> createTLOF() {
77   return std::make_unique<VEELFTargetObjectFile>();
78 }
79 
80 /// Create an Aurora VE architecture model
81 VETargetMachine::VETargetMachine(const Target &T, const Triple &TT,
82                                  StringRef CPU, StringRef FS,
83                                  const TargetOptions &Options,
84                                  Optional<Reloc::Model> RM,
85                                  Optional<CodeModel::Model> CM,
86                                  CodeGenOpt::Level OL, bool JIT)
87     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
88                         getEffectiveRelocModel(RM),
89                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
90       TLOF(createTLOF()),
91       Subtarget(TT, std::string(CPU), std::string(FS), *this) {
92   initAsmInfo();
93 }
94 
95 VETargetMachine::~VETargetMachine() {}
96 
97 TargetTransformInfo VETargetMachine::getTargetTransformInfo(const Function &F) {
98   return TargetTransformInfo(VETTIImpl(this, F));
99 }
100 
101 namespace {
102 /// VE Code Generator Pass Configuration Options.
103 class VEPassConfig : public TargetPassConfig {
104 public:
105   VEPassConfig(VETargetMachine &TM, PassManagerBase &PM)
106       : TargetPassConfig(TM, PM) {}
107 
108   VETargetMachine &getVETargetMachine() const {
109     return getTM<VETargetMachine>();
110   }
111 
112   void addIRPasses() override;
113   bool addInstSelector() override;
114   void addPreEmitPass() override;
115 };
116 } // namespace
117 
118 TargetPassConfig *VETargetMachine::createPassConfig(PassManagerBase &PM) {
119   return new VEPassConfig(*this, PM);
120 }
121 
122 void VEPassConfig::addIRPasses() {
123   // VE requires atomic expand pass.
124   addPass(createAtomicExpandPass());
125   TargetPassConfig::addIRPasses();
126 }
127 
128 bool VEPassConfig::addInstSelector() {
129   addPass(createVEISelDag(getVETargetMachine()));
130   return false;
131 }
132 
133 void VEPassConfig::addPreEmitPass() {
134   // LVLGen should be called after scheduling and register allocation
135   addPass(createLVLGenPass());
136 }
137