1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the VE implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "VEInstrInfo.h" 14 #include "VE.h" 15 #include "VEMachineFunctionInfo.h" 16 #include "VESubtarget.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineMemOperand.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 28 #define DEBUG_TYPE "ve-instr-info" 29 30 using namespace llvm; 31 32 #define GET_INSTRINFO_CTOR_DTOR 33 #include "VEGenInstrInfo.inc" 34 35 // Pin the vtable to this file. 36 void VEInstrInfo::anchor() {} 37 38 VEInstrInfo::VEInstrInfo(VESubtarget &ST) 39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} 40 41 static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); } 42 43 static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) { 44 switch (CC) { 45 case VECC::CC_IG: 46 return VECC::CC_ILE; 47 case VECC::CC_IL: 48 return VECC::CC_IGE; 49 case VECC::CC_INE: 50 return VECC::CC_IEQ; 51 case VECC::CC_IEQ: 52 return VECC::CC_INE; 53 case VECC::CC_IGE: 54 return VECC::CC_IL; 55 case VECC::CC_ILE: 56 return VECC::CC_IG; 57 case VECC::CC_AF: 58 return VECC::CC_AT; 59 case VECC::CC_G: 60 return VECC::CC_LENAN; 61 case VECC::CC_L: 62 return VECC::CC_GENAN; 63 case VECC::CC_NE: 64 return VECC::CC_EQNAN; 65 case VECC::CC_EQ: 66 return VECC::CC_NENAN; 67 case VECC::CC_GE: 68 return VECC::CC_LNAN; 69 case VECC::CC_LE: 70 return VECC::CC_GNAN; 71 case VECC::CC_NUM: 72 return VECC::CC_NAN; 73 case VECC::CC_NAN: 74 return VECC::CC_NUM; 75 case VECC::CC_GNAN: 76 return VECC::CC_LE; 77 case VECC::CC_LNAN: 78 return VECC::CC_GE; 79 case VECC::CC_NENAN: 80 return VECC::CC_EQ; 81 case VECC::CC_EQNAN: 82 return VECC::CC_NE; 83 case VECC::CC_GENAN: 84 return VECC::CC_L; 85 case VECC::CC_LENAN: 86 return VECC::CC_G; 87 case VECC::CC_AT: 88 return VECC::CC_AF; 89 case VECC::UNKNOWN: 90 return VECC::UNKNOWN; 91 } 92 llvm_unreachable("Invalid cond code"); 93 } 94 95 // Treat br.l [BRCF AT] as unconditional branch 96 static bool isUncondBranchOpcode(int Opc) { 97 return Opc == VE::BRCFLa || Opc == VE::BRCFWa || 98 Opc == VE::BRCFLa_nt || Opc == VE::BRCFWa_nt || 99 Opc == VE::BRCFLa_t || Opc == VE::BRCFWa_t || 100 Opc == VE::BRCFDa || Opc == VE::BRCFSa || 101 Opc == VE::BRCFDa_nt || Opc == VE::BRCFSa_nt || 102 Opc == VE::BRCFDa_t || Opc == VE::BRCFSa_t; 103 } 104 105 static bool isCondBranchOpcode(int Opc) { 106 return Opc == VE::BRCFLrr || Opc == VE::BRCFLir || 107 Opc == VE::BRCFLrr_nt || Opc == VE::BRCFLir_nt || 108 Opc == VE::BRCFLrr_t || Opc == VE::BRCFLir_t || 109 Opc == VE::BRCFWrr || Opc == VE::BRCFWir || 110 Opc == VE::BRCFWrr_nt || Opc == VE::BRCFWir_nt || 111 Opc == VE::BRCFWrr_t || Opc == VE::BRCFWir_t || 112 Opc == VE::BRCFDrr || Opc == VE::BRCFDir || 113 Opc == VE::BRCFDrr_nt || Opc == VE::BRCFDir_nt || 114 Opc == VE::BRCFDrr_t || Opc == VE::BRCFDir_t || 115 Opc == VE::BRCFSrr || Opc == VE::BRCFSir || 116 Opc == VE::BRCFSrr_nt || Opc == VE::BRCFSir_nt || 117 Opc == VE::BRCFSrr_t || Opc == VE::BRCFSir_t; 118 } 119 120 static bool isIndirectBranchOpcode(int Opc) { 121 return Opc == VE::BCFLari || Opc == VE::BCFLari || 122 Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt || 123 Opc == VE::BCFLari_t || Opc == VE::BCFLari_t || 124 Opc == VE::BCFLari || Opc == VE::BCFLari || 125 Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt || 126 Opc == VE::BCFLari_t || Opc == VE::BCFLari_t; 127 } 128 129 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, 130 SmallVectorImpl<MachineOperand> &Cond) { 131 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); 132 Cond.push_back(LastInst->getOperand(1)); 133 Cond.push_back(LastInst->getOperand(2)); 134 Target = LastInst->getOperand(3).getMBB(); 135 } 136 137 bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 138 MachineBasicBlock *&FBB, 139 SmallVectorImpl<MachineOperand> &Cond, 140 bool AllowModify) const { 141 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 142 if (I == MBB.end()) 143 return false; 144 145 if (!isUnpredicatedTerminator(*I)) 146 return false; 147 148 // Get the last instruction in the block. 149 MachineInstr *LastInst = &*I; 150 unsigned LastOpc = LastInst->getOpcode(); 151 152 // If there is only one terminator instruction, process it. 153 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 154 if (isUncondBranchOpcode(LastOpc)) { 155 TBB = LastInst->getOperand(0).getMBB(); 156 return false; 157 } 158 if (isCondBranchOpcode(LastOpc)) { 159 // Block ends with fall-through condbranch. 160 parseCondBranch(LastInst, TBB, Cond); 161 return false; 162 } 163 return true; // Can't handle indirect branch. 164 } 165 166 // Get the instruction before it if it is a terminator. 167 MachineInstr *SecondLastInst = &*I; 168 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 169 170 // If AllowModify is true and the block ends with two or more unconditional 171 // branches, delete all but the first unconditional branch. 172 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 173 while (isUncondBranchOpcode(SecondLastOpc)) { 174 LastInst->eraseFromParent(); 175 LastInst = SecondLastInst; 176 LastOpc = LastInst->getOpcode(); 177 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 178 // Return now the only terminator is an unconditional branch. 179 TBB = LastInst->getOperand(0).getMBB(); 180 return false; 181 } 182 SecondLastInst = &*I; 183 SecondLastOpc = SecondLastInst->getOpcode(); 184 } 185 } 186 187 // If there are three terminators, we don't know what sort of block this is. 188 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 189 return true; 190 191 // If the block ends with a B and a Bcc, handle it. 192 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 193 parseCondBranch(SecondLastInst, TBB, Cond); 194 FBB = LastInst->getOperand(0).getMBB(); 195 return false; 196 } 197 198 // If the block ends with two unconditional branches, handle it. The second 199 // one is not executed. 200 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 201 TBB = SecondLastInst->getOperand(0).getMBB(); 202 return false; 203 } 204 205 // ...likewise if it ends with an indirect branch followed by an unconditional 206 // branch. 207 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 208 I = LastInst; 209 if (AllowModify) 210 I->eraseFromParent(); 211 return true; 212 } 213 214 // Otherwise, can't handle this. 215 return true; 216 } 217 218 unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, 219 MachineBasicBlock *TBB, 220 MachineBasicBlock *FBB, 221 ArrayRef<MachineOperand> Cond, 222 const DebugLoc &DL, int *BytesAdded) const { 223 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 224 assert((Cond.size() == 3 || Cond.size() == 0) && 225 "VE branch conditions should have three component!"); 226 assert(!BytesAdded && "code size not handled"); 227 if (Cond.empty()) { 228 // Uncondition branch 229 assert(!FBB && "Unconditional branch with multiple successors!"); 230 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 231 .addMBB(TBB); 232 return 1; 233 } 234 235 // Conditional branch 236 // (BRCFir CC sy sz addr) 237 assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); 238 239 unsigned opc[2]; 240 const TargetRegisterInfo *TRI = &getRegisterInfo(); 241 MachineFunction *MF = MBB.getParent(); 242 const MachineRegisterInfo &MRI = MF->getRegInfo(); 243 unsigned Reg = Cond[2].getReg(); 244 if (IsIntegerCC(Cond[0].getImm())) { 245 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 246 opc[0] = VE::BRCFWir; 247 opc[1] = VE::BRCFWrr; 248 } else { 249 opc[0] = VE::BRCFLir; 250 opc[1] = VE::BRCFLrr; 251 } 252 } else { 253 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 254 opc[0] = VE::BRCFSir; 255 opc[1] = VE::BRCFSrr; 256 } else { 257 opc[0] = VE::BRCFDir; 258 opc[1] = VE::BRCFDrr; 259 } 260 } 261 if (Cond[1].isImm()) { 262 BuildMI(&MBB, DL, get(opc[0])) 263 .add(Cond[0]) // condition code 264 .add(Cond[1]) // lhs 265 .add(Cond[2]) // rhs 266 .addMBB(TBB); 267 } else { 268 BuildMI(&MBB, DL, get(opc[1])) 269 .add(Cond[0]) 270 .add(Cond[1]) 271 .add(Cond[2]) 272 .addMBB(TBB); 273 } 274 275 if (!FBB) 276 return 1; 277 278 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 279 .addMBB(FBB); 280 return 2; 281 } 282 283 unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, 284 int *BytesRemoved) const { 285 assert(!BytesRemoved && "code size not handled"); 286 287 MachineBasicBlock::iterator I = MBB.end(); 288 unsigned Count = 0; 289 while (I != MBB.begin()) { 290 --I; 291 292 if (I->isDebugValue()) 293 continue; 294 295 if (!isUncondBranchOpcode(I->getOpcode()) && 296 !isCondBranchOpcode(I->getOpcode())) 297 break; // Not a branch 298 299 I->eraseFromParent(); 300 I = MBB.end(); 301 ++Count; 302 } 303 return Count; 304 } 305 306 bool VEInstrInfo::reverseBranchCondition( 307 SmallVectorImpl<MachineOperand> &Cond) const { 308 VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm()); 309 Cond[0].setImm(GetOppositeBranchCondition(CC)); 310 return false; 311 } 312 313 static bool IsAliasOfSX(Register Reg) { 314 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || 315 VE::F32RegClass.contains(Reg); 316 } 317 318 static void copyPhysSubRegs(MachineBasicBlock &MBB, 319 MachineBasicBlock::iterator I, const DebugLoc &DL, 320 MCRegister DestReg, MCRegister SrcReg, bool KillSrc, 321 const MCInstrDesc &MCID, unsigned int NumSubRegs, 322 const unsigned *SubRegIdx, 323 const TargetRegisterInfo *TRI) { 324 MachineInstr *MovMI = nullptr; 325 326 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { 327 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); 328 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); 329 assert(SubDest && SubSrc && "Bad sub-register"); 330 331 if (MCID.getOpcode() == VE::ORri) { 332 // generate "ORri, dest, src, 0" instruction. 333 MachineInstrBuilder MIB = 334 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); 335 MovMI = MIB.getInstr(); 336 } else { 337 llvm_unreachable("Unexpected reg-to-reg copy instruction"); 338 } 339 } 340 // Add implicit super-register defs and kills to the last MovMI. 341 MovMI->addRegisterDefined(DestReg, TRI); 342 if (KillSrc) 343 MovMI->addRegisterKilled(SrcReg, TRI, true); 344 } 345 346 void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 347 MachineBasicBlock::iterator I, const DebugLoc &DL, 348 MCRegister DestReg, MCRegister SrcReg, 349 bool KillSrc) const { 350 351 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { 352 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) 353 .addReg(SrcReg, getKillRegState(KillSrc)) 354 .addImm(0); 355 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { 356 // Use two instructions. 357 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; 358 unsigned int NumSubRegs = 2; 359 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri), 360 NumSubRegs, SubRegIdx, &getRegisterInfo()); 361 } else { 362 const TargetRegisterInfo *TRI = &getRegisterInfo(); 363 dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI) 364 << " to " << printReg(DestReg, TRI) << "\n"; 365 llvm_unreachable("Impossible reg-to-reg copy"); 366 } 367 } 368 369 /// isLoadFromStackSlot - If the specified machine instruction is a direct 370 /// load from a stack slot, return the virtual or physical register number of 371 /// the destination along with the FrameIndex of the loaded stack slot. If 372 /// not, return 0. This predicate must return 0 if the instruction has 373 /// any side effects other than loading from the stack slot. 374 unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 375 int &FrameIndex) const { 376 if (MI.getOpcode() == VE::LDrii || // I64 377 MI.getOpcode() == VE::LDLSXrii || // I32 378 MI.getOpcode() == VE::LDUrii || // F32 379 MI.getOpcode() == VE::LDQrii // F128 (pseudo) 380 ) { 381 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 382 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() && 383 MI.getOperand(3).getImm() == 0) { 384 FrameIndex = MI.getOperand(1).getIndex(); 385 return MI.getOperand(0).getReg(); 386 } 387 } 388 return 0; 389 } 390 391 /// isStoreToStackSlot - If the specified machine instruction is a direct 392 /// store to a stack slot, return the virtual or physical register number of 393 /// the source reg along with the FrameIndex of the loaded stack slot. If 394 /// not, return 0. This predicate must return 0 if the instruction has 395 /// any side effects other than storing to the stack slot. 396 unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 397 int &FrameIndex) const { 398 if (MI.getOpcode() == VE::STrii || // I64 399 MI.getOpcode() == VE::STLrii || // I32 400 MI.getOpcode() == VE::STUrii || // F32 401 MI.getOpcode() == VE::STQrii // F128 (pseudo) 402 ) { 403 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && 404 MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() && 405 MI.getOperand(2).getImm() == 0) { 406 FrameIndex = MI.getOperand(0).getIndex(); 407 return MI.getOperand(3).getReg(); 408 } 409 } 410 return 0; 411 } 412 413 void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 414 MachineBasicBlock::iterator I, 415 Register SrcReg, bool isKill, int FI, 416 const TargetRegisterClass *RC, 417 const TargetRegisterInfo *TRI) const { 418 DebugLoc DL; 419 if (I != MBB.end()) 420 DL = I->getDebugLoc(); 421 422 MachineFunction *MF = MBB.getParent(); 423 const MachineFrameInfo &MFI = MF->getFrameInfo(); 424 MachineMemOperand *MMO = MF->getMachineMemOperand( 425 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 426 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 427 428 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 429 if (RC == &VE::I64RegClass) { 430 BuildMI(MBB, I, DL, get(VE::STrii)) 431 .addFrameIndex(FI) 432 .addImm(0) 433 .addImm(0) 434 .addReg(SrcReg, getKillRegState(isKill)) 435 .addMemOperand(MMO); 436 } else if (RC == &VE::I32RegClass) { 437 BuildMI(MBB, I, DL, get(VE::STLrii)) 438 .addFrameIndex(FI) 439 .addImm(0) 440 .addImm(0) 441 .addReg(SrcReg, getKillRegState(isKill)) 442 .addMemOperand(MMO); 443 } else if (RC == &VE::F32RegClass) { 444 BuildMI(MBB, I, DL, get(VE::STUrii)) 445 .addFrameIndex(FI) 446 .addImm(0) 447 .addImm(0) 448 .addReg(SrcReg, getKillRegState(isKill)) 449 .addMemOperand(MMO); 450 } else if (VE::F128RegClass.hasSubClassEq(RC)) { 451 BuildMI(MBB, I, DL, get(VE::STQrii)) 452 .addFrameIndex(FI) 453 .addImm(0) 454 .addImm(0) 455 .addReg(SrcReg, getKillRegState(isKill)) 456 .addMemOperand(MMO); 457 } else 458 report_fatal_error("Can't store this register to stack slot"); 459 } 460 461 void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 462 MachineBasicBlock::iterator I, 463 Register DestReg, int FI, 464 const TargetRegisterClass *RC, 465 const TargetRegisterInfo *TRI) const { 466 DebugLoc DL; 467 if (I != MBB.end()) 468 DL = I->getDebugLoc(); 469 470 MachineFunction *MF = MBB.getParent(); 471 const MachineFrameInfo &MFI = MF->getFrameInfo(); 472 MachineMemOperand *MMO = MF->getMachineMemOperand( 473 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 474 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 475 476 if (RC == &VE::I64RegClass) { 477 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) 478 .addFrameIndex(FI) 479 .addImm(0) 480 .addImm(0) 481 .addMemOperand(MMO); 482 } else if (RC == &VE::I32RegClass) { 483 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) 484 .addFrameIndex(FI) 485 .addImm(0) 486 .addImm(0) 487 .addMemOperand(MMO); 488 } else if (RC == &VE::F32RegClass) { 489 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) 490 .addFrameIndex(FI) 491 .addImm(0) 492 .addImm(0) 493 .addMemOperand(MMO); 494 } else if (VE::F128RegClass.hasSubClassEq(RC)) { 495 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) 496 .addFrameIndex(FI) 497 .addImm(0) 498 .addImm(0) 499 .addMemOperand(MMO); 500 } else 501 report_fatal_error("Can't load this register from stack slot"); 502 } 503 504 Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 505 VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>(); 506 Register GlobalBaseReg = VEFI->getGlobalBaseReg(); 507 if (GlobalBaseReg != 0) 508 return GlobalBaseReg; 509 510 // We use %s15 (%got) as a global base register 511 GlobalBaseReg = VE::SX15; 512 513 // Insert a pseudo instruction to set the GlobalBaseReg into the first 514 // MBB of the function 515 MachineBasicBlock &FirstMBB = MF->front(); 516 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 517 DebugLoc dl; 518 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg); 519 VEFI->setGlobalBaseReg(GlobalBaseReg); 520 return GlobalBaseReg; 521 } 522 523 bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 524 switch (MI.getOpcode()) { 525 case VE::EXTEND_STACK: { 526 return expandExtendStackPseudo(MI); 527 } 528 case VE::EXTEND_STACK_GUARD: { 529 MI.eraseFromParent(); // The pseudo instruction is gone now. 530 return true; 531 } 532 case VE::GETSTACKTOP: { 533 return expandGetStackTopPseudo(MI); 534 } 535 } 536 return false; 537 } 538 539 bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const { 540 MachineBasicBlock &MBB = *MI.getParent(); 541 MachineFunction &MF = *MBB.getParent(); 542 const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 543 const VEInstrInfo &TII = *STI.getInstrInfo(); 544 DebugLoc dl = MBB.findDebugLoc(MI); 545 546 // Create following instructions and multiple basic blocks. 547 // 548 // thisBB: 549 // brge.l.t %sp, %sl, sinkBB 550 // syscallBB: 551 // ld %s61, 0x18(, %tp) // load param area 552 // or %s62, 0, %s0 // spill the value of %s0 553 // lea %s63, 0x13b // syscall # of grow 554 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0 555 // shm.l %sl, 0x8(%s61) // store old limit at addr:8 556 // shm.l %sp, 0x10(%s61) // store new limit at addr:16 557 // monc // call monitor 558 // or %s0, 0, %s62 // restore the value of %s0 559 // sinkBB: 560 561 // Create new MBB 562 MachineBasicBlock *BB = &MBB; 563 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 564 MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB); 565 MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB); 566 MachineFunction::iterator It = ++(BB->getIterator()); 567 MF.insert(It, syscallMBB); 568 MF.insert(It, sinkMBB); 569 570 // Transfer the remainder of BB and its successor edges to sinkMBB. 571 sinkMBB->splice(sinkMBB->begin(), BB, 572 std::next(std::next(MachineBasicBlock::iterator(MI))), 573 BB->end()); 574 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 575 576 // Next, add the true and fallthrough blocks as its successors. 577 BB->addSuccessor(syscallMBB); 578 BB->addSuccessor(sinkMBB); 579 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) 580 .addImm(VECC::CC_IGE) 581 .addReg(VE::SX11) // %sp 582 .addReg(VE::SX8) // %sl 583 .addMBB(sinkMBB); 584 585 BB = syscallMBB; 586 587 // Update machine-CFG edges 588 BB->addSuccessor(sinkMBB); 589 590 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) 591 .addReg(VE::SX14) 592 .addImm(0) 593 .addImm(0x18); 594 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) 595 .addReg(VE::SX0) 596 .addImm(0); 597 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) 598 .addImm(0) 599 .addImm(0) 600 .addImm(0x13b); 601 BuildMI(BB, dl, TII.get(VE::SHMLri)) 602 .addReg(VE::SX61) 603 .addImm(0) 604 .addReg(VE::SX63); 605 BuildMI(BB, dl, TII.get(VE::SHMLri)) 606 .addReg(VE::SX61) 607 .addImm(8) 608 .addReg(VE::SX8); 609 BuildMI(BB, dl, TII.get(VE::SHMLri)) 610 .addReg(VE::SX61) 611 .addImm(16) 612 .addReg(VE::SX11); 613 BuildMI(BB, dl, TII.get(VE::MONC)); 614 615 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0) 616 .addReg(VE::SX62) 617 .addImm(0); 618 619 MI.eraseFromParent(); // The pseudo instruction is gone now. 620 return true; 621 } 622 623 bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const { 624 MachineBasicBlock *MBB = MI.getParent(); 625 MachineFunction &MF = *MBB->getParent(); 626 const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 627 const VEInstrInfo &TII = *STI.getInstrInfo(); 628 DebugLoc DL = MBB->findDebugLoc(MI); 629 630 // Create following instruction 631 // 632 // dst = %sp + target specific frame + the size of parameter area 633 634 const MachineFrameInfo &MFI = MF.getFrameInfo(); 635 const VEFrameLowering &TFL = *STI.getFrameLowering(); 636 637 // The VE ABI requires a reserved 176 bytes area at the top 638 // of stack as described in VESubtarget.cpp. So, we adjust it here. 639 unsigned NumBytes = STI.getAdjustedFrameSize(0); 640 641 // Also adds the size of parameter area. 642 if (MFI.adjustsStack() && TFL.hasReservedCallFrame(MF)) 643 NumBytes += MFI.getMaxCallFrameSize(); 644 645 BuildMI(*MBB, MI, DL, TII.get(VE::LEArii)) 646 .addDef(MI.getOperand(0).getReg()) 647 .addReg(VE::SX11) 648 .addImm(0) 649 .addImm(NumBytes); 650 651 MI.eraseFromParent(); // The pseudo instruction is gone now. 652 return true; 653 } 654