1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the VE implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "VEInstrInfo.h" 14 #include "VE.h" 15 #include "VEMachineFunctionInfo.h" 16 #include "VESubtarget.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineMemOperand.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 28 #define DEBUG_TYPE "ve-instr-info" 29 30 using namespace llvm; 31 32 #define GET_INSTRINFO_CTOR_DTOR 33 #include "VEGenInstrInfo.inc" 34 35 // Pin the vtable to this file. 36 void VEInstrInfo::anchor() {} 37 38 VEInstrInfo::VEInstrInfo(VESubtarget &ST) 39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} 40 41 static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); } 42 43 static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) { 44 switch (CC) { 45 case VECC::CC_IG: 46 return VECC::CC_ILE; 47 case VECC::CC_IL: 48 return VECC::CC_IGE; 49 case VECC::CC_INE: 50 return VECC::CC_IEQ; 51 case VECC::CC_IEQ: 52 return VECC::CC_INE; 53 case VECC::CC_IGE: 54 return VECC::CC_IL; 55 case VECC::CC_ILE: 56 return VECC::CC_IG; 57 case VECC::CC_AF: 58 return VECC::CC_AT; 59 case VECC::CC_G: 60 return VECC::CC_LENAN; 61 case VECC::CC_L: 62 return VECC::CC_GENAN; 63 case VECC::CC_NE: 64 return VECC::CC_EQNAN; 65 case VECC::CC_EQ: 66 return VECC::CC_NENAN; 67 case VECC::CC_GE: 68 return VECC::CC_LNAN; 69 case VECC::CC_LE: 70 return VECC::CC_GNAN; 71 case VECC::CC_NUM: 72 return VECC::CC_NAN; 73 case VECC::CC_NAN: 74 return VECC::CC_NUM; 75 case VECC::CC_GNAN: 76 return VECC::CC_LE; 77 case VECC::CC_LNAN: 78 return VECC::CC_GE; 79 case VECC::CC_NENAN: 80 return VECC::CC_EQ; 81 case VECC::CC_EQNAN: 82 return VECC::CC_NE; 83 case VECC::CC_GENAN: 84 return VECC::CC_L; 85 case VECC::CC_LENAN: 86 return VECC::CC_G; 87 case VECC::CC_AT: 88 return VECC::CC_AF; 89 case VECC::UNKNOWN: 90 return VECC::UNKNOWN; 91 } 92 llvm_unreachable("Invalid cond code"); 93 } 94 95 // Treat a branch relative long always instruction as unconditional branch. 96 // For example, br.l.t and br.l. 97 static bool isUncondBranchOpcode(int Opc) { 98 using namespace llvm::VE; 99 100 #define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t) 101 // VE has other branch relative always instructions for word/double/float, 102 // but we use only long branches in our lower. So, sanity check it here. 103 assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) && 104 "Branch relative word/double/float always instructions should not be " 105 "used!"); 106 return BRKIND(BRCFL); 107 #undef BRKIND 108 } 109 110 // Treat branch relative conditional as conditional branch instructions. 111 // For example, brgt.l.t and brle.s.nt. 112 static bool isCondBranchOpcode(int Opc) { 113 using namespace llvm::VE; 114 115 #define BRKIND(NAME) \ 116 (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \ 117 Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t) 118 return BRKIND(BRCFL) || BRKIND(BRCFW) || BRKIND(BRCFD) || BRKIND(BRCFS); 119 #undef BRKIND 120 } 121 122 // Treat branch long always instructions as indirect branch. 123 // For example, b.l.t and b.l. 124 static bool isIndirectBranchOpcode(int Opc) { 125 using namespace llvm::VE; 126 127 #define BRKIND(NAME) \ 128 (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t) 129 // VE has other branch always instructions for word/double/float, but 130 // we use only long branches in our lower. So, sanity check it here. 131 assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) && 132 "Branch word/double/float always instructions should not be used!"); 133 return BRKIND(BCFL); 134 #undef BRKIND 135 } 136 137 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, 138 SmallVectorImpl<MachineOperand> &Cond) { 139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); 140 Cond.push_back(LastInst->getOperand(1)); 141 Cond.push_back(LastInst->getOperand(2)); 142 Target = LastInst->getOperand(3).getMBB(); 143 } 144 145 bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 146 MachineBasicBlock *&FBB, 147 SmallVectorImpl<MachineOperand> &Cond, 148 bool AllowModify) const { 149 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 150 if (I == MBB.end()) 151 return false; 152 153 if (!isUnpredicatedTerminator(*I)) 154 return false; 155 156 // Get the last instruction in the block. 157 MachineInstr *LastInst = &*I; 158 unsigned LastOpc = LastInst->getOpcode(); 159 160 // If there is only one terminator instruction, process it. 161 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 162 if (isUncondBranchOpcode(LastOpc)) { 163 TBB = LastInst->getOperand(0).getMBB(); 164 return false; 165 } 166 if (isCondBranchOpcode(LastOpc)) { 167 // Block ends with fall-through condbranch. 168 parseCondBranch(LastInst, TBB, Cond); 169 return false; 170 } 171 return true; // Can't handle indirect branch. 172 } 173 174 // Get the instruction before it if it is a terminator. 175 MachineInstr *SecondLastInst = &*I; 176 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 177 178 // If AllowModify is true and the block ends with two or more unconditional 179 // branches, delete all but the first unconditional branch. 180 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 181 while (isUncondBranchOpcode(SecondLastOpc)) { 182 LastInst->eraseFromParent(); 183 LastInst = SecondLastInst; 184 LastOpc = LastInst->getOpcode(); 185 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 186 // Return now the only terminator is an unconditional branch. 187 TBB = LastInst->getOperand(0).getMBB(); 188 return false; 189 } 190 SecondLastInst = &*I; 191 SecondLastOpc = SecondLastInst->getOpcode(); 192 } 193 } 194 195 // If there are three terminators, we don't know what sort of block this is. 196 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 197 return true; 198 199 // If the block ends with a B and a Bcc, handle it. 200 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 201 parseCondBranch(SecondLastInst, TBB, Cond); 202 FBB = LastInst->getOperand(0).getMBB(); 203 return false; 204 } 205 206 // If the block ends with two unconditional branches, handle it. The second 207 // one is not executed. 208 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 209 TBB = SecondLastInst->getOperand(0).getMBB(); 210 return false; 211 } 212 213 // ...likewise if it ends with an indirect branch followed by an unconditional 214 // branch. 215 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 216 I = LastInst; 217 if (AllowModify) 218 I->eraseFromParent(); 219 return true; 220 } 221 222 // Otherwise, can't handle this. 223 return true; 224 } 225 226 unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, 227 MachineBasicBlock *TBB, 228 MachineBasicBlock *FBB, 229 ArrayRef<MachineOperand> Cond, 230 const DebugLoc &DL, int *BytesAdded) const { 231 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 232 assert((Cond.size() == 3 || Cond.size() == 0) && 233 "VE branch conditions should have three component!"); 234 assert(!BytesAdded && "code size not handled"); 235 if (Cond.empty()) { 236 // Uncondition branch 237 assert(!FBB && "Unconditional branch with multiple successors!"); 238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 239 .addMBB(TBB); 240 return 1; 241 } 242 243 // Conditional branch 244 // (BRCFir CC sy sz addr) 245 assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); 246 247 unsigned opc[2]; 248 const TargetRegisterInfo *TRI = &getRegisterInfo(); 249 MachineFunction *MF = MBB.getParent(); 250 const MachineRegisterInfo &MRI = MF->getRegInfo(); 251 unsigned Reg = Cond[2].getReg(); 252 if (IsIntegerCC(Cond[0].getImm())) { 253 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 254 opc[0] = VE::BRCFWir; 255 opc[1] = VE::BRCFWrr; 256 } else { 257 opc[0] = VE::BRCFLir; 258 opc[1] = VE::BRCFLrr; 259 } 260 } else { 261 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 262 opc[0] = VE::BRCFSir; 263 opc[1] = VE::BRCFSrr; 264 } else { 265 opc[0] = VE::BRCFDir; 266 opc[1] = VE::BRCFDrr; 267 } 268 } 269 if (Cond[1].isImm()) { 270 BuildMI(&MBB, DL, get(opc[0])) 271 .add(Cond[0]) // condition code 272 .add(Cond[1]) // lhs 273 .add(Cond[2]) // rhs 274 .addMBB(TBB); 275 } else { 276 BuildMI(&MBB, DL, get(opc[1])) 277 .add(Cond[0]) 278 .add(Cond[1]) 279 .add(Cond[2]) 280 .addMBB(TBB); 281 } 282 283 if (!FBB) 284 return 1; 285 286 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 287 .addMBB(FBB); 288 return 2; 289 } 290 291 unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, 292 int *BytesRemoved) const { 293 assert(!BytesRemoved && "code size not handled"); 294 295 MachineBasicBlock::iterator I = MBB.end(); 296 unsigned Count = 0; 297 while (I != MBB.begin()) { 298 --I; 299 300 if (I->isDebugValue()) 301 continue; 302 303 if (!isUncondBranchOpcode(I->getOpcode()) && 304 !isCondBranchOpcode(I->getOpcode())) 305 break; // Not a branch 306 307 I->eraseFromParent(); 308 I = MBB.end(); 309 ++Count; 310 } 311 return Count; 312 } 313 314 bool VEInstrInfo::reverseBranchCondition( 315 SmallVectorImpl<MachineOperand> &Cond) const { 316 VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm()); 317 Cond[0].setImm(GetOppositeBranchCondition(CC)); 318 return false; 319 } 320 321 static bool IsAliasOfSX(Register Reg) { 322 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || 323 VE::F32RegClass.contains(Reg); 324 } 325 326 static void copyPhysSubRegs(MachineBasicBlock &MBB, 327 MachineBasicBlock::iterator I, const DebugLoc &DL, 328 MCRegister DestReg, MCRegister SrcReg, bool KillSrc, 329 const MCInstrDesc &MCID, unsigned int NumSubRegs, 330 const unsigned *SubRegIdx, 331 const TargetRegisterInfo *TRI) { 332 MachineInstr *MovMI = nullptr; 333 334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { 335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); 336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); 337 assert(SubDest && SubSrc && "Bad sub-register"); 338 339 if (MCID.getOpcode() == VE::ORri) { 340 // generate "ORri, dest, src, 0" instruction. 341 MachineInstrBuilder MIB = 342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); 343 MovMI = MIB.getInstr(); 344 } else { 345 llvm_unreachable("Unexpected reg-to-reg copy instruction"); 346 } 347 } 348 // Add implicit super-register defs and kills to the last MovMI. 349 MovMI->addRegisterDefined(DestReg, TRI); 350 if (KillSrc) 351 MovMI->addRegisterKilled(SrcReg, TRI, true); 352 } 353 354 void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 355 MachineBasicBlock::iterator I, const DebugLoc &DL, 356 MCRegister DestReg, MCRegister SrcReg, 357 bool KillSrc) const { 358 359 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { 360 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) 361 .addReg(SrcReg, getKillRegState(KillSrc)) 362 .addImm(0); 363 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { 364 // Generate following instructions 365 // %sw16 = LEA32zii 256 366 // VORmvl %dest, (0)1, %src, %sw16 367 // TODO: reuse a register if vl is already assigned to a register 368 // FIXME: it would be better to scavenge a register here instead of 369 // reserving SX16 all of the time. 370 const TargetRegisterInfo *TRI = &getRegisterInfo(); 371 Register TmpReg = VE::SX16; 372 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); 373 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) 374 .addImm(0) 375 .addImm(0) 376 .addImm(256); 377 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) 378 .addImm(M1(0)) // Represent (0)1. 379 .addReg(SrcReg, getKillRegState(KillSrc)) 380 .addReg(SubTmp, getKillRegState(true)); 381 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); 382 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { 383 // Use two instructions. 384 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; 385 unsigned int NumSubRegs = 2; 386 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri), 387 NumSubRegs, SubRegIdx, &getRegisterInfo()); 388 } else { 389 const TargetRegisterInfo *TRI = &getRegisterInfo(); 390 dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI) 391 << " to " << printReg(DestReg, TRI) << "\n"; 392 llvm_unreachable("Impossible reg-to-reg copy"); 393 } 394 } 395 396 /// isLoadFromStackSlot - If the specified machine instruction is a direct 397 /// load from a stack slot, return the virtual or physical register number of 398 /// the destination along with the FrameIndex of the loaded stack slot. If 399 /// not, return 0. This predicate must return 0 if the instruction has 400 /// any side effects other than loading from the stack slot. 401 unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 402 int &FrameIndex) const { 403 if (MI.getOpcode() == VE::LDrii || // I64 404 MI.getOpcode() == VE::LDLSXrii || // I32 405 MI.getOpcode() == VE::LDUrii || // F32 406 MI.getOpcode() == VE::LDQrii // F128 (pseudo) 407 ) { 408 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 409 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() && 410 MI.getOperand(3).getImm() == 0) { 411 FrameIndex = MI.getOperand(1).getIndex(); 412 return MI.getOperand(0).getReg(); 413 } 414 } 415 return 0; 416 } 417 418 /// isStoreToStackSlot - If the specified machine instruction is a direct 419 /// store to a stack slot, return the virtual or physical register number of 420 /// the source reg along with the FrameIndex of the loaded stack slot. If 421 /// not, return 0. This predicate must return 0 if the instruction has 422 /// any side effects other than storing to the stack slot. 423 unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 424 int &FrameIndex) const { 425 if (MI.getOpcode() == VE::STrii || // I64 426 MI.getOpcode() == VE::STLrii || // I32 427 MI.getOpcode() == VE::STUrii || // F32 428 MI.getOpcode() == VE::STQrii // F128 (pseudo) 429 ) { 430 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && 431 MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() && 432 MI.getOperand(2).getImm() == 0) { 433 FrameIndex = MI.getOperand(0).getIndex(); 434 return MI.getOperand(3).getReg(); 435 } 436 } 437 return 0; 438 } 439 440 void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 441 MachineBasicBlock::iterator I, 442 Register SrcReg, bool isKill, int FI, 443 const TargetRegisterClass *RC, 444 const TargetRegisterInfo *TRI) const { 445 DebugLoc DL; 446 if (I != MBB.end()) 447 DL = I->getDebugLoc(); 448 449 MachineFunction *MF = MBB.getParent(); 450 const MachineFrameInfo &MFI = MF->getFrameInfo(); 451 MachineMemOperand *MMO = MF->getMachineMemOperand( 452 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 453 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 454 455 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 456 if (RC == &VE::I64RegClass) { 457 BuildMI(MBB, I, DL, get(VE::STrii)) 458 .addFrameIndex(FI) 459 .addImm(0) 460 .addImm(0) 461 .addReg(SrcReg, getKillRegState(isKill)) 462 .addMemOperand(MMO); 463 } else if (RC == &VE::I32RegClass) { 464 BuildMI(MBB, I, DL, get(VE::STLrii)) 465 .addFrameIndex(FI) 466 .addImm(0) 467 .addImm(0) 468 .addReg(SrcReg, getKillRegState(isKill)) 469 .addMemOperand(MMO); 470 } else if (RC == &VE::F32RegClass) { 471 BuildMI(MBB, I, DL, get(VE::STUrii)) 472 .addFrameIndex(FI) 473 .addImm(0) 474 .addImm(0) 475 .addReg(SrcReg, getKillRegState(isKill)) 476 .addMemOperand(MMO); 477 } else if (VE::F128RegClass.hasSubClassEq(RC)) { 478 BuildMI(MBB, I, DL, get(VE::STQrii)) 479 .addFrameIndex(FI) 480 .addImm(0) 481 .addImm(0) 482 .addReg(SrcReg, getKillRegState(isKill)) 483 .addMemOperand(MMO); 484 } else 485 report_fatal_error("Can't store this register to stack slot"); 486 } 487 488 void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 489 MachineBasicBlock::iterator I, 490 Register DestReg, int FI, 491 const TargetRegisterClass *RC, 492 const TargetRegisterInfo *TRI) const { 493 DebugLoc DL; 494 if (I != MBB.end()) 495 DL = I->getDebugLoc(); 496 497 MachineFunction *MF = MBB.getParent(); 498 const MachineFrameInfo &MFI = MF->getFrameInfo(); 499 MachineMemOperand *MMO = MF->getMachineMemOperand( 500 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 501 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 502 503 if (RC == &VE::I64RegClass) { 504 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) 505 .addFrameIndex(FI) 506 .addImm(0) 507 .addImm(0) 508 .addMemOperand(MMO); 509 } else if (RC == &VE::I32RegClass) { 510 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) 511 .addFrameIndex(FI) 512 .addImm(0) 513 .addImm(0) 514 .addMemOperand(MMO); 515 } else if (RC == &VE::F32RegClass) { 516 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) 517 .addFrameIndex(FI) 518 .addImm(0) 519 .addImm(0) 520 .addMemOperand(MMO); 521 } else if (VE::F128RegClass.hasSubClassEq(RC)) { 522 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) 523 .addFrameIndex(FI) 524 .addImm(0) 525 .addImm(0) 526 .addMemOperand(MMO); 527 } else 528 report_fatal_error("Can't load this register from stack slot"); 529 } 530 531 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 532 Register Reg, MachineRegisterInfo *MRI) const { 533 LLVM_DEBUG(dbgs() << "FoldImmediate\n"); 534 535 LLVM_DEBUG(dbgs() << "checking DefMI\n"); 536 int64_t ImmVal; 537 switch (DefMI.getOpcode()) { 538 default: 539 return false; 540 case VE::ORim: 541 // General move small immediate instruction on VE. 542 LLVM_DEBUG(dbgs() << "checking ORim\n"); 543 LLVM_DEBUG(DefMI.dump()); 544 // FIXME: We may need to support FPImm too. 545 assert(DefMI.getOperand(1).isImm()); 546 assert(DefMI.getOperand(2).isImm()); 547 ImmVal = 548 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm()); 549 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); 550 break; 551 case VE::LEAzii: 552 // General move immediate instruction on VE. 553 LLVM_DEBUG(dbgs() << "checking LEAzii\n"); 554 LLVM_DEBUG(DefMI.dump()); 555 // FIXME: We may need to support FPImm too. 556 assert(DefMI.getOperand(2).isImm()); 557 if (!DefMI.getOperand(3).isImm()) 558 // LEAzii may refer label 559 return false; 560 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm(); 561 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); 562 break; 563 } 564 565 // Try to fold like below: 566 // %1:i64 = ORim 0, 0(1) 567 // %2:i64 = CMPSLrr %0, %1 568 // To 569 // %2:i64 = CMPSLrm %0, 0(1) 570 // 571 // Another example: 572 // %1:i64 = ORim 6, 0(1) 573 // %2:i64 = CMPSLrr %1, %0 574 // To 575 // %2:i64 = CMPSLir 6, %0 576 // 577 // Support commutable instructions like below: 578 // %1:i64 = ORim 6, 0(1) 579 // %2:i64 = ADDSLrr %1, %0 580 // To 581 // %2:i64 = ADDSLri %0, 6 582 // 583 // FIXME: Need to support i32. Current implementtation requires 584 // EXTRACT_SUBREG, so input has following COPY and it avoids folding: 585 // %1:i64 = ORim 6, 0(1) 586 // %2:i32 = COPY %1.sub_i32 587 // %3:i32 = ADDSWSXrr %0, %2 588 // FIXME: Need to support shift, cmov, and more instructions. 589 // FIXME: Need to support lvl too, but LVLGen runs after peephole-opt. 590 591 LLVM_DEBUG(dbgs() << "checking UseMI\n"); 592 LLVM_DEBUG(UseMI.dump()); 593 unsigned NewUseOpcSImm7; 594 unsigned NewUseOpcMImm; 595 enum InstType { 596 rr2ri_rm, // rr -> ri or rm, commutable 597 rr2ir_rm, // rr -> ir or rm 598 } InstType; 599 600 using namespace llvm::VE; 601 #define INSTRKIND(NAME) \ 602 case NAME##rr: \ 603 NewUseOpcSImm7 = NAME##ri; \ 604 NewUseOpcMImm = NAME##rm; \ 605 InstType = rr2ri_rm; \ 606 break 607 #define NCINSTRKIND(NAME) \ 608 case NAME##rr: \ 609 NewUseOpcSImm7 = NAME##ir; \ 610 NewUseOpcMImm = NAME##rm; \ 611 InstType = rr2ir_rm; \ 612 break 613 614 switch (UseMI.getOpcode()) { 615 default: 616 return false; 617 618 INSTRKIND(ADDUL); 619 INSTRKIND(ADDSWSX); 620 INSTRKIND(ADDSWZX); 621 INSTRKIND(ADDSL); 622 NCINSTRKIND(SUBUL); 623 NCINSTRKIND(SUBSWSX); 624 NCINSTRKIND(SUBSWZX); 625 NCINSTRKIND(SUBSL); 626 INSTRKIND(MULUL); 627 INSTRKIND(MULSWSX); 628 INSTRKIND(MULSWZX); 629 INSTRKIND(MULSL); 630 NCINSTRKIND(DIVUL); 631 NCINSTRKIND(DIVSWSX); 632 NCINSTRKIND(DIVSWZX); 633 NCINSTRKIND(DIVSL); 634 NCINSTRKIND(CMPUL); 635 NCINSTRKIND(CMPSWSX); 636 NCINSTRKIND(CMPSWZX); 637 NCINSTRKIND(CMPSL); 638 INSTRKIND(MAXSWSX); 639 INSTRKIND(MAXSWZX); 640 INSTRKIND(MAXSL); 641 INSTRKIND(MINSWSX); 642 INSTRKIND(MINSWZX); 643 INSTRKIND(MINSL); 644 INSTRKIND(AND); 645 INSTRKIND(OR); 646 INSTRKIND(XOR); 647 INSTRKIND(EQV); 648 NCINSTRKIND(NND); 649 NCINSTRKIND(MRG); 650 } 651 652 #undef INSTRKIND 653 654 unsigned NewUseOpc; 655 unsigned UseIdx; 656 bool Commute = false; 657 LLVM_DEBUG(dbgs() << "checking UseMI operands\n"); 658 switch (InstType) { 659 case rr2ri_rm: 660 UseIdx = 2; 661 if (UseMI.getOperand(1).getReg() == Reg) { 662 Commute = true; 663 } else { 664 assert(UseMI.getOperand(2).getReg() == Reg); 665 } 666 if (isInt<7>(ImmVal)) { 667 // This ImmVal matches to SImm7 slot, so change UseOpc to an instruction 668 // holds a simm7 slot. 669 NewUseOpc = NewUseOpcSImm7; 670 } else if (isMImmVal(ImmVal)) { 671 // Similarly, change UseOpc to an instruction holds a mimm slot. 672 NewUseOpc = NewUseOpcMImm; 673 ImmVal = val2MImm(ImmVal); 674 } else 675 return false; 676 break; 677 case rr2ir_rm: 678 if (UseMI.getOperand(1).getReg() == Reg) { 679 // Check immediate value whether it matchs to the UseMI instruction. 680 if (!isInt<7>(ImmVal)) 681 return false; 682 NewUseOpc = NewUseOpcSImm7; 683 UseIdx = 1; 684 } else { 685 assert(UseMI.getOperand(2).getReg() == Reg); 686 // Check immediate value whether it matchs to the UseMI instruction. 687 if (!isMImmVal(ImmVal)) 688 return false; 689 NewUseOpc = NewUseOpcMImm; 690 ImmVal = val2MImm(ImmVal); 691 UseIdx = 2; 692 } 693 break; 694 } 695 696 LLVM_DEBUG(dbgs() << "modifying UseMI\n"); 697 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 698 UseMI.setDesc(get(NewUseOpc)); 699 if (Commute) { 700 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); 701 } 702 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); 703 if (DeleteDef) 704 DefMI.eraseFromParent(); 705 706 return true; 707 } 708 709 Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 710 VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>(); 711 Register GlobalBaseReg = VEFI->getGlobalBaseReg(); 712 if (GlobalBaseReg != 0) 713 return GlobalBaseReg; 714 715 // We use %s15 (%got) as a global base register 716 GlobalBaseReg = VE::SX15; 717 718 // Insert a pseudo instruction to set the GlobalBaseReg into the first 719 // MBB of the function 720 MachineBasicBlock &FirstMBB = MF->front(); 721 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 722 DebugLoc dl; 723 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg); 724 VEFI->setGlobalBaseReg(GlobalBaseReg); 725 return GlobalBaseReg; 726 } 727 728 static Register getVM512Upper(Register reg) { 729 return (reg - VE::VMP0) * 2 + VE::VM0; 730 } 731 732 static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; } 733 734 // Expand pseudo logical vector instructions for VM512 registers. 735 static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID) { 736 MachineBasicBlock *MBB = MI.getParent(); 737 DebugLoc DL = MI.getDebugLoc(); 738 739 Register VMXu = getVM512Upper(MI.getOperand(0).getReg()); 740 Register VMXl = getVM512Lower(MI.getOperand(0).getReg()); 741 Register VMYu = getVM512Upper(MI.getOperand(1).getReg()); 742 Register VMYl = getVM512Lower(MI.getOperand(1).getReg()); 743 744 switch (MI.getOpcode()) { 745 default: { 746 Register VMZu = getVM512Upper(MI.getOperand(2).getReg()); 747 Register VMZl = getVM512Lower(MI.getOperand(2).getReg()); 748 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); 749 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); 750 break; 751 } 752 case VE::NEGMy: 753 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); 754 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); 755 break; 756 } 757 MI.eraseFromParent(); 758 } 759 760 static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI, 761 bool Upper) { 762 // VM512 763 MIB.addReg(Upper ? getVM512Upper(MI.getOperand(0).getReg()) 764 : getVM512Lower(MI.getOperand(0).getReg())); 765 766 switch (MI.getNumExplicitOperands()) { 767 default: 768 report_fatal_error("unexpected number of operands for pvfmk"); 769 case 2: // _Ml: VM512, VL 770 // VL 771 MIB.addReg(MI.getOperand(1).getReg()); 772 break; 773 case 4: // _Mvl: VM512, CC, VR, VL 774 // CC 775 MIB.addImm(MI.getOperand(1).getImm()); 776 // VR 777 MIB.addReg(MI.getOperand(2).getReg()); 778 // VL 779 MIB.addReg(MI.getOperand(3).getReg()); 780 break; 781 case 5: // _MvMl: VM512, CC, VR, VM512, VL 782 // CC 783 MIB.addImm(MI.getOperand(1).getImm()); 784 // VR 785 MIB.addReg(MI.getOperand(2).getReg()); 786 // VM512 787 MIB.addReg(Upper ? getVM512Upper(MI.getOperand(3).getReg()) 788 : getVM512Lower(MI.getOperand(3).getReg())); 789 // VL 790 MIB.addReg(MI.getOperand(4).getReg()); 791 break; 792 } 793 } 794 795 static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI) { 796 // replace to pvfmk.w.up and pvfmk.w.lo 797 // replace to pvfmk.s.up and pvfmk.s.lo 798 799 static std::map<unsigned, std::pair<unsigned, unsigned>> VFMKMap = { 800 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}}, 801 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}}, 802 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}}, 803 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}}, 804 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}}, 805 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}}, 806 }; 807 808 unsigned Opcode = MI.getOpcode(); 809 810 auto Found = VFMKMap.find(Opcode); 811 if (Found == VFMKMap.end()) 812 report_fatal_error("unexpected opcode for pseudo vfmk"); 813 814 unsigned OpcodeUpper = (*Found).second.first; 815 unsigned OpcodeLower = (*Found).second.second; 816 817 MachineBasicBlock *MBB = MI.getParent(); 818 DebugLoc DL = MI.getDebugLoc(); 819 820 MachineInstrBuilder Bu = BuildMI(*MBB, MI, DL, TI.get(OpcodeUpper)); 821 addOperandsForVFMK(Bu, MI, /* Upper */ true); 822 MachineInstrBuilder Bl = BuildMI(*MBB, MI, DL, TI.get(OpcodeLower)); 823 addOperandsForVFMK(Bl, MI, /* Upper */ false); 824 825 MI.eraseFromParent(); 826 } 827 828 bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 829 switch (MI.getOpcode()) { 830 case VE::EXTEND_STACK: { 831 return expandExtendStackPseudo(MI); 832 } 833 case VE::EXTEND_STACK_GUARD: { 834 MI.eraseFromParent(); // The pseudo instruction is gone now. 835 return true; 836 } 837 case VE::GETSTACKTOP: { 838 return expandGetStackTopPseudo(MI); 839 } 840 841 case VE::ANDMyy: 842 expandPseudoLogM(MI, get(VE::ANDMmm)); 843 return true; 844 case VE::ORMyy: 845 expandPseudoLogM(MI, get(VE::ORMmm)); 846 return true; 847 case VE::XORMyy: 848 expandPseudoLogM(MI, get(VE::XORMmm)); 849 return true; 850 case VE::EQVMyy: 851 expandPseudoLogM(MI, get(VE::EQVMmm)); 852 return true; 853 case VE::NNDMyy: 854 expandPseudoLogM(MI, get(VE::NNDMmm)); 855 return true; 856 case VE::NEGMy: 857 expandPseudoLogM(MI, get(VE::NEGMm)); 858 return true; 859 860 case VE::LVMyir: 861 case VE::LVMyim: 862 case VE::LVMyir_y: 863 case VE::LVMyim_y: { 864 Register VMXu = getVM512Upper(MI.getOperand(0).getReg()); 865 Register VMXl = getVM512Lower(MI.getOperand(0).getReg()); 866 int64_t Imm = MI.getOperand(1).getImm(); 867 bool IsSrcReg = 868 MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y; 869 Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister; 870 int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm(); 871 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false; 872 Register VMX = VMXl; 873 if (Imm >= 4) { 874 VMX = VMXu; 875 Imm -= 4; 876 } 877 MachineBasicBlock *MBB = MI.getParent(); 878 DebugLoc DL = MI.getDebugLoc(); 879 switch (MI.getOpcode()) { 880 case VE::LVMyir: 881 BuildMI(*MBB, MI, DL, get(VE::LVMir)) 882 .addDef(VMX) 883 .addImm(Imm) 884 .addReg(Src, getKillRegState(KillSrc)); 885 break; 886 case VE::LVMyim: 887 BuildMI(*MBB, MI, DL, get(VE::LVMim)) 888 .addDef(VMX) 889 .addImm(Imm) 890 .addImm(MImm); 891 break; 892 case VE::LVMyir_y: 893 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() && 894 "LVMyir_y has different register in 3rd operand"); 895 BuildMI(*MBB, MI, DL, get(VE::LVMir_m)) 896 .addDef(VMX) 897 .addImm(Imm) 898 .addReg(Src, getKillRegState(KillSrc)) 899 .addReg(VMX); 900 break; 901 case VE::LVMyim_y: 902 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() && 903 "LVMyim_y has different register in 3rd operand"); 904 BuildMI(*MBB, MI, DL, get(VE::LVMim_m)) 905 .addDef(VMX) 906 .addImm(Imm) 907 .addImm(MImm) 908 .addReg(VMX); 909 break; 910 } 911 MI.eraseFromParent(); 912 return true; 913 } 914 case VE::SVMyi: { 915 Register Dest = MI.getOperand(0).getReg(); 916 Register VMZu = getVM512Upper(MI.getOperand(1).getReg()); 917 Register VMZl = getVM512Lower(MI.getOperand(1).getReg()); 918 bool KillSrc = MI.getOperand(1).isKill(); 919 int64_t Imm = MI.getOperand(2).getImm(); 920 Register VMZ = VMZl; 921 if (Imm >= 4) { 922 VMZ = VMZu; 923 Imm -= 4; 924 } 925 MachineBasicBlock *MBB = MI.getParent(); 926 DebugLoc DL = MI.getDebugLoc(); 927 MachineInstrBuilder MIB = 928 BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm); 929 MachineInstr *Inst = MIB.getInstr(); 930 MI.eraseFromParent(); 931 if (KillSrc) { 932 const TargetRegisterInfo *TRI = &getRegisterInfo(); 933 Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true); 934 } 935 return true; 936 } 937 case VE::VFMKyal: 938 case VE::VFMKynal: 939 case VE::VFMKWyvl: 940 case VE::VFMKWyvyl: 941 case VE::VFMKSyvl: 942 case VE::VFMKSyvyl: 943 expandPseudoVFMK(*this, MI); 944 } 945 return false; 946 } 947 948 bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const { 949 MachineBasicBlock &MBB = *MI.getParent(); 950 MachineFunction &MF = *MBB.getParent(); 951 const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 952 const VEInstrInfo &TII = *STI.getInstrInfo(); 953 DebugLoc dl = MBB.findDebugLoc(MI); 954 955 // Create following instructions and multiple basic blocks. 956 // 957 // thisBB: 958 // brge.l.t %sp, %sl, sinkBB 959 // syscallBB: 960 // ld %s61, 0x18(, %tp) // load param area 961 // or %s62, 0, %s0 // spill the value of %s0 962 // lea %s63, 0x13b // syscall # of grow 963 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0 964 // shm.l %sl, 0x8(%s61) // store old limit at addr:8 965 // shm.l %sp, 0x10(%s61) // store new limit at addr:16 966 // monc // call monitor 967 // or %s0, 0, %s62 // restore the value of %s0 968 // sinkBB: 969 970 // Create new MBB 971 MachineBasicBlock *BB = &MBB; 972 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 973 MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB); 974 MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB); 975 MachineFunction::iterator It = ++(BB->getIterator()); 976 MF.insert(It, syscallMBB); 977 MF.insert(It, sinkMBB); 978 979 // Transfer the remainder of BB and its successor edges to sinkMBB. 980 sinkMBB->splice(sinkMBB->begin(), BB, 981 std::next(std::next(MachineBasicBlock::iterator(MI))), 982 BB->end()); 983 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 984 985 // Next, add the true and fallthrough blocks as its successors. 986 BB->addSuccessor(syscallMBB); 987 BB->addSuccessor(sinkMBB); 988 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) 989 .addImm(VECC::CC_IGE) 990 .addReg(VE::SX11) // %sp 991 .addReg(VE::SX8) // %sl 992 .addMBB(sinkMBB); 993 994 BB = syscallMBB; 995 996 // Update machine-CFG edges 997 BB->addSuccessor(sinkMBB); 998 999 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) 1000 .addReg(VE::SX14) 1001 .addImm(0) 1002 .addImm(0x18); 1003 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) 1004 .addReg(VE::SX0) 1005 .addImm(0); 1006 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) 1007 .addImm(0) 1008 .addImm(0) 1009 .addImm(0x13b); 1010 BuildMI(BB, dl, TII.get(VE::SHMLri)) 1011 .addReg(VE::SX61) 1012 .addImm(0) 1013 .addReg(VE::SX63); 1014 BuildMI(BB, dl, TII.get(VE::SHMLri)) 1015 .addReg(VE::SX61) 1016 .addImm(8) 1017 .addReg(VE::SX8); 1018 BuildMI(BB, dl, TII.get(VE::SHMLri)) 1019 .addReg(VE::SX61) 1020 .addImm(16) 1021 .addReg(VE::SX11); 1022 BuildMI(BB, dl, TII.get(VE::MONC)); 1023 1024 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0) 1025 .addReg(VE::SX62) 1026 .addImm(0); 1027 1028 MI.eraseFromParent(); // The pseudo instruction is gone now. 1029 return true; 1030 } 1031 1032 bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const { 1033 MachineBasicBlock *MBB = MI.getParent(); 1034 MachineFunction &MF = *MBB->getParent(); 1035 const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 1036 const VEInstrInfo &TII = *STI.getInstrInfo(); 1037 DebugLoc DL = MBB->findDebugLoc(MI); 1038 1039 // Create following instruction 1040 // 1041 // dst = %sp + target specific frame + the size of parameter area 1042 1043 const MachineFrameInfo &MFI = MF.getFrameInfo(); 1044 const VEFrameLowering &TFL = *STI.getFrameLowering(); 1045 1046 // The VE ABI requires a reserved area at the top of stack as described 1047 // in VEFrameLowering.cpp. So, we adjust it here. 1048 unsigned NumBytes = STI.getAdjustedFrameSize(0); 1049 1050 // Also adds the size of parameter area. 1051 if (MFI.adjustsStack() && TFL.hasReservedCallFrame(MF)) 1052 NumBytes += MFI.getMaxCallFrameSize(); 1053 1054 BuildMI(*MBB, MI, DL, TII.get(VE::LEArii)) 1055 .addDef(MI.getOperand(0).getReg()) 1056 .addReg(VE::SX11) 1057 .addImm(0) 1058 .addImm(NumBytes); 1059 1060 MI.eraseFromParent(); // The pseudo instruction is gone now. 1061 return true; 1062 } 1063