1 //===-- VEFrameLowering.cpp - VE Frame Information ------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the VE implementation of TargetFrameLowering class. 10 // 11 // On VE, stack frames are structured as follows: 12 // 13 // The stack grows downward. 14 // 15 // All of the individual frame areas on the frame below are optional, i.e. it's 16 // possible to create a function so that the particular area isn't present 17 // in the frame. 18 // 19 // At function entry, the "frame" looks as follows: 20 // 21 // | | Higher address 22 // |----------------------------------------------| 23 // | Parameter area for this function | 24 // |----------------------------------------------| 25 // | Register save area (RSA) for this function | 26 // |----------------------------------------------| 27 // | Return address for this function | 28 // |----------------------------------------------| 29 // | Frame pointer for this function | 30 // |----------------------------------------------| <- sp 31 // | | Lower address 32 // 33 // VE doesn't use on demand stack allocation, so user code generated by LLVM 34 // needs to call VEOS to allocate stack frame. VE's ABI want to reduce the 35 // number of VEOS calls, so ABI requires to allocate not only RSA (in general 36 // CSR, callee saved register) area but also call frame at the prologue of 37 // caller function. 38 // 39 // After the prologue has run, the frame has the following general structure. 40 // Note that technically the last frame area (VLAs) doesn't get created until 41 // in the main function body, after the prologue is run. However, it's depicted 42 // here for completeness. 43 // 44 // | | Higher address 45 // |----------------------------------------------| 46 // | Parameter area for this function | 47 // |----------------------------------------------| 48 // | Register save area (RSA) for this function | 49 // |----------------------------------------------| 50 // | Return address for this function | 51 // |----------------------------------------------| 52 // | Frame pointer for this function | 53 // |----------------------------------------------| <- fp(=old sp) 54 // |.empty.space.to.make.part.below.aligned.in....| 55 // |.case.it.needs.more.than.the.standard.16-byte.| (size of this area is 56 // |.alignment....................................| unknown at compile time) 57 // |----------------------------------------------| 58 // | Local variables of fixed size including spill| 59 // | slots | 60 // |----------------------------------------------| <- bp(not defined by ABI, 61 // |.variable-sized.local.variables.(VLAs)........| LLVM chooses SX17) 62 // |..............................................| (size of this area is 63 // |..............................................| unknown at compile time) 64 // |----------------------------------------------| <- stack top (returned by 65 // | Parameter area for callee | alloca) 66 // |----------------------------------------------| 67 // | Register save area (RSA) for callee | 68 // |----------------------------------------------| 69 // | Return address for callee | 70 // |----------------------------------------------| 71 // | Frame pointer for callee | 72 // |----------------------------------------------| <- sp 73 // | | Lower address 74 // 75 // To access the data in a frame, at-compile time, a constant offset must be 76 // computable from one of the pointers (fp, bp, sp) to access it. The size 77 // of the areas with a dotted background cannot be computed at compile-time 78 // if they are present, making it required to have all three of fp, bp and 79 // sp to be set up to be able to access all contents in the frame areas, 80 // assuming all of the frame areas are non-empty. 81 // 82 // For most functions, some of the frame areas are empty. For those functions, 83 // it may not be necessary to set up fp or bp: 84 // * A base pointer is definitely needed when there are both VLAs and local 85 // variables with more-than-default alignment requirements. 86 // * A frame pointer is definitely needed when there are local variables with 87 // more-than-default alignment requirements. 88 // 89 // In addition, VE ABI defines RSA frame, return address, and frame pointer 90 // as follows: 91 // 92 // |----------------------------------------------| <- sp+176 93 // | %s18...%s33 | 94 // |----------------------------------------------| <- sp+48 95 // | Linkage area register (%s17) | 96 // |----------------------------------------------| <- sp+40 97 // | Procedure linkage table register (%plt=%s16) | 98 // |----------------------------------------------| <- sp+32 99 // | Global offset table register (%got=%s15) | 100 // |----------------------------------------------| <- sp+24 101 // | Thread pointer register (%tp=%s14) | 102 // |----------------------------------------------| <- sp+16 103 // | Return address | 104 // |----------------------------------------------| <- sp+8 105 // | Frame pointer | 106 // |----------------------------------------------| <- sp+0 107 // 108 // NOTE: This description is based on VE ABI and description in 109 // AArch64FrameLowering.cpp. Thanks a lot. 110 //===----------------------------------------------------------------------===// 111 112 #include "VEFrameLowering.h" 113 #include "VEInstrInfo.h" 114 #include "VEMachineFunctionInfo.h" 115 #include "VESubtarget.h" 116 #include "llvm/CodeGen/MachineFrameInfo.h" 117 #include "llvm/CodeGen/MachineFunction.h" 118 #include "llvm/CodeGen/MachineInstrBuilder.h" 119 #include "llvm/CodeGen/MachineModuleInfo.h" 120 #include "llvm/CodeGen/MachineRegisterInfo.h" 121 #include "llvm/CodeGen/RegisterScavenging.h" 122 #include "llvm/IR/DataLayout.h" 123 #include "llvm/IR/Function.h" 124 #include "llvm/Support/CommandLine.h" 125 #include "llvm/Target/TargetOptions.h" 126 #include "llvm/Support/MathExtras.h" 127 128 using namespace llvm; 129 130 VEFrameLowering::VEFrameLowering(const VESubtarget &ST) 131 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(16), 0, 132 Align(16)), 133 STI(ST) {} 134 135 void VEFrameLowering::emitPrologueInsns(MachineFunction &MF, 136 MachineBasicBlock &MBB, 137 MachineBasicBlock::iterator MBBI, 138 uint64_t NumBytes, 139 bool RequireFPUpdate) const { 140 DebugLoc DL; 141 const VEInstrInfo &TII = 142 *static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo()); 143 144 // Insert following codes here as prologue 145 // 146 // st %fp, 0(,%sp) 147 // st %lr, 8(,%sp) 148 // st %got, 24(,%sp) 149 // st %plt, 32(,%sp) 150 // st %s17, 40(,%sp) iff this function is using s17 as BP 151 // or %fp, 0, %sp 152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) 153 .addReg(VE::SX11) 154 .addImm(0) 155 .addImm(0) 156 .addReg(VE::SX9); 157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) 158 .addReg(VE::SX11) 159 .addImm(0) 160 .addImm(8) 161 .addReg(VE::SX10); 162 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) 163 .addReg(VE::SX11) 164 .addImm(0) 165 .addImm(24) 166 .addReg(VE::SX15); 167 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) 168 .addReg(VE::SX11) 169 .addImm(0) 170 .addImm(32) 171 .addReg(VE::SX16); 172 if (hasBP(MF)) 173 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) 174 .addReg(VE::SX11) 175 .addImm(0) 176 .addImm(40) 177 .addReg(VE::SX17); 178 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX9).addReg(VE::SX11).addImm(0); 179 } 180 181 void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF, 182 MachineBasicBlock &MBB, 183 MachineBasicBlock::iterator MBBI, 184 uint64_t NumBytes, 185 bool RequireFPUpdate) const { 186 DebugLoc DL; 187 const VEInstrInfo &TII = 188 *static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo()); 189 190 // Insert following codes here as epilogue 191 // 192 // or %sp, 0, %fp 193 // ld %s17, 40(,%sp) iff this function is using s17 as BP 194 // ld %plt, 32(,%sp) 195 // ld %got, 24(,%sp) 196 // ld %lr, 8(,%sp) 197 // ld %fp, 0(,%sp) 198 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11).addReg(VE::SX9).addImm(0); 199 if (hasBP(MF)) 200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) 201 .addReg(VE::SX11) 202 .addImm(0) 203 .addImm(40); 204 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) 205 .addReg(VE::SX11) 206 .addImm(0) 207 .addImm(32); 208 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) 209 .addReg(VE::SX11) 210 .addImm(0) 211 .addImm(24); 212 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10) 213 .addReg(VE::SX11) 214 .addImm(0) 215 .addImm(8); 216 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9) 217 .addReg(VE::SX11) 218 .addImm(0) 219 .addImm(0); 220 } 221 222 void VEFrameLowering::emitSPAdjustment(MachineFunction &MF, 223 MachineBasicBlock &MBB, 224 MachineBasicBlock::iterator MBBI, 225 int64_t NumBytes, 226 MaybeAlign MaybeAlign) const { 227 DebugLoc DL; 228 const VEInstrInfo &TII = *STI.getInstrInfo(); 229 230 if (NumBytes == 0) { 231 // Nothing to do here. 232 } else if (isInt<7>(NumBytes)) { 233 // adds.l %s11, NumBytes@lo, %s11 234 BuildMI(MBB, MBBI, DL, TII.get(VE::ADDSLri), VE::SX11) 235 .addReg(VE::SX11) 236 .addImm(NumBytes); 237 } else if (isInt<32>(NumBytes)) { 238 // lea %s11, NumBytes@lo(, %s11) 239 BuildMI(MBB, MBBI, DL, TII.get(VE::LEArii), VE::SX11) 240 .addReg(VE::SX11) 241 .addImm(0) 242 .addImm(Lo_32(NumBytes)); 243 } else { 244 // Emit following codes. This clobbers SX13 which we always know is 245 // available here. 246 // lea %s13, NumBytes@lo 247 // and %s13, %s13, (32)0 248 // lea.sl %sp, NumBytes@hi(%s13, %sp) 249 BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13) 250 .addImm(0) 251 .addImm(0) 252 .addImm(Lo_32(NumBytes)); 253 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13) 254 .addReg(VE::SX13) 255 .addImm(M0(32)); 256 BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11) 257 .addReg(VE::SX11) 258 .addReg(VE::SX13) 259 .addImm(Hi_32(NumBytes)); 260 } 261 262 if (MaybeAlign) { 263 // and %sp, %sp, Align-1 264 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11) 265 .addReg(VE::SX11) 266 .addImm(M1(64 - Log2_64(MaybeAlign.valueOrOne().value()))); 267 } 268 } 269 270 void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB, 271 MachineBasicBlock::iterator MBBI) const { 272 DebugLoc DL; 273 const VEInstrInfo &TII = 274 *static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo()); 275 276 // Emit following codes. It is not possible to insert multiple 277 // BasicBlocks in PEI pass, so we emit two pseudo instructions here. 278 // 279 // EXTEND_STACK // pseudo instrcution 280 // EXTEND_STACK_GUARD // pseudo instrcution 281 // 282 // EXTEND_STACK pseudo will be converted by ExpandPostRA pass into 283 // following instructions with multiple basic blocks later. 284 // 285 // thisBB: 286 // brge.l.t %sp, %sl, sinkBB 287 // syscallBB: 288 // ld %s61, 0x18(, %tp) // load param area 289 // or %s62, 0, %s0 // spill the value of %s0 290 // lea %s63, 0x13b // syscall # of grow 291 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0 292 // shm.l %sl, 0x8(%s61) // store old limit at addr:8 293 // shm.l %sp, 0x10(%s61) // store new limit at addr:16 294 // monc // call monitor 295 // or %s0, 0, %s62 // restore the value of %s0 296 // sinkBB: 297 // 298 // EXTEND_STACK_GUARD pseudo will be simply eliminated by ExpandPostRA 299 // pass. This pseudo is required to be at the next of EXTEND_STACK 300 // pseudo in order to protect iteration loop in ExpandPostRA. 301 BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK)); 302 BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK_GUARD)); 303 } 304 305 void VEFrameLowering::emitPrologue(MachineFunction &MF, 306 MachineBasicBlock &MBB) const { 307 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>(); 308 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); 309 MachineFrameInfo &MFI = MF.getFrameInfo(); 310 const VEInstrInfo &TII = *STI.getInstrInfo(); 311 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); 312 MachineBasicBlock::iterator MBBI = MBB.begin(); 313 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); 314 315 // Debug location must be unknown since the first debug location is used 316 // to determine the end of the prologue. 317 DebugLoc DL; 318 319 // FIXME: unfortunately, returning false from canRealignStack 320 // actually just causes needsStackRealignment to return false, 321 // rather than reporting an error, as would be sensible. This is 322 // poor, but fixing that bogosity is going to be a large project. 323 // For now, just see if it's lied, and report an error here. 324 if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign()) 325 report_fatal_error("Function \"" + Twine(MF.getName()) + 326 "\" required " 327 "stack re-alignment, but LLVM couldn't handle it " 328 "(probably because it has a dynamic alloca)."); 329 330 // Get the number of bytes to allocate from the FrameInfo 331 uint64_t NumBytes = MFI.getStackSize(); 332 333 // The VE ABI requires a reserved area at the top of stack as described 334 // in VESubtarget.cpp. So, we adjust it here. 335 NumBytes = STI.getAdjustedFrameSize(NumBytes); 336 337 // Finally, ensure that the size is sufficiently aligned for the 338 // data on the stack. 339 NumBytes = alignTo(NumBytes, MFI.getMaxAlign()); 340 341 // Update stack size with corrected value. 342 MFI.setStackSize(NumBytes); 343 344 if (FuncInfo->isLeafProc()) 345 return; 346 347 // Emit Prologue instructions to save multiple registers. 348 emitPrologueInsns(MF, MBB, MBBI, NumBytes, true); 349 350 // Emit stack adjust instructions 351 MaybeAlign RuntimeAlign = 352 NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : None; 353 emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign); 354 355 if (hasBP(MF)) { 356 // Copy SP to BP. 357 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX17) 358 .addReg(VE::SX11) 359 .addImm(0); 360 } 361 362 // Emit stack extend instructions 363 emitSPExtend(MF, MBB, MBBI); 364 365 Register RegFP = RegInfo.getDwarfRegNum(VE::SX9, true); 366 367 // Emit ".cfi_def_cfa_register 30". 368 unsigned CFIIndex = 369 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, RegFP)); 370 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 371 .addCFIIndex(CFIIndex); 372 373 // Emit ".cfi_window_save". 374 CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr)); 375 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 376 .addCFIIndex(CFIIndex); 377 } 378 379 MachineBasicBlock::iterator VEFrameLowering::eliminateCallFramePseudoInstr( 380 MachineFunction &MF, MachineBasicBlock &MBB, 381 MachineBasicBlock::iterator I) const { 382 if (!hasReservedCallFrame(MF)) { 383 MachineInstr &MI = *I; 384 int64_t Size = MI.getOperand(0).getImm(); 385 if (MI.getOpcode() == VE::ADJCALLSTACKDOWN) 386 Size = -Size; 387 388 if (Size) 389 emitSPAdjustment(MF, MBB, I, Size); 390 } 391 return MBB.erase(I); 392 } 393 394 void VEFrameLowering::emitEpilogue(MachineFunction &MF, 395 MachineBasicBlock &MBB) const { 396 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>(); 397 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 398 MachineFrameInfo &MFI = MF.getFrameInfo(); 399 400 uint64_t NumBytes = MFI.getStackSize(); 401 402 if (FuncInfo->isLeafProc()) 403 return; 404 405 // Emit Epilogue instructions to restore multiple registers. 406 emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true); 407 } 408 409 // hasFP - Return true if the specified function should have a dedicated frame 410 // pointer register. This is true if the function has variable sized allocas 411 // or if frame pointer elimination is disabled. 412 bool VEFrameLowering::hasFP(const MachineFunction &MF) const { 413 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 414 415 const MachineFrameInfo &MFI = MF.getFrameInfo(); 416 return MF.getTarget().Options.DisableFramePointerElim(MF) || 417 RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || 418 MFI.isFrameAddressTaken(); 419 } 420 421 bool VEFrameLowering::hasBP(const MachineFunction &MF) const { 422 const MachineFrameInfo &MFI = MF.getFrameInfo(); 423 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 424 425 return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); 426 } 427 428 StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF, 429 int FI, 430 Register &FrameReg) const { 431 const MachineFrameInfo &MFI = MF.getFrameInfo(); 432 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); 433 bool isFixed = MFI.isFixedObjectIndex(FI); 434 435 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI); 436 437 if (!hasFP(MF)) { 438 // If FP is not used, frame indexies are based on a %sp regiter. 439 FrameReg = VE::SX11; // %sp 440 return StackOffset::getFixed(FrameOffset + 441 MF.getFrameInfo().getStackSize()); 442 } 443 if (RegInfo->needsStackRealignment(MF) && !isFixed) { 444 // If data on stack require realignemnt, frame indexies are based on a %sp 445 // or %s17 (bp) register. If there is a variable sized object, bp is used. 446 if (hasBP(MF)) 447 FrameReg = VE::SX17; // %bp 448 else 449 FrameReg = VE::SX11; // %sp 450 return StackOffset::getFixed(FrameOffset + 451 MF.getFrameInfo().getStackSize()); 452 } 453 // Use %fp by default. 454 FrameReg = RegInfo->getFrameRegister(MF); 455 return StackOffset::getFixed(FrameOffset); 456 } 457 458 bool VEFrameLowering::isLeafProc(MachineFunction &MF) const { 459 460 MachineRegisterInfo &MRI = MF.getRegInfo(); 461 MachineFrameInfo &MFI = MF.getFrameInfo(); 462 463 return !MFI.hasCalls() // No calls 464 && !MRI.isPhysRegUsed(VE::SX18) // Registers within limits 465 // (s18 is first CSR) 466 && !MRI.isPhysRegUsed(VE::SX11) // %sp un-used 467 && !hasFP(MF); // Don't need %fp 468 } 469 470 void VEFrameLowering::determineCalleeSaves(MachineFunction &MF, 471 BitVector &SavedRegs, 472 RegScavenger *RS) const { 473 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 474 const MachineFrameInfo &MFI = MF.getFrameInfo(); 475 476 // Functions having BP or stack objects need to emit prologue and epilogue 477 // to allocate local buffer on the stack. 478 if (isLeafProc(MF) && !hasBP(MF) && !MFI.hasStackObjects()) { 479 VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>(); 480 FuncInfo->setLeafProc(true); 481 } 482 } 483