1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the VE Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/VEMCTargetDesc.h" 14 #include "TargetInfo/VETargetInfo.h" 15 #include "VE.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/Support/TargetRegistry.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "ve-disassembler" 26 27 typedef MCDisassembler::DecodeStatus DecodeStatus; 28 29 namespace { 30 31 /// A disassembler class for VE. 32 class VEDisassembler : public MCDisassembler { 33 public: 34 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 35 : MCDisassembler(STI, Ctx) {} 36 virtual ~VEDisassembler() {} 37 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 39 ArrayRef<uint8_t> Bytes, uint64_t Address, 40 raw_ostream &CStream) const override; 41 }; 42 } // namespace 43 44 static MCDisassembler *createVEDisassembler(const Target &T, 45 const MCSubtargetInfo &STI, 46 MCContext &Ctx) { 47 return new VEDisassembler(STI, Ctx); 48 } 49 50 extern "C" void LLVMInitializeVEDisassembler() { 51 // Register the disassembler. 52 TargetRegistry::RegisterMCDisassembler(getTheVETarget(), 53 createVEDisassembler); 54 } 55 56 static const unsigned I32RegDecoderTable[] = { 57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, 58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, 59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, 60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, 61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34, 62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, 63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, 64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, 65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, 66 VE::SW63}; 67 68 static const unsigned I64RegDecoderTable[] = { 69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, 70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, 71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, 72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, 73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, 74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, 75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, 76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, 77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, 78 VE::SX63}; 79 80 static const unsigned F32RegDecoderTable[] = { 81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, 82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, 83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, 84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, 85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34, 86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, 87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, 88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, 89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, 90 VE::SF63}; 91 92 static const unsigned F128RegDecoderTable[] = { 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7, 94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, 95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, 96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31}; 97 98 static const unsigned MiscRegDecoderTable[] = { 99 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister, 100 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, 101 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, 102 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, 103 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, 104 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, 105 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, 106 VE::PMC12, VE::PMC13, VE::PMC14}; 107 108 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder) { 111 if (RegNo > 63) 112 return MCDisassembler::Fail; 113 unsigned Reg = I32RegDecoderTable[RegNo]; 114 Inst.addOperand(MCOperand::createReg(Reg)); 115 return MCDisassembler::Success; 116 } 117 118 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder) { 121 if (RegNo > 63) 122 return MCDisassembler::Fail; 123 unsigned Reg = I64RegDecoderTable[RegNo]; 124 Inst.addOperand(MCOperand::createReg(Reg)); 125 return MCDisassembler::Success; 126 } 127 128 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder) { 131 if (RegNo > 63) 132 return MCDisassembler::Fail; 133 unsigned Reg = F32RegDecoderTable[RegNo]; 134 Inst.addOperand(MCOperand::createReg(Reg)); 135 return MCDisassembler::Success; 136 } 137 138 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder) { 141 if (RegNo % 2 || RegNo > 63) 142 return MCDisassembler::Fail; 143 unsigned Reg = F128RegDecoderTable[RegNo / 2]; 144 Inst.addOperand(MCOperand::createReg(Reg)); 145 return MCDisassembler::Success; 146 } 147 148 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder) { 151 if (RegNo > 30) 152 return MCDisassembler::Fail; 153 unsigned Reg = MiscRegDecoderTable[RegNo]; 154 if (Reg == VE::NoRegister) 155 return MCDisassembler::Fail; 156 Inst.addOperand(MCOperand::createReg(Reg)); 157 return MCDisassembler::Success; 158 } 159 160 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 165 const void *Decoder); 166 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 173 const void *Decoder); 174 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, 179 uint64_t Address, 180 const void *Decoder); 181 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, 182 uint64_t Address, 183 const void *Decoder); 184 185 #include "VEGenDisassemblerTables.inc" 186 187 /// Read four bytes from the ArrayRef and return 32 bit word. 188 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, 189 uint64_t &Size, uint64_t &Insn, 190 bool IsLittleEndian) { 191 // We want to read exactly 8 Bytes of data. 192 if (Bytes.size() < 8) { 193 Size = 0; 194 return MCDisassembler::Fail; 195 } 196 197 Insn = IsLittleEndian 198 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | 199 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) | 200 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) | 201 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56) 202 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | 203 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | 204 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | 205 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); 206 207 return MCDisassembler::Success; 208 } 209 210 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 211 ArrayRef<uint8_t> Bytes, 212 uint64_t Address, 213 raw_ostream &CStream) const { 214 uint64_t Insn; 215 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 216 DecodeStatus Result = 217 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); 218 if (Result == MCDisassembler::Fail) 219 return MCDisassembler::Fail; 220 221 // Calling the auto-generated decoder function. 222 223 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); 224 225 if (Result != MCDisassembler::Fail) { 226 Size = 8; 227 return Result; 228 } 229 230 return MCDisassembler::Fail; 231 } 232 233 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, 234 const void *Decoder); 235 236 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, 237 const void *Decoder) { 238 unsigned sy = fieldFromInstruction(insn, 40, 7); 239 bool cy = fieldFromInstruction(insn, 47, 1); 240 unsigned sz = fieldFromInstruction(insn, 32, 7); 241 bool cz = fieldFromInstruction(insn, 39, 1); 242 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 243 DecodeStatus status; 244 245 // Decode sz. 246 if (cz) { 247 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 248 if (status != MCDisassembler::Success) 249 return status; 250 } else { 251 MI.addOperand(MCOperand::createImm(0)); 252 } 253 254 // Decode sy. 255 if (cy) { 256 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 257 if (status != MCDisassembler::Success) 258 return status; 259 } else { 260 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 261 } 262 263 // Decode simm32. 264 MI.addOperand(MCOperand::createImm(simm32)); 265 266 return MCDisassembler::Success; 267 } 268 269 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, 270 const void *Decoder) { 271 unsigned sz = fieldFromInstruction(insn, 32, 7); 272 bool cz = fieldFromInstruction(insn, 39, 1); 273 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 274 DecodeStatus status; 275 276 // Decode sz. 277 if (cz) { 278 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 279 if (status != MCDisassembler::Success) 280 return status; 281 } else { 282 MI.addOperand(MCOperand::createImm(0)); 283 } 284 285 // Decode simm32. 286 MI.addOperand(MCOperand::createImm(simm32)); 287 288 return MCDisassembler::Success; 289 } 290 291 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, 292 const void *Decoder, bool isLoad, 293 DecodeFunc DecodeSX) { 294 unsigned sx = fieldFromInstruction(insn, 48, 7); 295 296 DecodeStatus status; 297 if (isLoad) { 298 status = DecodeSX(MI, sx, Address, Decoder); 299 if (status != MCDisassembler::Success) 300 return status; 301 } 302 303 status = DecodeASX(MI, insn, Address, Decoder); 304 if (status != MCDisassembler::Success) 305 return status; 306 307 if (!isLoad) { 308 status = DecodeSX(MI, sx, Address, Decoder); 309 if (status != MCDisassembler::Success) 310 return status; 311 } 312 return MCDisassembler::Success; 313 } 314 315 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 316 const void *Decoder) { 317 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); 318 } 319 320 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 321 uint64_t Address, const void *Decoder) { 322 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); 323 } 324 325 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 326 const void *Decoder) { 327 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 328 } 329 330 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 331 uint64_t Address, const void *Decoder) { 332 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); 333 } 334 335 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 336 const void *Decoder) { 337 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); 338 } 339 340 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 341 uint64_t Address, const void *Decoder) { 342 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); 343 } 344 345 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 346 const void *Decoder) { 347 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 348 } 349 350 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, 351 const void *Decoder) { 352 uint64_t tgt = SignExtend64<7>(insn); 353 MI.addOperand(MCOperand::createImm(tgt)); 354 return MCDisassembler::Success; 355 } 356 357 static bool isIntegerBCKind(MCInst &MI) { 358 359 #define BCm_kind(NAME) \ 360 case NAME##rri: \ 361 case NAME##rzi: \ 362 case NAME##iri: \ 363 case NAME##izi: \ 364 case NAME##rri_nt: \ 365 case NAME##rzi_nt: \ 366 case NAME##iri_nt: \ 367 case NAME##izi_nt: \ 368 case NAME##rri_t: \ 369 case NAME##rzi_t: \ 370 case NAME##iri_t: \ 371 case NAME##izi_t: 372 373 #define BCRm_kind(NAME) \ 374 case NAME##rr: \ 375 case NAME##ir: \ 376 case NAME##rr_nt: \ 377 case NAME##ir_nt: \ 378 case NAME##rr_t: \ 379 case NAME##ir_t: 380 381 { 382 using namespace llvm::VE; 383 switch (MI.getOpcode()) { 384 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL) 385 BCRm_kind(BRCFW) return true; 386 } 387 } 388 #undef BCm_kind 389 390 return false; 391 } 392 393 // Decode CC Operand field. 394 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, 395 const void *Decoder) { 396 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 397 return MCDisassembler::Success; 398 } 399 400 // Decode branch condition instruction and CCOperand field in it. 401 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, 402 uint64_t Address, 403 const void *Decoder) { 404 unsigned cf = fieldFromInstruction(insn, 48, 4); 405 bool cy = fieldFromInstruction(insn, 47, 1); 406 unsigned sy = fieldFromInstruction(insn, 40, 7); 407 408 // Decode cf. 409 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 410 411 // Decode sy. 412 DecodeStatus status; 413 if (cy) { 414 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 415 if (status != MCDisassembler::Success) 416 return status; 417 } else { 418 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 419 } 420 421 // Decode MEMri. 422 return DecodeAS(MI, insn, Address, Decoder); 423 } 424 425 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, 426 uint64_t Address, 427 const void *Decoder) { 428 // Decode MEMri. 429 return DecodeAS(MI, insn, Address, Decoder); 430 } 431