1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the VE Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/VEMCTargetDesc.h" 14 #include "TargetInfo/VETargetInfo.h" 15 #include "VE.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/Support/TargetRegistry.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "ve-disassembler" 26 27 typedef MCDisassembler::DecodeStatus DecodeStatus; 28 29 namespace { 30 31 /// A disassembler class for VE. 32 class VEDisassembler : public MCDisassembler { 33 public: 34 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 35 : MCDisassembler(STI, Ctx) {} 36 virtual ~VEDisassembler() {} 37 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 39 ArrayRef<uint8_t> Bytes, uint64_t Address, 40 raw_ostream &CStream) const override; 41 }; 42 } // namespace 43 44 static MCDisassembler *createVEDisassembler(const Target &T, 45 const MCSubtargetInfo &STI, 46 MCContext &Ctx) { 47 return new VEDisassembler(STI, Ctx); 48 } 49 50 extern "C" void LLVMInitializeVEDisassembler() { 51 // Register the disassembler. 52 TargetRegistry::RegisterMCDisassembler(getTheVETarget(), 53 createVEDisassembler); 54 } 55 56 static const unsigned I32RegDecoderTable[] = { 57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, 58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, 59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, 60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, 61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34, 62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, 63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, 64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, 65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, 66 VE::SW63}; 67 68 static const unsigned I64RegDecoderTable[] = { 69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, 70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, 71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, 72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, 73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, 74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, 75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, 76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, 77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, 78 VE::SX63}; 79 80 static const unsigned F32RegDecoderTable[] = { 81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, 82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, 83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, 84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, 85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34, 86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, 87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, 88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, 89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, 90 VE::SF63}; 91 92 static const unsigned F128RegDecoderTable[] = { 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7, 94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, 95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, 96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31}; 97 98 static const unsigned MiscRegDecoderTable[] = { 99 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister, 100 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, 101 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, 102 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, 103 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, 104 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, 105 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, 106 VE::PMC12, VE::PMC13, VE::PMC14}; 107 108 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder) { 111 if (RegNo > 63) 112 return MCDisassembler::Fail; 113 unsigned Reg = I32RegDecoderTable[RegNo]; 114 Inst.addOperand(MCOperand::createReg(Reg)); 115 return MCDisassembler::Success; 116 } 117 118 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder) { 121 if (RegNo > 63) 122 return MCDisassembler::Fail; 123 unsigned Reg = I64RegDecoderTable[RegNo]; 124 Inst.addOperand(MCOperand::createReg(Reg)); 125 return MCDisassembler::Success; 126 } 127 128 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder) { 131 if (RegNo > 63) 132 return MCDisassembler::Fail; 133 unsigned Reg = F32RegDecoderTable[RegNo]; 134 Inst.addOperand(MCOperand::createReg(Reg)); 135 return MCDisassembler::Success; 136 } 137 138 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder) { 141 if (RegNo % 2 || RegNo > 63) 142 return MCDisassembler::Fail; 143 unsigned Reg = F128RegDecoderTable[RegNo / 2]; 144 Inst.addOperand(MCOperand::createReg(Reg)); 145 return MCDisassembler::Success; 146 } 147 148 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder) { 151 if (RegNo > 30) 152 return MCDisassembler::Fail; 153 unsigned Reg = MiscRegDecoderTable[RegNo]; 154 if (Reg == VE::NoRegister) 155 return MCDisassembler::Fail; 156 Inst.addOperand(MCOperand::createReg(Reg)); 157 return MCDisassembler::Success; 158 } 159 160 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 167 const void *Decoder); 168 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 171 const void *Decoder); 172 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address, 183 const void *Decoder); 184 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 187 const void *Decoder); 188 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, 189 const void *Decoder); 190 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, 193 uint64_t Address, 194 const void *Decoder); 195 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, 196 uint64_t Address, 197 const void *Decoder); 198 199 #include "VEGenDisassemblerTables.inc" 200 201 /// Read four bytes from the ArrayRef and return 32 bit word. 202 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, 203 uint64_t &Size, uint64_t &Insn, 204 bool IsLittleEndian) { 205 // We want to read exactly 8 Bytes of data. 206 if (Bytes.size() < 8) { 207 Size = 0; 208 return MCDisassembler::Fail; 209 } 210 211 Insn = IsLittleEndian 212 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | 213 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) | 214 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) | 215 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56) 216 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | 217 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | 218 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | 219 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); 220 221 return MCDisassembler::Success; 222 } 223 224 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 225 ArrayRef<uint8_t> Bytes, 226 uint64_t Address, 227 raw_ostream &CStream) const { 228 uint64_t Insn; 229 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 230 DecodeStatus Result = 231 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); 232 if (Result == MCDisassembler::Fail) 233 return MCDisassembler::Fail; 234 235 // Calling the auto-generated decoder function. 236 237 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); 238 239 if (Result != MCDisassembler::Fail) { 240 Size = 8; 241 return Result; 242 } 243 244 return MCDisassembler::Fail; 245 } 246 247 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, 248 const void *Decoder); 249 250 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, 251 const void *Decoder) { 252 unsigned sy = fieldFromInstruction(insn, 40, 7); 253 bool cy = fieldFromInstruction(insn, 47, 1); 254 unsigned sz = fieldFromInstruction(insn, 32, 7); 255 bool cz = fieldFromInstruction(insn, 39, 1); 256 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 257 DecodeStatus status; 258 259 // Decode sz. 260 if (cz) { 261 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 262 if (status != MCDisassembler::Success) 263 return status; 264 } else { 265 MI.addOperand(MCOperand::createImm(0)); 266 } 267 268 // Decode sy. 269 if (cy) { 270 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 271 if (status != MCDisassembler::Success) 272 return status; 273 } else { 274 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 275 } 276 277 // Decode simm32. 278 MI.addOperand(MCOperand::createImm(simm32)); 279 280 return MCDisassembler::Success; 281 } 282 283 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, 284 const void *Decoder) { 285 unsigned sz = fieldFromInstruction(insn, 32, 7); 286 bool cz = fieldFromInstruction(insn, 39, 1); 287 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 288 DecodeStatus status; 289 290 // Decode sz. 291 if (cz) { 292 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 293 if (status != MCDisassembler::Success) 294 return status; 295 } else { 296 MI.addOperand(MCOperand::createImm(0)); 297 } 298 299 // Decode simm32. 300 MI.addOperand(MCOperand::createImm(simm32)); 301 302 return MCDisassembler::Success; 303 } 304 305 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, 306 const void *Decoder, bool isLoad, 307 DecodeFunc DecodeSX) { 308 unsigned sx = fieldFromInstruction(insn, 48, 7); 309 310 DecodeStatus status; 311 if (isLoad) { 312 status = DecodeSX(MI, sx, Address, Decoder); 313 if (status != MCDisassembler::Success) 314 return status; 315 } 316 317 status = DecodeASX(MI, insn, Address, Decoder); 318 if (status != MCDisassembler::Success) 319 return status; 320 321 if (!isLoad) { 322 status = DecodeSX(MI, sx, Address, Decoder); 323 if (status != MCDisassembler::Success) 324 return status; 325 } 326 return MCDisassembler::Success; 327 } 328 329 static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address, 330 const void *Decoder, bool isLoad, 331 DecodeFunc DecodeSX) { 332 unsigned sx = fieldFromInstruction(insn, 48, 7); 333 334 DecodeStatus status; 335 if (isLoad) { 336 status = DecodeSX(MI, sx, Address, Decoder); 337 if (status != MCDisassembler::Success) 338 return status; 339 } 340 341 status = DecodeAS(MI, insn, Address, Decoder); 342 if (status != MCDisassembler::Success) 343 return status; 344 345 if (!isLoad) { 346 status = DecodeSX(MI, sx, Address, Decoder); 347 if (status != MCDisassembler::Success) 348 return status; 349 } 350 return MCDisassembler::Success; 351 } 352 353 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 354 const void *Decoder) { 355 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); 356 } 357 358 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 359 uint64_t Address, const void *Decoder) { 360 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); 361 } 362 363 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 364 const void *Decoder) { 365 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 366 } 367 368 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 369 uint64_t Address, const void *Decoder) { 370 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); 371 } 372 373 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 374 const void *Decoder) { 375 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); 376 } 377 378 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 379 uint64_t Address, const void *Decoder) { 380 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); 381 } 382 383 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, 384 uint64_t Address, const void *Decoder) { 385 return DecodeMemAS(Inst, insn, Address, Decoder, true, 386 DecodeI64RegisterClass); 387 } 388 389 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, 390 uint64_t Address, const void *Decoder) { 391 return DecodeMemAS(Inst, insn, Address, Decoder, false, 392 DecodeI64RegisterClass); 393 } 394 395 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, 396 const void *Decoder, bool isImmOnly, bool isUImm, 397 DecodeFunc DecodeSX) { 398 unsigned sx = fieldFromInstruction(insn, 48, 7); 399 bool cy = fieldFromInstruction(insn, 47, 1); 400 unsigned sy = fieldFromInstruction(insn, 40, 7); 401 402 // Add $sx. 403 DecodeStatus status; 404 status = DecodeSX(MI, sx, Address, Decoder); 405 if (status != MCDisassembler::Success) 406 return status; 407 408 // Add $disp($sz). 409 status = DecodeAS(MI, insn, Address, Decoder); 410 if (status != MCDisassembler::Success) 411 return status; 412 413 // Add $sy. 414 if (cy && !isImmOnly) { 415 status = DecodeSX(MI, sy, Address, Decoder); 416 if (status != MCDisassembler::Success) 417 return status; 418 } else { 419 if (isUImm) 420 MI.addOperand(MCOperand::createImm(sy)); 421 else 422 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 423 } 424 425 // Add $sd. 426 status = DecodeSX(MI, sx, Address, Decoder); 427 if (status != MCDisassembler::Success) 428 return status; 429 430 return MCDisassembler::Success; 431 } 432 433 static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, 434 const void *Decoder) { 435 return DecodeCAS(MI, insn, Address, Decoder, false, true, 436 DecodeI64RegisterClass); 437 } 438 439 static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, 440 const void *Decoder) { 441 return DecodeCAS(MI, insn, Address, Decoder, false, true, 442 DecodeI32RegisterClass); 443 } 444 445 static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, 446 const void *Decoder) { 447 return DecodeCAS(MI, insn, Address, Decoder, false, false, 448 DecodeI64RegisterClass); 449 } 450 451 static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, 452 const void *Decoder) { 453 return DecodeCAS(MI, insn, Address, Decoder, false, false, 454 DecodeI32RegisterClass); 455 } 456 457 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 458 const void *Decoder) { 459 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 460 } 461 462 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, 463 const void *Decoder) { 464 uint64_t tgt = SignExtend64<7>(insn); 465 MI.addOperand(MCOperand::createImm(tgt)); 466 return MCDisassembler::Success; 467 } 468 469 static bool isIntegerBCKind(MCInst &MI) { 470 471 #define BCm_kind(NAME) \ 472 case NAME##rri: \ 473 case NAME##rzi: \ 474 case NAME##iri: \ 475 case NAME##izi: \ 476 case NAME##rri_nt: \ 477 case NAME##rzi_nt: \ 478 case NAME##iri_nt: \ 479 case NAME##izi_nt: \ 480 case NAME##rri_t: \ 481 case NAME##rzi_t: \ 482 case NAME##iri_t: \ 483 case NAME##izi_t: 484 485 #define BCRm_kind(NAME) \ 486 case NAME##rr: \ 487 case NAME##ir: \ 488 case NAME##rr_nt: \ 489 case NAME##ir_nt: \ 490 case NAME##rr_t: \ 491 case NAME##ir_t: 492 493 { 494 using namespace llvm::VE; 495 switch (MI.getOpcode()) { 496 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL) 497 BCRm_kind(BRCFW) return true; 498 } 499 } 500 #undef BCm_kind 501 502 return false; 503 } 504 505 // Decode CC Operand field. 506 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, 507 const void *Decoder) { 508 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 509 return MCDisassembler::Success; 510 } 511 512 // Decode branch condition instruction and CCOperand field in it. 513 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, 514 uint64_t Address, 515 const void *Decoder) { 516 unsigned cf = fieldFromInstruction(insn, 48, 4); 517 bool cy = fieldFromInstruction(insn, 47, 1); 518 unsigned sy = fieldFromInstruction(insn, 40, 7); 519 520 // Decode cf. 521 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 522 523 // Decode sy. 524 DecodeStatus status; 525 if (cy) { 526 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 527 if (status != MCDisassembler::Success) 528 return status; 529 } else { 530 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 531 } 532 533 // Decode MEMri. 534 return DecodeAS(MI, insn, Address, Decoder); 535 } 536 537 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, 538 uint64_t Address, 539 const void *Decoder) { 540 // Decode MEMri. 541 return DecodeAS(MI, insn, Address, Decoder); 542 } 543