1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the VE Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/VEMCTargetDesc.h"
14 #include "TargetInfo/VETargetInfo.h"
15 #include "VE.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/TargetRegistry.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "ve-disassembler"
26 
27 typedef MCDisassembler::DecodeStatus DecodeStatus;
28 
29 namespace {
30 
31 /// A disassembler class for VE.
32 class VEDisassembler : public MCDisassembler {
33 public:
34   VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
35       : MCDisassembler(STI, Ctx) {}
36   virtual ~VEDisassembler() {}
37 
38   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39                               ArrayRef<uint8_t> Bytes, uint64_t Address,
40                               raw_ostream &CStream) const override;
41 };
42 } // namespace
43 
44 static MCDisassembler *createVEDisassembler(const Target &T,
45                                             const MCSubtargetInfo &STI,
46                                             MCContext &Ctx) {
47   return new VEDisassembler(STI, Ctx);
48 }
49 
50 extern "C" void LLVMInitializeVEDisassembler() {
51   // Register the disassembler.
52   TargetRegistry::RegisterMCDisassembler(getTheVETarget(),
53                                          createVEDisassembler);
54 }
55 
56 static const unsigned I32RegDecoderTable[] = {
57     VE::SW0,  VE::SW1,  VE::SW2,  VE::SW3,  VE::SW4,  VE::SW5,  VE::SW6,
58     VE::SW7,  VE::SW8,  VE::SW9,  VE::SW10, VE::SW11, VE::SW12, VE::SW13,
59     VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
60     VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
61     VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
62     VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
63     VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
64     VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
65     VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
66     VE::SW63};
67 
68 static const unsigned I64RegDecoderTable[] = {
69     VE::SX0,  VE::SX1,  VE::SX2,  VE::SX3,  VE::SX4,  VE::SX5,  VE::SX6,
70     VE::SX7,  VE::SX8,  VE::SX9,  VE::SX10, VE::SX11, VE::SX12, VE::SX13,
71     VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,
72     VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,
73     VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,
74     VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,
75     VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,
76     VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,
77     VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,
78     VE::SX63};
79 
80 static const unsigned F32RegDecoderTable[] = {
81     VE::SF0,  VE::SF1,  VE::SF2,  VE::SF3,  VE::SF4,  VE::SF5,  VE::SF6,
82     VE::SF7,  VE::SF8,  VE::SF9,  VE::SF10, VE::SF11, VE::SF12, VE::SF13,
83     VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
84     VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
85     VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
86     VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
87     VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
88     VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
89     VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
90     VE::SF63};
91 
92 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
93                                            uint64_t Address,
94                                            const void *Decoder) {
95   if (RegNo > 63)
96     return MCDisassembler::Fail;
97   unsigned Reg = I32RegDecoderTable[RegNo];
98   Inst.addOperand(MCOperand::createReg(Reg));
99   return MCDisassembler::Success;
100 }
101 
102 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo,
103                                            uint64_t Address,
104                                            const void *Decoder) {
105   if (RegNo > 63)
106     return MCDisassembler::Fail;
107   unsigned Reg = I64RegDecoderTable[RegNo];
108   Inst.addOperand(MCOperand::createReg(Reg));
109   return MCDisassembler::Success;
110 }
111 
112 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
113                                            uint64_t Address,
114                                            const void *Decoder) {
115   if (RegNo > 63)
116     return MCDisassembler::Fail;
117   unsigned Reg = F32RegDecoderTable[RegNo];
118   Inst.addOperand(MCOperand::createReg(Reg));
119   return MCDisassembler::Success;
120 }
121 
122 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
123                                   const void *Decoder);
124 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
125                                    uint64_t Address, const void *Decoder);
126 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
127                                   const void *Decoder);
128 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
129                                    uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
131                                   const void *Decoder);
132 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
133                                    uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
135                                 const void *Decoder);
136 
137 #include "VEGenDisassemblerTables.inc"
138 
139 /// Read four bytes from the ArrayRef and return 32 bit word.
140 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
141                                       uint64_t &Size, uint64_t &Insn,
142                                       bool IsLittleEndian) {
143   // We want to read exactly 8 Bytes of data.
144   if (Bytes.size() < 8) {
145     Size = 0;
146     return MCDisassembler::Fail;
147   }
148 
149   Insn = IsLittleEndian
150              ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
151                    ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) |
152                    ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) |
153                    ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56)
154              : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) |
155                    ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) |
156                    ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) |
157                    ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56);
158 
159   return MCDisassembler::Success;
160 }
161 
162 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
163                                             ArrayRef<uint8_t> Bytes,
164                                             uint64_t Address,
165                                             raw_ostream &CStream) const {
166   uint64_t Insn;
167   bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
168   DecodeStatus Result =
169       readInstruction64(Bytes, Address, Size, Insn, isLittleEndian);
170   if (Result == MCDisassembler::Fail)
171     return MCDisassembler::Fail;
172 
173   // Calling the auto-generated decoder function.
174 
175   Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI);
176 
177   if (Result != MCDisassembler::Fail) {
178     Size = 8;
179     return Result;
180   }
181 
182   return MCDisassembler::Fail;
183 }
184 
185 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address,
186                                    const void *Decoder);
187 
188 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
189                               const void *Decoder) {
190   unsigned sy = fieldFromInstruction(insn, 40, 7);
191   bool cy = fieldFromInstruction(insn, 47, 1);
192   unsigned sz = fieldFromInstruction(insn, 32, 7);
193   bool cz = fieldFromInstruction(insn, 39, 1);
194   uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
195   DecodeStatus status;
196 
197   // Decode sz.
198   if (cz) {
199     status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
200     if (status != MCDisassembler::Success)
201       return status;
202   } else {
203     MI.addOperand(MCOperand::createImm(0));
204   }
205 
206   // Decode sy.
207   if (cy) {
208     status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
209     if (status != MCDisassembler::Success)
210       return status;
211   } else {
212     MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
213   }
214 
215   // Decode simm32.
216   MI.addOperand(MCOperand::createImm(simm32));
217 
218   return MCDisassembler::Success;
219 }
220 
221 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
222                               const void *Decoder, bool isLoad,
223                               DecodeFunc DecodeSX) {
224   unsigned sx = fieldFromInstruction(insn, 48, 7);
225 
226   DecodeStatus status;
227   if (isLoad) {
228     status = DecodeSX(MI, sx, Address, Decoder);
229     if (status != MCDisassembler::Success)
230       return status;
231   }
232 
233   status = DecodeASX(MI, insn, Address, Decoder);
234   if (status != MCDisassembler::Success)
235     return status;
236 
237   if (!isLoad) {
238     status = DecodeSX(MI, sx, Address, Decoder);
239     if (status != MCDisassembler::Success)
240       return status;
241   }
242   return MCDisassembler::Success;
243 }
244 
245 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
246                                   const void *Decoder) {
247   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
248 }
249 
250 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
251                                    uint64_t Address, const void *Decoder) {
252   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);
253 }
254 
255 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
256                                   const void *Decoder) {
257   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
258 }
259 
260 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
261                                    uint64_t Address, const void *Decoder) {
262   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass);
263 }
264 
265 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
266                                   const void *Decoder) {
267   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);
268 }
269 
270 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
271                                    uint64_t Address, const void *Decoder) {
272   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
273 }
274 
275 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,
276                                 const void *Decoder) {
277   uint64_t tgt = SignExtend64<7>(insn);
278   MI.addOperand(MCOperand::createImm(tgt));
279   return MCDisassembler::Success;
280 }
281