1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the VE Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/VEMCTargetDesc.h" 14 #include "TargetInfo/VETargetInfo.h" 15 #include "VE.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/Support/TargetRegistry.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "ve-disassembler" 26 27 typedef MCDisassembler::DecodeStatus DecodeStatus; 28 29 namespace { 30 31 /// A disassembler class for VE. 32 class VEDisassembler : public MCDisassembler { 33 public: 34 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 35 : MCDisassembler(STI, Ctx) {} 36 virtual ~VEDisassembler() {} 37 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 39 ArrayRef<uint8_t> Bytes, uint64_t Address, 40 raw_ostream &CStream) const override; 41 }; 42 } // namespace 43 44 static MCDisassembler *createVEDisassembler(const Target &T, 45 const MCSubtargetInfo &STI, 46 MCContext &Ctx) { 47 return new VEDisassembler(STI, Ctx); 48 } 49 50 extern "C" void LLVMInitializeVEDisassembler() { 51 // Register the disassembler. 52 TargetRegistry::RegisterMCDisassembler(getTheVETarget(), 53 createVEDisassembler); 54 } 55 56 static const unsigned I32RegDecoderTable[] = { 57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, 58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, 59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, 60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, 61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34, 62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, 63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, 64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, 65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, 66 VE::SW63}; 67 68 static const unsigned I64RegDecoderTable[] = { 69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, 70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, 71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, 72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, 73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, 74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, 75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, 76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, 77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, 78 VE::SX63}; 79 80 static const unsigned F32RegDecoderTable[] = { 81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, 82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, 83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, 84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, 85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34, 86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, 87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, 88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, 89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, 90 VE::SF63}; 91 92 static const unsigned MiscRegDecoderTable[] = { 93 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister, 94 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, 95 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, 96 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, 97 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, 98 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, 99 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, 100 VE::PMC12, VE::PMC13, VE::PMC14}; 101 102 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder) { 105 if (RegNo > 63) 106 return MCDisassembler::Fail; 107 unsigned Reg = I32RegDecoderTable[RegNo]; 108 Inst.addOperand(MCOperand::createReg(Reg)); 109 return MCDisassembler::Success; 110 } 111 112 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder) { 115 if (RegNo > 63) 116 return MCDisassembler::Fail; 117 unsigned Reg = I64RegDecoderTable[RegNo]; 118 Inst.addOperand(MCOperand::createReg(Reg)); 119 return MCDisassembler::Success; 120 } 121 122 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder) { 125 if (RegNo > 63) 126 return MCDisassembler::Fail; 127 unsigned Reg = F32RegDecoderTable[RegNo]; 128 Inst.addOperand(MCOperand::createReg(Reg)); 129 return MCDisassembler::Success; 130 } 131 132 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder) { 135 if (RegNo > 30) 136 return MCDisassembler::Fail; 137 unsigned Reg = MiscRegDecoderTable[RegNo]; 138 if (Reg == VE::NoRegister) 139 return MCDisassembler::Fail; 140 Inst.addOperand(MCOperand::createReg(Reg)); 141 return MCDisassembler::Success; 142 } 143 144 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 153 const void *Decoder); 154 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, 159 const void *Decoder); 160 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, 163 uint64_t Address, 164 const void *Decoder); 165 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, 166 uint64_t Address, 167 const void *Decoder); 168 169 #include "VEGenDisassemblerTables.inc" 170 171 /// Read four bytes from the ArrayRef and return 32 bit word. 172 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, 173 uint64_t &Size, uint64_t &Insn, 174 bool IsLittleEndian) { 175 // We want to read exactly 8 Bytes of data. 176 if (Bytes.size() < 8) { 177 Size = 0; 178 return MCDisassembler::Fail; 179 } 180 181 Insn = IsLittleEndian 182 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | 183 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) | 184 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) | 185 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56) 186 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | 187 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | 188 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | 189 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); 190 191 return MCDisassembler::Success; 192 } 193 194 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 195 ArrayRef<uint8_t> Bytes, 196 uint64_t Address, 197 raw_ostream &CStream) const { 198 uint64_t Insn; 199 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 200 DecodeStatus Result = 201 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); 202 if (Result == MCDisassembler::Fail) 203 return MCDisassembler::Fail; 204 205 // Calling the auto-generated decoder function. 206 207 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); 208 209 if (Result != MCDisassembler::Fail) { 210 Size = 8; 211 return Result; 212 } 213 214 return MCDisassembler::Fail; 215 } 216 217 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, 221 const void *Decoder) { 222 unsigned sy = fieldFromInstruction(insn, 40, 7); 223 bool cy = fieldFromInstruction(insn, 47, 1); 224 unsigned sz = fieldFromInstruction(insn, 32, 7); 225 bool cz = fieldFromInstruction(insn, 39, 1); 226 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 227 DecodeStatus status; 228 229 // Decode sz. 230 if (cz) { 231 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 232 if (status != MCDisassembler::Success) 233 return status; 234 } else { 235 MI.addOperand(MCOperand::createImm(0)); 236 } 237 238 // Decode sy. 239 if (cy) { 240 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 241 if (status != MCDisassembler::Success) 242 return status; 243 } else { 244 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 245 } 246 247 // Decode simm32. 248 MI.addOperand(MCOperand::createImm(simm32)); 249 250 return MCDisassembler::Success; 251 } 252 253 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, 254 const void *Decoder) { 255 unsigned sz = fieldFromInstruction(insn, 32, 7); 256 bool cz = fieldFromInstruction(insn, 39, 1); 257 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 258 DecodeStatus status; 259 260 // Decode sz. 261 if (cz) { 262 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 263 if (status != MCDisassembler::Success) 264 return status; 265 } else { 266 MI.addOperand(MCOperand::createImm(0)); 267 } 268 269 // Decode simm32. 270 MI.addOperand(MCOperand::createImm(simm32)); 271 272 return MCDisassembler::Success; 273 } 274 275 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, 276 const void *Decoder, bool isLoad, 277 DecodeFunc DecodeSX) { 278 unsigned sx = fieldFromInstruction(insn, 48, 7); 279 280 DecodeStatus status; 281 if (isLoad) { 282 status = DecodeSX(MI, sx, Address, Decoder); 283 if (status != MCDisassembler::Success) 284 return status; 285 } 286 287 status = DecodeASX(MI, insn, Address, Decoder); 288 if (status != MCDisassembler::Success) 289 return status; 290 291 if (!isLoad) { 292 status = DecodeSX(MI, sx, Address, Decoder); 293 if (status != MCDisassembler::Success) 294 return status; 295 } 296 return MCDisassembler::Success; 297 } 298 299 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 300 const void *Decoder) { 301 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); 302 } 303 304 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 305 uint64_t Address, const void *Decoder) { 306 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); 307 } 308 309 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 310 const void *Decoder) { 311 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 312 } 313 314 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 315 uint64_t Address, const void *Decoder) { 316 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); 317 } 318 319 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 320 const void *Decoder) { 321 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); 322 } 323 324 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 325 uint64_t Address, const void *Decoder) { 326 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); 327 } 328 329 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 330 const void *Decoder) { 331 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 332 } 333 334 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, 335 const void *Decoder) { 336 uint64_t tgt = SignExtend64<7>(insn); 337 MI.addOperand(MCOperand::createImm(tgt)); 338 return MCDisassembler::Success; 339 } 340 341 static bool isIntegerBCKind(MCInst &MI) { 342 343 #define BCm_kind(NAME) \ 344 case NAME##rri: \ 345 case NAME##rzi: \ 346 case NAME##iri: \ 347 case NAME##izi: \ 348 case NAME##rri_nt: \ 349 case NAME##rzi_nt: \ 350 case NAME##iri_nt: \ 351 case NAME##izi_nt: \ 352 case NAME##rri_t: \ 353 case NAME##rzi_t: \ 354 case NAME##iri_t: \ 355 case NAME##izi_t: 356 357 #define BCRm_kind(NAME) \ 358 case NAME##rr: \ 359 case NAME##ir: \ 360 case NAME##rr_nt: \ 361 case NAME##ir_nt: \ 362 case NAME##rr_t: \ 363 case NAME##ir_t: 364 365 { 366 using namespace llvm::VE; 367 switch (MI.getOpcode()) { 368 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL) 369 BCRm_kind(BRCFW) return true; 370 } 371 } 372 #undef BCm_kind 373 374 return false; 375 } 376 377 // Decode CC Operand field. 378 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, 379 const void *Decoder) { 380 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 381 return MCDisassembler::Success; 382 } 383 384 // Decode branch condition instruction and CCOperand field in it. 385 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, 386 uint64_t Address, 387 const void *Decoder) { 388 unsigned cf = fieldFromInstruction(insn, 48, 4); 389 bool cy = fieldFromInstruction(insn, 47, 1); 390 unsigned sy = fieldFromInstruction(insn, 40, 7); 391 392 // Decode cf. 393 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 394 395 // Decode sy. 396 DecodeStatus status; 397 if (cy) { 398 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 399 if (status != MCDisassembler::Success) 400 return status; 401 } else { 402 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 403 } 404 405 // Decode MEMri. 406 return DecodeAS(MI, insn, Address, Decoder); 407 } 408 409 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, 410 uint64_t Address, 411 const void *Decoder) { 412 // Decode MEMri. 413 return DecodeAS(MI, insn, Address, Decoder); 414 } 415