1 //===-- TargetMachine.cpp - General Target Information ---------------------==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the general parts of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/MC/MCAsmInfo.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/TargetOptions.h"
17 #include "llvm/Support/CommandLine.h"
18 using namespace llvm;
19 
20 //---------------------------------------------------------------------------
21 // Command-line options that tend to be useful on more than one back-end.
22 //
23 
24 namespace llvm {
25   bool StrongPHIElim;
26   bool EnableMachineSched;
27   bool HasDivModLibcall;
28   bool AsmVerbosityDefault(false);
29 }
30 
31 static cl::opt<bool>
32 DataSections("fdata-sections",
33   cl::desc("Emit data into separate sections"),
34   cl::init(false));
35 static cl::opt<bool>
36 FunctionSections("ffunction-sections",
37   cl::desc("Emit functions into separate sections"),
38   cl::init(false));
39 
40 /// EnableMachineSched - temporary flag to enable the machine scheduling pass
41 /// until we complete the register allocation pass configuration cleanup.
42 static cl::opt<bool, true>
43 MachineSchedOpt("enable-misched",
44                 cl::desc("Enable the machine instruction scheduling pass."),
45                 cl::location(EnableMachineSched),
46                 cl::init(false), cl::Hidden);
47 
48 //---------------------------------------------------------------------------
49 // TargetMachine Class
50 //
51 
52 TargetMachine::TargetMachine(const Target &T,
53                              StringRef TT, StringRef CPU, StringRef FS,
54                              const TargetOptions &Options)
55   : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS),
56     CodeGenInfo(0), AsmInfo(0),
57     MCRelaxAll(false),
58     MCNoExecStack(false),
59     MCSaveTempLabels(false),
60     MCUseLoc(true),
61     MCUseCFI(true),
62     MCUseDwarfDirectory(false),
63     Options(Options) {
64 }
65 
66 TargetMachine::~TargetMachine() {
67   delete CodeGenInfo;
68   delete AsmInfo;
69 }
70 
71 /// getRelocationModel - Returns the code generation relocation model. The
72 /// choices are static, PIC, and dynamic-no-pic, and target default.
73 Reloc::Model TargetMachine::getRelocationModel() const {
74   if (!CodeGenInfo)
75     return Reloc::Default;
76   return CodeGenInfo->getRelocationModel();
77 }
78 
79 /// getCodeModel - Returns the code model. The choices are small, kernel,
80 /// medium, large, and target default.
81 CodeModel::Model TargetMachine::getCodeModel() const {
82   if (!CodeGenInfo)
83     return CodeModel::Default;
84   return CodeGenInfo->getCodeModel();
85 }
86 
87 /// getOptLevel - Returns the optimization level: None, Less,
88 /// Default, or Aggressive.
89 CodeGenOpt::Level TargetMachine::getOptLevel() const {
90   if (!CodeGenInfo)
91     return CodeGenOpt::Default;
92   return CodeGenInfo->getOptLevel();
93 }
94 
95 bool TargetMachine::getAsmVerbosityDefault() {
96   return AsmVerbosityDefault;
97 }
98 
99 void TargetMachine::setAsmVerbosityDefault(bool V) {
100   AsmVerbosityDefault = V;
101 }
102 
103 bool TargetMachine::getFunctionSections() {
104   return FunctionSections;
105 }
106 
107 bool TargetMachine::getDataSections() {
108   return DataSections;
109 }
110 
111 void TargetMachine::setFunctionSections(bool V) {
112   FunctionSections = V;
113 }
114 
115 void TargetMachine::setDataSections(bool V) {
116   DataSections = V;
117 }
118 
119