1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZTargetMachine.h"
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "SystemZ.h"
12 #include "SystemZMachineScheduler.h"
13 #include "SystemZTargetTransformInfo.h"
14 #include "TargetInfo/SystemZTargetInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Support/CodeGen.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetLoweringObjectFile.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include <string>
29 
30 using namespace llvm;
31 
32 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() {
33   // Register the target.
34   RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
35 }
36 
37 // Determine whether we use the vector ABI.
38 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
39   // We use the vector ABI whenever the vector facility is avaiable.
40   // This is the case by default if CPU is z13 or later, and can be
41   // overridden via "[+-]vector" feature string elements.
42   bool VectorABI = true;
43   bool SoftFloat = false;
44   if (CPU.empty() || CPU == "generic" ||
45       CPU == "z10" || CPU == "z196" || CPU == "zEC12")
46     VectorABI = false;
47 
48   SmallVector<StringRef, 3> Features;
49   FS.split(Features, ',', -1, false /* KeepEmpty */);
50   for (auto &Feature : Features) {
51     if (Feature == "vector" || Feature == "+vector")
52       VectorABI = true;
53     if (Feature == "-vector")
54       VectorABI = false;
55     if (Feature == "soft-float" || Feature == "+soft-float")
56       SoftFloat = true;
57     if (Feature == "-soft-float")
58       SoftFloat = false;
59   }
60 
61   return VectorABI && !SoftFloat;
62 }
63 
64 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
65                                      StringRef FS) {
66   bool VectorABI = UsesVectorABI(CPU, FS);
67   std::string Ret;
68 
69   // Big endian.
70   Ret += "E";
71 
72   // Data mangling.
73   Ret += DataLayout::getManglingComponent(TT);
74 
75   // Make sure that global data has at least 16 bits of alignment by
76   // default, so that we can refer to it using LARL.  We don't have any
77   // special requirements for stack variables though.
78   Ret += "-i1:8:16-i8:8:16";
79 
80   // 64-bit integers are naturally aligned.
81   Ret += "-i64:64";
82 
83   // 128-bit floats are aligned only to 64 bits.
84   Ret += "-f128:64";
85 
86   // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
87   if (VectorABI)
88     Ret += "-v128:64";
89 
90   // We prefer 16 bits of aligned for all globals; see above.
91   Ret += "-a:8:16";
92 
93   // Integer registers are 32 or 64 bits.
94   Ret += "-n32:64";
95 
96   return Ret;
97 }
98 
99 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
100   // Static code is suitable for use in a dynamic executable; there is no
101   // separate DynamicNoPIC model.
102   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
103     return Reloc::Static;
104   return *RM;
105 }
106 
107 // For SystemZ we define the models as follows:
108 //
109 // Small:  BRASL can call any function and will use a stub if necessary.
110 //         Locally-binding symbols will always be in range of LARL.
111 //
112 // Medium: BRASL can call any function and will use a stub if necessary.
113 //         GOT slots and locally-defined text will always be in range
114 //         of LARL, but other symbols might not be.
115 //
116 // Large:  Equivalent to Medium for now.
117 //
118 // Kernel: Equivalent to Medium for now.
119 //
120 // This means that any PIC module smaller than 4GB meets the
121 // requirements of Small, so Small seems like the best default there.
122 //
123 // All symbols bind locally in a non-PIC module, so the choice is less
124 // obvious.  There are two cases:
125 //
126 // - When creating an executable, PLTs and copy relocations allow
127 //   us to treat external symbols as part of the executable.
128 //   Any executable smaller than 4GB meets the requirements of Small,
129 //   so that seems like the best default.
130 //
131 // - When creating JIT code, stubs will be in range of BRASL if the
132 //   image is less than 4GB in size.  GOT entries will likewise be
133 //   in range of LARL.  However, the JIT environment has no equivalent
134 //   of copy relocs, so locally-binding data symbols might not be in
135 //   the range of LARL.  We need the Medium model in that case.
136 static CodeModel::Model
137 getEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
138                              bool JIT) {
139   if (CM) {
140     if (*CM == CodeModel::Tiny)
141       report_fatal_error("Target does not support the tiny CodeModel", false);
142     if (*CM == CodeModel::Kernel)
143       report_fatal_error("Target does not support the kernel CodeModel", false);
144     return *CM;
145   }
146   if (JIT)
147     return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
148   return CodeModel::Small;
149 }
150 
151 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
152                                            StringRef CPU, StringRef FS,
153                                            const TargetOptions &Options,
154                                            Optional<Reloc::Model> RM,
155                                            Optional<CodeModel::Model> CM,
156                                            CodeGenOpt::Level OL, bool JIT)
157     : LLVMTargetMachine(
158           T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
159           getEffectiveRelocModel(RM),
160           getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT),
161           OL),
162       TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
163       Subtarget(TT, std::string(CPU), std::string(FS), *this) {
164   initAsmInfo();
165 }
166 
167 SystemZTargetMachine::~SystemZTargetMachine() = default;
168 
169 namespace {
170 
171 /// SystemZ Code Generator Pass Configuration Options.
172 class SystemZPassConfig : public TargetPassConfig {
173 public:
174   SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
175     : TargetPassConfig(TM, PM) {}
176 
177   SystemZTargetMachine &getSystemZTargetMachine() const {
178     return getTM<SystemZTargetMachine>();
179   }
180 
181   ScheduleDAGInstrs *
182   createPostMachineScheduler(MachineSchedContext *C) const override {
183     return new ScheduleDAGMI(C,
184                              std::make_unique<SystemZPostRASchedStrategy>(C),
185                              /*RemoveKillFlags=*/true);
186   }
187 
188   void addIRPasses() override;
189   bool addInstSelector() override;
190   bool addILPOpts() override;
191   void addPostRewrite() override;
192   void addPostRegAlloc() override;
193   void addPreSched2() override;
194   void addPreEmitPass() override;
195 };
196 
197 } // end anonymous namespace
198 
199 void SystemZPassConfig::addIRPasses() {
200   if (getOptLevel() != CodeGenOpt::None) {
201     if (!getTM<SystemZTargetMachine>().getSubtargetImpl()->hasSoftFloat())
202       addPass(createSystemZTDCPass());
203     addPass(createLoopDataPrefetchPass());
204   }
205 
206   TargetPassConfig::addIRPasses();
207 }
208 
209 bool SystemZPassConfig::addInstSelector() {
210   addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
211 
212  if (getOptLevel() != CodeGenOpt::None)
213     addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
214 
215   return false;
216 }
217 
218 bool SystemZPassConfig::addILPOpts() {
219   addPass(&EarlyIfConverterID);
220   return true;
221 }
222 
223 void SystemZPassConfig::addPostRewrite() {
224   addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
225 }
226 
227 void SystemZPassConfig::addPostRegAlloc() {
228   // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
229   // is not called).
230   if (getOptLevel() == CodeGenOpt::None)
231     addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
232 }
233 
234 void SystemZPassConfig::addPreSched2() {
235   if (getOptLevel() != CodeGenOpt::None)
236     addPass(&IfConverterID);
237 }
238 
239 void SystemZPassConfig::addPreEmitPass() {
240   // Do instruction shortening before compare elimination because some
241   // vector instructions will be shortened into opcodes that compare
242   // elimination recognizes.
243   if (getOptLevel() != CodeGenOpt::None)
244     addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
245 
246   // We eliminate comparisons here rather than earlier because some
247   // transformations can change the set of available CC values and we
248   // generally want those transformations to have priority.  This is
249   // especially true in the commonest case where the result of the comparison
250   // is used by a single in-range branch instruction, since we will then
251   // be able to fuse the compare and the branch instead.
252   //
253   // For example, two-address NILF can sometimes be converted into
254   // three-address RISBLG.  NILF produces a CC value that indicates whether
255   // the low word is zero, but RISBLG does not modify CC at all.  On the
256   // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
257   // The CC value produced by NILL isn't useful for our purposes, but the
258   // value produced by RISBG can be used for any comparison with zero
259   // (not just equality).  So there are some transformations that lose
260   // CC values (while still being worthwhile) and others that happen to make
261   // the CC result more useful than it was originally.
262   //
263   // Another reason is that we only want to use BRANCH ON COUNT in cases
264   // where we know that the count register is not going to be spilled.
265   //
266   // Doing it so late makes it more likely that a register will be reused
267   // between the comparison and the branch, but it isn't clear whether
268   // preventing that would be a win or not.
269   if (getOptLevel() != CodeGenOpt::None)
270     addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
271   addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
272 
273   // Do final scheduling after all other optimizations, to get an
274   // optimal input for the decoder (branch relaxation must happen
275   // after block placement).
276   if (getOptLevel() != CodeGenOpt::None)
277     addPass(&PostMachineSchedulerID);
278 }
279 
280 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
281   return new SystemZPassConfig(*this, PM);
282 }
283 
284 TargetTransformInfo
285 SystemZTargetMachine::getTargetTransformInfo(const Function &F) {
286   return TargetTransformInfo(SystemZTTIImpl(this, F));
287 }
288