1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZTargetMachine.h"
11 #include "SystemZTargetTransformInfo.h"
12 #include "llvm/CodeGen/Passes.h"
13 #include "llvm/Support/TargetRegistry.h"
14 #include "llvm/Transforms/Scalar.h"
15 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
16 
17 using namespace llvm;
18 
19 extern cl::opt<bool> MISchedPostRA;
20 extern "C" void LLVMInitializeSystemZTarget() {
21   // Register the target.
22   RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget);
23 }
24 
25 // Determine whether we use the vector ABI.
26 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
27   // We use the vector ABI whenever the vector facility is avaiable.
28   // This is the case by default if CPU is z13 or later, and can be
29   // overridden via "[+-]vector" feature string elements.
30   bool VectorABI = true;
31   if (CPU.empty() || CPU == "generic" ||
32       CPU == "z10" || CPU == "z196" || CPU == "zEC12")
33     VectorABI = false;
34 
35   SmallVector<StringRef, 3> Features;
36   FS.split(Features, ',', -1, false /* KeepEmpty */);
37   for (auto &Feature : Features) {
38     if (Feature == "vector" || Feature == "+vector")
39       VectorABI = true;
40     if (Feature == "-vector")
41       VectorABI = false;
42   }
43 
44   return VectorABI;
45 }
46 
47 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
48                                      StringRef FS) {
49   bool VectorABI = UsesVectorABI(CPU, FS);
50   std::string Ret = "";
51 
52   // Big endian.
53   Ret += "E";
54 
55   // Data mangling.
56   Ret += DataLayout::getManglingComponent(TT);
57 
58   // Make sure that global data has at least 16 bits of alignment by
59   // default, so that we can refer to it using LARL.  We don't have any
60   // special requirements for stack variables though.
61   Ret += "-i1:8:16-i8:8:16";
62 
63   // 64-bit integers are naturally aligned.
64   Ret += "-i64:64";
65 
66   // 128-bit floats are aligned only to 64 bits.
67   Ret += "-f128:64";
68 
69   // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
70   if (VectorABI)
71     Ret += "-v128:64";
72 
73   // We prefer 16 bits of aligned for all globals; see above.
74   Ret += "-a:8:16";
75 
76   // Integer registers are 32 or 64 bits.
77   Ret += "-n32:64";
78 
79   return Ret;
80 }
81 
82 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
83                                            StringRef CPU, StringRef FS,
84                                            const TargetOptions &Options,
85                                            Reloc::Model RM, CodeModel::Model CM,
86                                            CodeGenOpt::Level OL)
87     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
88                         RM, CM, OL),
89       TLOF(make_unique<TargetLoweringObjectFileELF>()),
90       Subtarget(TT, CPU, FS, *this) {
91   initAsmInfo();
92 }
93 
94 SystemZTargetMachine::~SystemZTargetMachine() {}
95 
96 namespace {
97 /// SystemZ Code Generator Pass Configuration Options.
98 class SystemZPassConfig : public TargetPassConfig {
99 public:
100   SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM)
101     : TargetPassConfig(TM, PM) {}
102 
103   SystemZTargetMachine &getSystemZTargetMachine() const {
104     return getTM<SystemZTargetMachine>();
105   }
106 
107   void addIRPasses() override;
108   bool addInstSelector() override;
109   void addPreSched2() override;
110   void addPreEmitPass() override;
111 };
112 } // end anonymous namespace
113 
114 void SystemZPassConfig::addIRPasses() {
115   TargetPassConfig::addIRPasses();
116 }
117 
118 bool SystemZPassConfig::addInstSelector() {
119   addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
120 
121  if (getOptLevel() != CodeGenOpt::None)
122     addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
123 
124   return false;
125 }
126 
127 void SystemZPassConfig::addPreSched2() {
128   if (getOptLevel() != CodeGenOpt::None)
129     addPass(&IfConverterID);
130 }
131 
132 void SystemZPassConfig::addPreEmitPass() {
133 
134   // Do instruction shortening before compare elimination because some
135   // vector instructions will be shortened into opcodes that compare
136   // elimination recognizes.
137   if (getOptLevel() != CodeGenOpt::None)
138     addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
139 
140   // We eliminate comparisons here rather than earlier because some
141   // transformations can change the set of available CC values and we
142   // generally want those transformations to have priority.  This is
143   // especially true in the commonest case where the result of the comparison
144   // is used by a single in-range branch instruction, since we will then
145   // be able to fuse the compare and the branch instead.
146   //
147   // For example, two-address NILF can sometimes be converted into
148   // three-address RISBLG.  NILF produces a CC value that indicates whether
149   // the low word is zero, but RISBLG does not modify CC at all.  On the
150   // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
151   // The CC value produced by NILL isn't useful for our purposes, but the
152   // value produced by RISBG can be used for any comparison with zero
153   // (not just equality).  So there are some transformations that lose
154   // CC values (while still being worthwhile) and others that happen to make
155   // the CC result more useful than it was originally.
156   //
157   // Another reason is that we only want to use BRANCH ON COUNT in cases
158   // where we know that the count register is not going to be spilled.
159   //
160   // Doing it so late makes it more likely that a register will be reused
161   // between the comparison and the branch, but it isn't clear whether
162   // preventing that would be a win or not.
163   if (getOptLevel() != CodeGenOpt::None)
164     addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
165   addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
166 
167   // Do final scheduling after all other optimizations, to get an
168   // optimal input for the decoder (branch relaxation must happen
169   // after block placement).
170   if (getOptLevel() != CodeGenOpt::None) {
171     if (MISchedPostRA)
172       addPass(&PostMachineSchedulerID);
173     else
174       addPass(&PostRASchedulerID);
175   }
176 }
177 
178 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
179   return new SystemZPassConfig(this, PM);
180 }
181 
182 TargetIRAnalysis SystemZTargetMachine::getTargetIRAnalysis() {
183   return TargetIRAnalysis([this](const Function &F) {
184     return TargetTransformInfo(SystemZTTIImpl(this, F));
185   });
186 }
187