1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This pass tries to replace instructions with shorter forms. For example, 11 // IILF can be replaced with LLILL or LLILH if the constant fits and if the 12 // other 32 bits of the GR64 destination are not live. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "SystemZTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunctionPass.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/LivePhysRegs.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "systemz-shorten-inst" 25 26 namespace { 27 class SystemZShortenInst : public MachineFunctionPass { 28 public: 29 static char ID; 30 SystemZShortenInst(const SystemZTargetMachine &tm); 31 32 const char *getPassName() const override { 33 return "SystemZ Instruction Shortening"; 34 } 35 36 bool processBlock(MachineBasicBlock &MBB); 37 bool runOnMachineFunction(MachineFunction &F) override; 38 MachineFunctionProperties getRequiredProperties() const override { 39 return MachineFunctionProperties().set( 40 MachineFunctionProperties::Property::AllVRegsAllocated); 41 } 42 43 private: 44 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH); 45 bool shortenOn0(MachineInstr &MI, unsigned Opcode); 46 bool shortenOn01(MachineInstr &MI, unsigned Opcode); 47 bool shortenOn001(MachineInstr &MI, unsigned Opcode); 48 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode); 49 bool shortenFPConv(MachineInstr &MI, unsigned Opcode); 50 51 const SystemZInstrInfo *TII; 52 const TargetRegisterInfo *TRI; 53 LivePhysRegs LiveRegs; 54 }; 55 56 char SystemZShortenInst::ID = 0; 57 } // end anonymous namespace 58 59 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) { 60 return new SystemZShortenInst(TM); 61 } 62 63 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm) 64 : MachineFunctionPass(ID), TII(nullptr) {} 65 66 // Tie operands if MI has become a two-address instruction. 67 static void tieOpsIfNeeded(MachineInstr &MI) { 68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 69 !MI.getOperand(0).isTied()) 70 MI.tieOperands(0, 1); 71 } 72 73 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH 74 // are the halfword immediate loads for the same word. Try to use one of them 75 // instead of IIxF. 76 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, 77 unsigned LLIxL, unsigned LLIxH) { 78 unsigned Reg = MI.getOperand(0).getReg(); 79 // The new opcode will clear the other half of the GR64 reg, so 80 // cancel if that is live. 81 unsigned thisSubRegIdx = (SystemZ::GRH32BitRegClass.contains(Reg) ? 82 SystemZ::subreg_h32 : SystemZ::subreg_l32); 83 unsigned otherSubRegIdx = (thisSubRegIdx == SystemZ::subreg_l32 ? 84 SystemZ::subreg_h32 : SystemZ::subreg_l32); 85 unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx, 86 &SystemZ::GR64BitRegClass); 87 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); 88 if (LiveRegs.contains(OtherReg)) 89 return false; 90 91 uint64_t Imm = MI.getOperand(1).getImm(); 92 if (SystemZ::isImmLL(Imm)) { 93 MI.setDesc(TII->get(LLIxL)); 94 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); 95 return true; 96 } 97 if (SystemZ::isImmLH(Imm)) { 98 MI.setDesc(TII->get(LLIxH)); 99 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); 100 MI.getOperand(1).setImm(Imm >> 16); 101 return true; 102 } 103 return false; 104 } 105 106 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding. 107 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { 108 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { 109 MI.setDesc(TII->get(Opcode)); 110 return true; 111 } 112 return false; 113 } 114 115 // Change MI's opcode to Opcode if register operands 0 and 1 have a 116 // 4-bit encoding. 117 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { 118 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && 119 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { 120 MI.setDesc(TII->get(Opcode)); 121 return true; 122 } 123 return false; 124 } 125 126 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a 127 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0 128 // with op 1, if MI becomes 2-address. 129 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { 130 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && 131 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && 132 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) { 133 MI.setDesc(TII->get(Opcode)); 134 tieOpsIfNeeded(MI); 135 return true; 136 } 137 return false; 138 } 139 140 // Calls shortenOn001 if CCLive is false. CC def operand is added in 141 // case of success. 142 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, 143 unsigned Opcode) { 144 if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) { 145 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) 146 .addReg(SystemZ::CC, RegState::ImplicitDefine); 147 return true; 148 } 149 return false; 150 } 151 152 // MI is a vector-style conversion instruction with the operand order: 153 // destination, source, exact-suppress, rounding-mode. If both registers 154 // have a 4-bit encoding then change it to Opcode, which has operand order: 155 // destination, rouding-mode, source, exact-suppress. 156 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { 157 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && 158 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { 159 MachineOperand Dest(MI.getOperand(0)); 160 MachineOperand Src(MI.getOperand(1)); 161 MachineOperand Suppress(MI.getOperand(2)); 162 MachineOperand Mode(MI.getOperand(3)); 163 MI.RemoveOperand(3); 164 MI.RemoveOperand(2); 165 MI.RemoveOperand(1); 166 MI.RemoveOperand(0); 167 MI.setDesc(TII->get(Opcode)); 168 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) 169 .addOperand(Dest) 170 .addOperand(Mode) 171 .addOperand(Src) 172 .addOperand(Suppress); 173 return true; 174 } 175 return false; 176 } 177 178 // Process all instructions in MBB. Return true if something changed. 179 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) { 180 bool Changed = false; 181 182 // Set up the set of live registers at the end of MBB (live out) 183 LiveRegs.clear(); 184 LiveRegs.addLiveOuts(&MBB); 185 186 // Iterate backwards through the block looking for instructions to change. 187 for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) { 188 MachineInstr &MI = *MBBI; 189 switch (MI.getOpcode()) { 190 case SystemZ::IILF: 191 Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH); 192 break; 193 194 case SystemZ::IIHF: 195 Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH); 196 break; 197 198 case SystemZ::WFADB: 199 Changed |= shortenOn001AddCC(MI, SystemZ::ADBR); 200 break; 201 202 case SystemZ::WFDDB: 203 Changed |= shortenOn001(MI, SystemZ::DDBR); 204 break; 205 206 case SystemZ::WFIDB: 207 Changed |= shortenFPConv(MI, SystemZ::FIDBRA); 208 break; 209 210 case SystemZ::WLDEB: 211 Changed |= shortenOn01(MI, SystemZ::LDEBR); 212 break; 213 214 case SystemZ::WLEDB: 215 Changed |= shortenFPConv(MI, SystemZ::LEDBRA); 216 break; 217 218 case SystemZ::WFMDB: 219 Changed |= shortenOn001(MI, SystemZ::MDBR); 220 break; 221 222 case SystemZ::WFLCDB: 223 Changed |= shortenOn01(MI, SystemZ::LCDFR); 224 break; 225 226 case SystemZ::WFLNDB: 227 Changed |= shortenOn01(MI, SystemZ::LNDFR); 228 break; 229 230 case SystemZ::WFLPDB: 231 Changed |= shortenOn01(MI, SystemZ::LPDFR); 232 break; 233 234 case SystemZ::WFSQDB: 235 Changed |= shortenOn01(MI, SystemZ::SQDBR); 236 break; 237 238 case SystemZ::WFSDB: 239 Changed |= shortenOn001AddCC(MI, SystemZ::SDBR); 240 break; 241 242 case SystemZ::WFCDB: 243 Changed |= shortenOn01(MI, SystemZ::CDBR); 244 break; 245 246 case SystemZ::VL32: 247 // For z13 we prefer LDE over LE to avoid partial register dependencies. 248 Changed |= shortenOn0(MI, SystemZ::LDE32); 249 break; 250 251 case SystemZ::VST32: 252 Changed |= shortenOn0(MI, SystemZ::STE); 253 break; 254 255 case SystemZ::VL64: 256 Changed |= shortenOn0(MI, SystemZ::LD); 257 break; 258 259 case SystemZ::VST64: 260 Changed |= shortenOn0(MI, SystemZ::STD); 261 break; 262 } 263 264 LiveRegs.stepBackward(MI); 265 } 266 267 return Changed; 268 } 269 270 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) { 271 const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>(); 272 TII = ST.getInstrInfo(); 273 TRI = ST.getRegisterInfo(); 274 LiveRegs.init(TRI); 275 276 bool Changed = false; 277 for (auto &MBB : F) 278 Changed |= processBlock(MBB); 279 280 return Changed; 281 } 282