1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass tries to replace instructions with shorter forms.  For example,
11 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
12 // other 32 bits of the GR64 destination are not live.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "systemz-shorten-inst"
23 
24 namespace {
25 class SystemZShortenInst : public MachineFunctionPass {
26 public:
27   static char ID;
28   SystemZShortenInst(const SystemZTargetMachine &tm);
29 
30   const char *getPassName() const override {
31     return "SystemZ Instruction Shortening";
32   }
33 
34   bool processBlock(MachineBasicBlock &MBB);
35   bool runOnMachineFunction(MachineFunction &F) override;
36 
37 private:
38   bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,
39                   unsigned LLIxL, unsigned LLIxH);
40   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
41   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
42   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
43   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode, bool CCLive);
44   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
45 
46   const SystemZInstrInfo *TII;
47 
48   // LowGPRs[I] has bit N set if LLVM register I includes the low
49   // word of GPR N.  HighGPRs is the same for the high word.
50   unsigned LowGPRs[SystemZ::NUM_TARGET_REGS];
51   unsigned HighGPRs[SystemZ::NUM_TARGET_REGS];
52 };
53 
54 char SystemZShortenInst::ID = 0;
55 } // end anonymous namespace
56 
57 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
58   return new SystemZShortenInst(TM);
59 }
60 
61 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
62   : MachineFunctionPass(ID), TII(nullptr), LowGPRs(), HighGPRs() {
63   // Set up LowGPRs and HighGPRs.
64   for (unsigned I = 0; I < 16; ++I) {
65     LowGPRs[SystemZMC::GR32Regs[I]] |= 1 << I;
66     LowGPRs[SystemZMC::GR64Regs[I]] |= 1 << I;
67     HighGPRs[SystemZMC::GRH32Regs[I]] |= 1 << I;
68     HighGPRs[SystemZMC::GR64Regs[I]] |= 1 << I;
69     if (unsigned GR128 = SystemZMC::GR128Regs[I]) {
70       LowGPRs[GR128] |= 3 << I;
71       HighGPRs[GR128] |= 3 << I;
72     }
73   }
74 }
75 
76 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
77 // are the halfword immediate loads for the same word.  Try to use one of them
78 // instead of IIxF.  If MI loads the high word, GPRMap[X] is the set of high
79 // words referenced by LLVM register X while LiveOther is the mask of low
80 // words that are currently live, and vice versa.
81 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned *GPRMap,
82                                     unsigned LiveOther, unsigned LLIxL,
83                                     unsigned LLIxH) {
84   unsigned Reg = MI.getOperand(0).getReg();
85   assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
86   unsigned GPRs = GPRMap[Reg];
87   assert(GPRs != 0 && "Register must be a GPR");
88   if (GPRs & LiveOther)
89     return false;
90 
91   uint64_t Imm = MI.getOperand(1).getImm();
92   if (SystemZ::isImmLL(Imm)) {
93     MI.setDesc(TII->get(LLIxL));
94     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
95     return true;
96   }
97   if (SystemZ::isImmLH(Imm)) {
98     MI.setDesc(TII->get(LLIxH));
99     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
100     MI.getOperand(1).setImm(Imm >> 16);
101     return true;
102   }
103   return false;
104 }
105 
106 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
107 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
108   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
109     MI.setDesc(TII->get(Opcode));
110     return true;
111   }
112   return false;
113 }
114 
115 // Change MI's opcode to Opcode if register operands 0 and 1 have a
116 // 4-bit encoding.
117 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
118   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
119       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
120     MI.setDesc(TII->get(Opcode));
121     return true;
122   }
123   return false;
124 }
125 
126 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
127 // 4-bit encoding and if operands 0 and 1 are tied.
128 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
129   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
130       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
131       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
132     MI.setDesc(TII->get(Opcode));
133     return true;
134   }
135   return false;
136 }
137 
138 // Calls shortenOn001 if CCLive is false. CC def operand is added in
139 // case of success.
140 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode,
141 					   bool CCLive) {
142   if (!CCLive && shortenOn001(MI, Opcode)) {
143     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
144       .addReg(SystemZ::CC, RegState::ImplicitDefine);
145     return true;
146   }
147   return false;
148 }
149 
150 // MI is a vector-style conversion instruction with the operand order:
151 // destination, source, exact-suppress, rounding-mode.  If both registers
152 // have a 4-bit encoding then change it to Opcode, which has operand order:
153 // destination, rouding-mode, source, exact-suppress.
154 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
155   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
156       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
157     MachineOperand Dest(MI.getOperand(0));
158     MachineOperand Src(MI.getOperand(1));
159     MachineOperand Suppress(MI.getOperand(2));
160     MachineOperand Mode(MI.getOperand(3));
161     MI.RemoveOperand(3);
162     MI.RemoveOperand(2);
163     MI.RemoveOperand(1);
164     MI.RemoveOperand(0);
165     MI.setDesc(TII->get(Opcode));
166     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
167       .addOperand(Dest)
168       .addOperand(Mode)
169       .addOperand(Src)
170       .addOperand(Suppress);
171     return true;
172   }
173   return false;
174 }
175 
176 // Process all instructions in MBB.  Return true if something changed.
177 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
178   bool Changed = false;
179 
180   // Work out which words are live on exit from the block.
181   unsigned LiveLow = 0;
182   unsigned LiveHigh = 0;
183   bool CCLive = false;
184   for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) {
185     for (const auto &LI : (*SI)->liveins()) {
186       unsigned Reg = LI.PhysReg;
187       assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
188       LiveLow |= LowGPRs[Reg];
189       LiveHigh |= HighGPRs[Reg];
190       if (Reg == SystemZ::CC)
191 	CCLive = true;
192     }
193   }
194 
195   // Iterate backwards through the block looking for instructions to change.
196   for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
197     MachineInstr &MI = *MBBI;
198     switch (MI.getOpcode()) {
199     case SystemZ::IILF:
200       Changed |= shortenIIF(MI, LowGPRs, LiveHigh, SystemZ::LLILL,
201                             SystemZ::LLILH);
202       break;
203 
204     case SystemZ::IIHF:
205       Changed |= shortenIIF(MI, HighGPRs, LiveLow, SystemZ::LLIHL,
206                             SystemZ::LLIHH);
207       break;
208 
209     case SystemZ::WFADB:
210       Changed |= shortenOn001AddCC(MI, SystemZ::ADBR, CCLive);
211       break;
212 
213     case SystemZ::WFDDB:
214       Changed |= shortenOn001(MI, SystemZ::DDBR);
215       break;
216 
217     case SystemZ::WFIDB:
218       Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
219       break;
220 
221     case SystemZ::WLDEB:
222       Changed |= shortenOn01(MI, SystemZ::LDEBR);
223       break;
224 
225     case SystemZ::WLEDB:
226       Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
227       break;
228 
229     case SystemZ::WFMDB:
230       Changed |= shortenOn001(MI, SystemZ::MDBR);
231       break;
232 
233     case SystemZ::WFLCDB:
234       Changed |= shortenOn01(MI, SystemZ::LCDFR);
235       break;
236 
237     case SystemZ::WFLNDB:
238       Changed |= shortenOn01(MI, SystemZ::LNDFR);
239       break;
240 
241     case SystemZ::WFLPDB:
242       Changed |= shortenOn01(MI, SystemZ::LPDFR);
243       break;
244 
245     case SystemZ::WFSQDB:
246       Changed |= shortenOn01(MI, SystemZ::SQDBR);
247       break;
248 
249     case SystemZ::WFSDB:
250       Changed |= shortenOn001AddCC(MI, SystemZ::SDBR, CCLive);
251       break;
252 
253     case SystemZ::WFCDB:
254       Changed |= shortenOn01(MI, SystemZ::CDBR);
255       break;
256 
257     case SystemZ::VL32:
258       // For z13 we prefer LDE over LE to avoid partial register dependencies.
259       Changed |= shortenOn0(MI, SystemZ::LDE32);
260       break;
261 
262     case SystemZ::VST32:
263       Changed |= shortenOn0(MI, SystemZ::STE);
264       break;
265 
266     case SystemZ::VL64:
267       Changed |= shortenOn0(MI, SystemZ::LD);
268       break;
269 
270     case SystemZ::VST64:
271       Changed |= shortenOn0(MI, SystemZ::STD);
272       break;
273     }
274 
275     unsigned UsedLow = 0;
276     unsigned UsedHigh = 0;
277     for (auto MOI = MI.operands_begin(), MOE = MI.operands_end();
278          MOI != MOE; ++MOI) {
279       MachineOperand &MO = *MOI;
280       if (MO.isReg()) {
281         if (unsigned Reg = MO.getReg()) {
282           assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
283           if (MO.isDef()) {
284             LiveLow &= ~LowGPRs[Reg];
285             LiveHigh &= ~HighGPRs[Reg];
286           } else if (!MO.isUndef()) {
287             UsedLow |= LowGPRs[Reg];
288             UsedHigh |= HighGPRs[Reg];
289           }
290         }
291       }
292     }
293     LiveLow |= UsedLow;
294     LiveHigh |= UsedHigh;
295 
296     if (MI.definesRegister(SystemZ::CC))
297       CCLive = false;
298     if (MI.readsRegister(SystemZ::CC))
299       CCLive = true;
300   }
301 
302   return Changed;
303 }
304 
305 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
306   TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
307 
308   bool Changed = false;
309   for (auto &MBB : F)
310     Changed |= processBlock(MBB);
311 
312   return Changed;
313 }
314