1//=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for ZEC12 to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15def ZEC12Model : SchedMachineModel {
16
17    let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
18
19    let IssueWidth = 5;
20    let MicroOpBufferSize = 40;     // Issue queues
21    let LoadLatency = 1;            // Optimistic load latency.
22
23    let PostRAScheduler = 1;
24
25    // Extra cycles for a mispredicted branch.
26    let MispredictPenalty = 16;
27}
28
29let SchedModel = ZEC12Model in  {
30
31// These definitions could be put in a subtarget common include file,
32// but it seems the include system in Tablegen currently rejects
33// multiple includes of same file.
34def : WriteRes<GroupAlone, []> {
35  let NumMicroOps = 0;
36  let BeginGroup  = 1;
37  let EndGroup    = 1;
38}
39def : WriteRes<EndGroup, []> {
40  let NumMicroOps = 0;
41  let EndGroup    = 1;
42}
43def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
44def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
45def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
46def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
47def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
48def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
49def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
50def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
51def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
52def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
53def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
54def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
55def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
56def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
57
58// Execution units.
59def ZEC12_FXUnit : ProcResource<2>;
60def ZEC12_LSUnit : ProcResource<2>;
61def ZEC12_FPUnit : ProcResource<1>;
62def ZEC12_VBUnit : ProcResource<1>;
63
64// Subtarget specific definitions of scheduling resources.
65def : WriteRes<FXU,      [ZEC12_FXUnit]> { let Latency = 1; }
66def : WriteRes<LSU,      [ZEC12_LSUnit]> { let Latency = 4; }
67def : WriteRes<LSU_lat1, [ZEC12_LSUnit]> { let Latency = 1; }
68def : WriteRes<FPU,  [ZEC12_FPUnit]> { let Latency = 8; }
69def : WriteRes<FPU2, [ZEC12_FPUnit, ZEC12_FPUnit]> { let Latency = 9; }
70def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
71
72// -------------------------- INSTRUCTIONS ---------------------------------- //
73
74// InstRW constructs have been used in order to preserve the
75// readability of the InstrInfo files.
76
77// For each instruction, as matched by a regexp, provide a list of
78// resources that it needs. These will be combined into a SchedClass.
79
80//===----------------------------------------------------------------------===//
81// Stack allocation
82//===----------------------------------------------------------------------===//
83
84def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
85
86//===----------------------------------------------------------------------===//
87// Branch instructions
88//===----------------------------------------------------------------------===//
89
90// Branch
91def : InstRW<[VBU], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
92def : InstRW<[VBU], (instregex "(Call)?J(G)?(Asm.*)?$")>;
93def : InstRW<[LSU, Lat4], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
94def : InstRW<[LSU, Lat4], (instregex "(Call)?B(R)?(Asm.*)?$")>;
95def : InstRW<[FXU, EndGroup], (instregex "BRCT(G)?$")>;
96def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCTH$")>;
97def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BCT(G)?(R)?$")>;
98def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone],
99             (instregex "B(R)?X(H|L).*$")>;
100
101// Compare and branch
102def : InstRW<[FXU], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
103def : InstRW<[FXU, LSU, Lat5, GroupAlone],
104             (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
105
106//===----------------------------------------------------------------------===//
107// Trap instructions
108//===----------------------------------------------------------------------===//
109
110// Trap
111def : InstRW<[VBU], (instregex "(Cond)?Trap$")>;
112
113// Compare and trap
114def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
115def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
116def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
117def : InstRW<[FXU, LSU, Lat5], (instregex "CL(G)?T(Asm.*)?$")>;
118
119//===----------------------------------------------------------------------===//
120// Call and return instructions
121//===----------------------------------------------------------------------===//
122
123// Call
124def : InstRW<[VBU, FXU, FXU, Lat3, GroupAlone], (instregex "(Call)?BRAS$")>;
125def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
126def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
127def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
128
129// Return
130def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
131def : InstRW<[LSU_lat1], (instregex "CondReturn$")>;
132
133//===----------------------------------------------------------------------===//
134// Select instructions
135//===----------------------------------------------------------------------===//
136
137// Select pseudo
138def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
139
140// CondStore pseudos
141def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
142def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
143def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
144def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
145def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
146def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
147
148//===----------------------------------------------------------------------===//
149// Move instructions
150//===----------------------------------------------------------------------===//
151
152// Moves
153def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
154def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
155
156// Move character
157def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
158
159// Pseudo -> reg move
160def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
161def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
162def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
163def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
164def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
165
166// Loads
167def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
168def : InstRW<[LSU], (instregex "LG(RL)?$")>;
169def : InstRW<[LSU], (instregex "L128$")>;
170
171def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
172def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
173
174def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
175def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
176def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
177
178// Load and trap
179def : InstRW<[FXU, LSU, Lat5], (instregex "L(FH|G)?AT$")>;
180
181// Load and test
182def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
183def : InstRW<[FXU], (instregex "LT(G)?R$")>;
184
185// Stores
186def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
187def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
188def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
189
190// String moves.
191def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
192
193//===----------------------------------------------------------------------===//
194// Conditional move instructions
195//===----------------------------------------------------------------------===//
196
197def : InstRW<[FXU, Lat2], (instregex "LOC(G)?R(Asm.*)?$")>;
198def : InstRW<[FXU, LSU, Lat6], (instregex "LOC(G)?(Asm.*)?$")>;
199def : InstRW<[FXU, LSU, Lat5], (instregex "STOC(G)?(Asm.*)?$")>;
200
201//===----------------------------------------------------------------------===//
202// Sign extensions
203//===----------------------------------------------------------------------===//
204
205def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
206def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
207
208def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
209def : InstRW<[FXU], (instregex "LTGFR$")>;
210
211def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
212def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
213def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
214def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
215def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
216
217//===----------------------------------------------------------------------===//
218// Zero extensions
219//===----------------------------------------------------------------------===//
220
221def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
222def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
223def : InstRW<[FXU], (instregex "LLG(C|H|F|T)R$")>;
224def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
225def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
226def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
227def : InstRW<[LSU], (instregex "LLHRL$")>;
228def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
229
230// Load and trap
231def : InstRW<[FXU, LSU, Lat5], (instregex "LLG(F|T)?AT$")>;
232
233//===----------------------------------------------------------------------===//
234// Truncations
235//===----------------------------------------------------------------------===//
236
237def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
238def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
239
240//===----------------------------------------------------------------------===//
241// Multi-register moves
242//===----------------------------------------------------------------------===//
243
244// Load multiple (estimated average of 5 ops)
245def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
246             (instregex "LM(H|Y|G)?$")>;
247
248// Store multiple (estimated average of 3 ops)
249def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
250             (instregex "STM(H|Y|G)?$")>;
251
252//===----------------------------------------------------------------------===//
253// Byte swaps
254//===----------------------------------------------------------------------===//
255
256def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
257def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
258def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
259
260//===----------------------------------------------------------------------===//
261// Load address instructions
262//===----------------------------------------------------------------------===//
263
264def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
265
266// Load the Global Offset Table address
267def : InstRW<[FXU], (instregex "GOT$")>;
268
269//===----------------------------------------------------------------------===//
270// Absolute and Negation
271//===----------------------------------------------------------------------===//
272
273def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
274def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
275def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
276def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
277def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
278
279//===----------------------------------------------------------------------===//
280// Insertion
281//===----------------------------------------------------------------------===//
282
283def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
284def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
285def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
286def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
287def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
288def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
289def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
290def : InstRW<[FXU], (instregex "IILF(64)?$")>;
291def : InstRW<[FXU], (instregex "IILH(64)?$")>;
292def : InstRW<[FXU], (instregex "IILL(64)?$")>;
293
294//===----------------------------------------------------------------------===//
295// Addition
296//===----------------------------------------------------------------------===//
297
298def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
299def : InstRW<[FXU, LSU, Lat6], (instregex "AH(Y)?$")>;
300def : InstRW<[FXU], (instregex "AIH$")>;
301def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
302def : InstRW<[FXU], (instregex "AGFI$")>;
303def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
304def : InstRW<[FXU], (instregex "AGR(K)?$")>;
305def : InstRW<[FXU], (instregex "AHI(K)?$")>;
306def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
307def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
308def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
309def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
310def : InstRW<[FXU], (instregex "ALGHSIK$")>;
311def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
312def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
313def : InstRW<[FXU], (instregex "ALR(K)?$")>;
314def : InstRW<[FXU], (instregex "AR(K)?$")>;
315def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
316
317// Logical addition with carry
318def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
319def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
320
321// Add with sign extension (32 -> 64)
322def : InstRW<[FXU, LSU, Lat6], (instregex "AGF$")>;
323def : InstRW<[FXU, Lat2], (instregex "AGFR$")>;
324
325//===----------------------------------------------------------------------===//
326// Subtraction
327//===----------------------------------------------------------------------===//
328
329def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
330def : InstRW<[FXU, LSU, Lat6], (instregex "SH(Y)?$")>;
331def : InstRW<[FXU], (instregex "SGR(K)?$")>;
332def : InstRW<[FXU], (instregex "SLFI$")>;
333def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
334def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
335def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
336def : InstRW<[FXU], (instregex "SLR(K)?$")>;
337def : InstRW<[FXU], (instregex "SR(K)?$")>;
338
339// Subtraction with borrow
340def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
341def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
342
343// Subtraction with sign extension (32 -> 64)
344def : InstRW<[FXU, LSU, Lat6], (instregex "SGF$")>;
345def : InstRW<[FXU, Lat2], (instregex "SGFR$")>;
346
347//===----------------------------------------------------------------------===//
348// AND
349//===----------------------------------------------------------------------===//
350
351def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
352def : InstRW<[FXU], (instregex "NGR(K)?$")>;
353def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
354def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
355def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
356def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
357def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
358def : InstRW<[FXU], (instregex "NILF(64)?$")>;
359def : InstRW<[FXU], (instregex "NILH(64)?$")>;
360def : InstRW<[FXU], (instregex "NILL(64)?$")>;
361def : InstRW<[FXU], (instregex "NR(K)?$")>;
362def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
363
364//===----------------------------------------------------------------------===//
365// OR
366//===----------------------------------------------------------------------===//
367
368def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
369def : InstRW<[FXU], (instregex "OGR(K)?$")>;
370def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
371def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
372def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
373def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
374def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
375def : InstRW<[FXU], (instregex "OILF(64)?$")>;
376def : InstRW<[FXU], (instregex "OILH(64)?$")>;
377def : InstRW<[FXU], (instregex "OILL(64)?$")>;
378def : InstRW<[FXU], (instregex "OR(K)?$")>;
379def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
380
381//===----------------------------------------------------------------------===//
382// XOR
383//===----------------------------------------------------------------------===//
384
385def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
386def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
387def : InstRW<[FXU], (instregex "XIFMux$")>;
388def : InstRW<[FXU], (instregex "XGR(K)?$")>;
389def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
390def : InstRW<[FXU], (instregex "XILF(64)?$")>;
391def : InstRW<[FXU], (instregex "XR(K)?$")>;
392def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
393
394//===----------------------------------------------------------------------===//
395// Multiplication
396//===----------------------------------------------------------------------===//
397
398def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
399def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
400def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
401def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
402def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
403def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
404def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
405def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
406def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
407def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
408
409//===----------------------------------------------------------------------===//
410// Division and remainder
411//===----------------------------------------------------------------------===//
412
413def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
414              (instregex "DSG(F)?R$")>;
415def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
416              (instregex "DSG(F)?$")>;
417def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
418              (instregex "DL(G)?R$")>;
419def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
420              (instregex "DL(G)?$")>;
421
422//===----------------------------------------------------------------------===//
423// Shifts
424//===----------------------------------------------------------------------===//
425
426def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
427def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
428def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
429def : InstRW<[FXU], (instregex "SLA(K)?$")>;
430
431// Rotate
432def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
433
434// Rotate and insert
435def : InstRW<[FXU], (instregex "RISBG(N|32)?$")>;
436def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
437def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
438def : InstRW<[FXU], (instregex "RISBMux$")>;
439
440// Rotate and Select
441def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
442
443//===----------------------------------------------------------------------===//
444// Comparison
445//===----------------------------------------------------------------------===//
446
447def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
448def : InstRW<[FXU], (instregex "C(F|H)I(Mux)?$")>;
449def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
450def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
451def : InstRW<[FXU], (instregex "C(G)?R$")>;
452def : InstRW<[FXU], (instregex "CIH$")>;
453def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
454def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
455def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
456def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
457def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
458def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
459def : InstRW<[FXU], (instregex "CLGR$")>;
460def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
461def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
462def : InstRW<[FXU], (instregex "CLIH$")>;
463def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
464def : InstRW<[FXU], (instregex "CLR$")>;
465def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
466
467// Compare halfword
468def : InstRW<[FXU, LSU, Lat6], (instregex "CH(Y|RL)?$")>;
469def : InstRW<[FXU, LSU, Lat6], (instregex "CGH(RL)?$")>;
470def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CHHSI$")>;
471
472// Compare with sign extension (32 -> 64)
473def : InstRW<[FXU, LSU, Lat6], (instregex "CGF(RL)?$")>;
474def : InstRW<[FXU, Lat2], (instregex "CGFR$")>;
475
476// Compare logical character
477def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "CLC$")>;
478
479def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
480
481// Test under mask
482def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
483def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
484def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
485def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
486def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
487def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
488
489//===----------------------------------------------------------------------===//
490// Prefetch and execution hint
491//===----------------------------------------------------------------------===//
492
493def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
494def : InstRW<[LSU], (instregex "BP(R)?P$")>;
495def : InstRW<[FXU], (instregex "NIAI$")>;
496
497//===----------------------------------------------------------------------===//
498// Atomic operations
499//===----------------------------------------------------------------------===//
500
501def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
502
503def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
504def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
505def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
506def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
507def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
508
509// Test and set
510def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
511
512// Compare and swap
513def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
514
515// Compare double and swap
516def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
517             (instregex "CDS(Y)?$")>;
518def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
519             (instregex "CDSG$")>;
520
521// Compare and swap and store
522def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
523
524// Perform locked operation
525def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
526
527// Load/store pair from/to quadword
528def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
529def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
530
531// Load pair disjoint
532def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
533
534//===----------------------------------------------------------------------===//
535// Access registers
536//===----------------------------------------------------------------------===//
537
538// Extract/set/copy access register
539def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
540
541// Load address extended
542def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
543
544// Load/store access multiple (not modeled precisely)
545def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
546
547//===----------------------------------------------------------------------===//
548// Program mask and addressing mode
549//===----------------------------------------------------------------------===//
550
551// Insert Program Mask
552def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
553
554// Set Program Mask
555def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
556
557// Branch and link
558def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
559
560// Test addressing mode
561def : InstRW<[FXU], (instregex "TAM$")>;
562
563// Set addressing mode
564def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
565
566// Branch (and save) and set mode.
567def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
568def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
569
570//===----------------------------------------------------------------------===//
571// Transactional execution
572//===----------------------------------------------------------------------===//
573
574// Transaction begin
575def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone],
576              (instregex "TBEGIN(C|_nofloat)?$")>;
577
578// Transaction end
579def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>;
580
581// Transaction abort
582def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>;
583
584// Extract Transaction Nesting Depth
585def : InstRW<[FXU], (instregex "ETND$")>;
586
587// Nontransactional store
588def : InstRW<[FXU, LSU, Lat5], (instregex "NTSTG$")>;
589
590//===----------------------------------------------------------------------===//
591// Processor assist
592//===----------------------------------------------------------------------===//
593
594def : InstRW<[FXU], (instregex "PPA$")>;
595
596//===----------------------------------------------------------------------===//
597// Miscellaneous Instructions.
598//===----------------------------------------------------------------------===//
599
600// Find leftmost one
601def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
602
603// Population count
604def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
605
606// Extend
607def : InstRW<[FXU], (instregex "AEXT128_64$")>;
608def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
609
610// String instructions
611def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
612
613// Move with key
614def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
615
616// Extract CPU Time
617def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
618
619// Execute
620def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
621
622// Program return
623def : InstRW<[FXU, Lat30], (instregex "PR$")>;
624
625// Inline assembly
626def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>;
627def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone],
628             (instregex "STCKE$")>;
629def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
630def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
631
632// Store real address
633def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
634
635//===----------------------------------------------------------------------===//
636// .insn directive instructions
637//===----------------------------------------------------------------------===//
638
639// An "empty" sched-class will be assigned instead of the "invalid sched-class".
640// getNumDecoderSlots() will then return 1 instead of 0.
641def : InstRW<[], (instregex "Insn.*")>;
642
643
644// ----------------------------- Floating point ----------------------------- //
645
646//===----------------------------------------------------------------------===//
647// FP: Select instructions
648//===----------------------------------------------------------------------===//
649
650def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
651def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
652def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
653
654//===----------------------------------------------------------------------===//
655// FP: Move instructions
656//===----------------------------------------------------------------------===//
657
658// Load zero
659def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
660def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
661
662// Load
663def : InstRW<[FXU], (instregex "LER$")>;
664def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
665def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
666def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
667
668// Load and Test
669def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
670def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
671def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
672def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
673def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
674             (instregex "LTXBRCompare(_VecPseudo)?$")>;
675
676// Copy sign
677def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
678def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
679
680//===----------------------------------------------------------------------===//
681// FP: Load instructions
682//===----------------------------------------------------------------------===//
683
684def : InstRW<[LSU], (instregex "LE(Y)?$")>;
685def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
686def : InstRW<[LSU], (instregex "LX$")>;
687
688//===----------------------------------------------------------------------===//
689// FP: Store instructions
690//===----------------------------------------------------------------------===//
691
692def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
693def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
694def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
695
696//===----------------------------------------------------------------------===//
697// FP: Conversion instructions
698//===----------------------------------------------------------------------===//
699
700// Load rounded
701def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
702def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
703def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
704
705// Load lengthened
706def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
707def : InstRW<[FPU], (instregex "LDEBR$")>;
708def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
709def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
710
711// Convert from fixed / logical
712def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A?)$")>;
713def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A?)$")>;
714def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A?)$")>;
715def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
716def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
717def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
718
719// Convert to fixed / logical
720def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A?)$")>;
721def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A?)$")>;
722def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A?)$")>;
723def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
724def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
725def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
726
727//===----------------------------------------------------------------------===//
728// FP: Unary arithmetic
729//===----------------------------------------------------------------------===//
730
731// Load Complement / Negative / Positive
732def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
733def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
734def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
735def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
736def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
737def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
738
739// Square root
740def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
741def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
742def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
743
744// Load FP integer
745def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
746def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
747def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
748
749//===----------------------------------------------------------------------===//
750// FP: Binary arithmetic
751//===----------------------------------------------------------------------===//
752
753// Addition
754def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
755def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
756def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
757
758// Subtraction
759def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
760def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
761def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
762
763// Multiply
764def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
765def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
766def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
767def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
768def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
769
770// Multiply and add / subtract
771def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
772def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
773def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
774def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
775
776// Division
777def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
778def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
779def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
780
781//===----------------------------------------------------------------------===//
782// FP: Comparisons
783//===----------------------------------------------------------------------===//
784
785// Compare
786def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
787def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
788def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
789
790// Test Data Class
791def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
792def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
793
794//===----------------------------------------------------------------------===//
795// FP: Floating-point control register instructions
796//===----------------------------------------------------------------------===//
797
798def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
799def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
800def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
801def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
802def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
803def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
804def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;
805
806}
807
808