1//=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Z196 to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15def Z196Model : SchedMachineModel {
16
17    let UnsupportedFeatures = Arch9UnsupportedFeatures.List;
18
19    let IssueWidth = 5;
20    let MicroOpBufferSize = 40;     // Issue queues
21    let LoadLatency = 1;            // Optimistic load latency.
22
23    let PostRAScheduler = 1;
24
25    // Extra cycles for a mispredicted branch.
26    let MispredictPenalty = 16;
27}
28
29let SchedModel = Z196Model in  {
30
31// These definitions could be put in a subtarget common include file,
32// but it seems the include system in Tablegen currently rejects
33// multiple includes of same file.
34def : WriteRes<GroupAlone, []> {
35  let NumMicroOps = 0;
36  let BeginGroup  = 1;
37  let EndGroup    = 1;
38}
39def : WriteRes<EndGroup, []> {
40  let NumMicroOps = 0;
41  let EndGroup    = 1;
42}
43def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
44def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
45def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
46def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
47def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
48def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
49def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
50def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
51def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
52def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
53def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
54def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
55def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
56def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
57
58// Execution units.
59def Z196_FXUnit : ProcResource<2>;
60def Z196_LSUnit : ProcResource<2>;
61def Z196_FPUnit : ProcResource<1>;
62
63// Subtarget specific definitions of scheduling resources.
64def : WriteRes<FXU,       [Z196_FXUnit]> { let Latency = 1; }
65def : WriteRes<LSU,       [Z196_LSUnit]> { let Latency = 4; }
66def : WriteRes<LSU_lat1,  [Z196_LSUnit]> { let Latency = 1; }
67def : WriteRes<FPU,       [Z196_FPUnit]> { let Latency = 8; }
68def : WriteRes<FPU2,      [Z196_FPUnit, Z196_FPUnit]> { let Latency = 9; }
69
70// -------------------------- INSTRUCTIONS ---------------------------------- //
71
72// InstRW constructs have been used in order to preserve the
73// readability of the InstrInfo files.
74
75// For each instruction, as matched by a regexp, provide a list of
76// resources that it needs. These will be combined into a SchedClass.
77
78//===----------------------------------------------------------------------===//
79// Stack allocation
80//===----------------------------------------------------------------------===//
81
82def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
83
84//===----------------------------------------------------------------------===//
85// Branch instructions
86//===----------------------------------------------------------------------===//
87
88// Branch
89def : InstRW<[LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
90def : InstRW<[LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
91def : InstRW<[LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
92def : InstRW<[LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
93def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCT(G|H)?$")>;
94def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BCT(G)?(R)?$")>;
95def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone],
96             (instregex "B(R)?X(H|L).*$")>;
97
98// Compare and branch
99def : InstRW<[FXU, LSU, Lat5, GroupAlone],
100             (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
101def : InstRW<[FXU, LSU, Lat5, GroupAlone],
102             (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
103
104//===----------------------------------------------------------------------===//
105// Trap instructions
106//===----------------------------------------------------------------------===//
107
108// Trap
109def : InstRW<[LSU, EndGroup], (instregex "(Cond)?Trap$")>;
110
111// Compare and trap
112def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
113def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
114def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
115
116//===----------------------------------------------------------------------===//
117// Call and return instructions
118//===----------------------------------------------------------------------===//
119
120// Call
121def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRAS$")>;
122def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
123def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
124def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
125
126// Return
127def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
128def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
129
130//===----------------------------------------------------------------------===//
131// Select instructions
132//===----------------------------------------------------------------------===//
133
134// Select pseudo
135def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
136
137// CondStore pseudos
138def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
139def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
140def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
141def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
142def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
143def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
144
145//===----------------------------------------------------------------------===//
146// Move instructions
147//===----------------------------------------------------------------------===//
148
149// Moves
150def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
151def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
152
153// Move character
154def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
155
156// Pseudo -> reg move
157def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
158def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
159def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
160def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
161def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
162
163// Loads
164def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
165def : InstRW<[LSU], (instregex "LG(RL)?$")>;
166def : InstRW<[LSU], (instregex "L128$")>;
167
168def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
169def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
170
171def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
172def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
173def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
174
175// Load and test
176def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
177def : InstRW<[FXU], (instregex "LT(G)?R$")>;
178
179// Stores
180def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
181def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
182def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
183
184// String moves.
185def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
186
187//===----------------------------------------------------------------------===//
188// Conditional move instructions
189//===----------------------------------------------------------------------===//
190
191def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?R(Asm.*)?$")>;
192def : InstRW<[FXU, LSU, Lat6, EndGroup], (instregex "LOC(G)?(Asm.*)?$")>;
193def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "STOC(G)?(Asm.*)?$")>;
194
195//===----------------------------------------------------------------------===//
196// Sign extensions
197//===----------------------------------------------------------------------===//
198def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
199def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
200
201def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
202def : InstRW<[FXU], (instregex "LTGFR$")>;
203
204def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
205def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
206def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
207def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
208def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
209
210//===----------------------------------------------------------------------===//
211// Zero extensions
212//===----------------------------------------------------------------------===//
213
214def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
215def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
216def : InstRW<[FXU], (instregex "LLG(C|F|H|T)R$")>;
217def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
218def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
219def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
220def : InstRW<[LSU], (instregex "LLHRL$")>;
221def : InstRW<[LSU], (instregex "LLG(C|F|H|T|FRL|HRL)$")>;
222
223//===----------------------------------------------------------------------===//
224// Truncations
225//===----------------------------------------------------------------------===//
226
227def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
228def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
229
230//===----------------------------------------------------------------------===//
231// Multi-register moves
232//===----------------------------------------------------------------------===//
233
234// Load multiple (estimated average of 5 ops)
235def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
236             (instregex "LM(H|Y|G)?$")>;
237
238// Store multiple (estimated average of 3 ops)
239def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
240             (instregex "STM(H|Y|G)?$")>;
241
242//===----------------------------------------------------------------------===//
243// Byte swaps
244//===----------------------------------------------------------------------===//
245
246def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
247def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
248def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
249
250//===----------------------------------------------------------------------===//
251// Load address instructions
252//===----------------------------------------------------------------------===//
253
254def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
255
256// Load the Global Offset Table address
257def : InstRW<[FXU], (instregex "GOT$")>;
258
259//===----------------------------------------------------------------------===//
260// Absolute and Negation
261//===----------------------------------------------------------------------===//
262
263def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
264def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
265def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
266def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
267def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
268
269//===----------------------------------------------------------------------===//
270// Insertion
271//===----------------------------------------------------------------------===//
272
273def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
274def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
275def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
276def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
277def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
278def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
279def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
280def : InstRW<[FXU], (instregex "IILF(64)?$")>;
281def : InstRW<[FXU], (instregex "IILH(64)?$")>;
282def : InstRW<[FXU], (instregex "IILL(64)?$")>;
283
284//===----------------------------------------------------------------------===//
285// Addition
286//===----------------------------------------------------------------------===//
287
288def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
289def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AH(Y)?$")>;
290def : InstRW<[FXU], (instregex "AIH$")>;
291def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
292def : InstRW<[FXU], (instregex "AGFI$")>;
293def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
294def : InstRW<[FXU], (instregex "AGR(K)?$")>;
295def : InstRW<[FXU], (instregex "AHI(K)?$")>;
296def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
297def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
298def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
299def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
300def : InstRW<[FXU], (instregex "ALGHSIK$")>;
301def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
302def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
303def : InstRW<[FXU], (instregex "ALR(K)?$")>;
304def : InstRW<[FXU], (instregex "AR(K)?$")>;
305def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
306
307// Logical addition with carry
308def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
309def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
310
311// Add with sign extension (32 -> 64)
312def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AGF$")>;
313def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "AGFR$")>;
314
315//===----------------------------------------------------------------------===//
316// Subtraction
317//===----------------------------------------------------------------------===//
318
319def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
320def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SH(Y)?$")>;
321def : InstRW<[FXU], (instregex "SGR(K)?$")>;
322def : InstRW<[FXU], (instregex "SLFI$")>;
323def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
324def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
325def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
326def : InstRW<[FXU], (instregex "SLR(K)?$")>;
327def : InstRW<[FXU], (instregex "SR(K)?$")>;
328
329// Subtraction with borrow
330def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
331def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
332
333// Subtraction with sign extension (32 -> 64)
334def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SGF$")>;
335def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "SGFR$")>;
336
337//===----------------------------------------------------------------------===//
338// AND
339//===----------------------------------------------------------------------===//
340
341def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
342def : InstRW<[FXU], (instregex "NGR(K)?$")>;
343def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
344def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
345def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
346def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
347def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
348def : InstRW<[FXU], (instregex "NILF(64)?$")>;
349def : InstRW<[FXU], (instregex "NILH(64)?$")>;
350def : InstRW<[FXU], (instregex "NILL(64)?$")>;
351def : InstRW<[FXU], (instregex "NR(K)?$")>;
352def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
353
354//===----------------------------------------------------------------------===//
355// OR
356//===----------------------------------------------------------------------===//
357
358def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
359def : InstRW<[FXU], (instregex "OGR(K)?$")>;
360def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
361def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
362def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
363def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
364def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
365def : InstRW<[FXU], (instregex "OILF(64)?$")>;
366def : InstRW<[FXU], (instregex "OILH(64)?$")>;
367def : InstRW<[FXU], (instregex "OILL(64)?$")>;
368def : InstRW<[FXU], (instregex "OR(K)?$")>;
369def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
370
371//===----------------------------------------------------------------------===//
372// XOR
373//===----------------------------------------------------------------------===//
374
375def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
376def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
377def : InstRW<[FXU], (instregex "XIFMux$")>;
378def : InstRW<[FXU], (instregex "XGR(K)?$")>;
379def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
380def : InstRW<[FXU], (instregex "XILF(64)?$")>;
381def : InstRW<[FXU], (instregex "XR(K)?$")>;
382def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
383
384//===----------------------------------------------------------------------===//
385// Multiplication
386//===----------------------------------------------------------------------===//
387
388def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
389def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
390def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
391def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
392def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
393def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
394def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
395def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
396def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
397def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
398
399//===----------------------------------------------------------------------===//
400// Division and remainder
401//===----------------------------------------------------------------------===//
402
403def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
404              (instregex "DSG(F)?R$")>;
405def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
406              (instregex "DSG(F)?$")>;
407def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
408              (instregex "DL(G)?R$")>;
409def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
410              (instregex "DL(G)?$")>;
411
412//===----------------------------------------------------------------------===//
413// Shifts
414//===----------------------------------------------------------------------===//
415
416def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
417def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
418def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
419def : InstRW<[FXU, Lat2], (instregex "SLA(K)?$")>;
420
421// Rotate
422def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
423
424// Rotate and insert
425def : InstRW<[FXU], (instregex "RISBG(32)?$")>;
426def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
427def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
428def : InstRW<[FXU], (instregex "RISBMux$")>;
429
430// Rotate and Select
431def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
432
433//===----------------------------------------------------------------------===//
434// Comparison
435//===----------------------------------------------------------------------===//
436
437def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
438def : InstRW<[FXU], (instregex "C(F|H)I(Mux)?$")>;
439def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
440def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
441def : InstRW<[FXU], (instregex "C(G)?R$")>;
442def : InstRW<[FXU], (instregex "CIH$")>;
443def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
444def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
445def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
446def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
447def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
448def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
449def : InstRW<[FXU], (instregex "CLGR$")>;
450def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
451def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
452def : InstRW<[FXU], (instregex "CLIH$")>;
453def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
454def : InstRW<[FXU], (instregex "CLR$")>;
455def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
456
457// Compare halfword
458def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CH(Y|RL)?$")>;
459def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CGH(RL)?$")>;
460def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CHHSI$")>;
461
462// Compare with sign extension (32 -> 64)
463def : InstRW<[FXU, FXU, LSU, Lat6, Lat2, GroupAlone], (instregex "CGF(RL)?$")>;
464def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "CGFR$")>;
465
466// Compare logical character
467def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
468
469def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
470
471// Test under mask
472def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
473def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
474def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
475def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
476def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
477def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
478
479//===----------------------------------------------------------------------===//
480// Prefetch
481//===----------------------------------------------------------------------===//
482
483def : InstRW<[LSU, GroupAlone], (instregex "PFD(RL)?$")>;
484
485//===----------------------------------------------------------------------===//
486// Atomic operations
487//===----------------------------------------------------------------------===//
488
489def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
490
491def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
492def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
493def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
494def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
495def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
496
497// Test and set
498def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
499
500// Compare and swap
501def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
502
503// Compare double and swap
504def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
505             (instregex "CDS(Y)?$")>;
506def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
507             (instregex "CDSG$")>;
508
509// Compare and swap and store
510def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
511
512// Perform locked operation
513def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
514
515// Load/store pair from/to quadword
516def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
517def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
518
519// Load pair disjoint
520def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
521
522//===----------------------------------------------------------------------===//
523// Access registers
524//===----------------------------------------------------------------------===//
525
526// Extract/set/copy access register
527def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
528
529// Load address extended
530def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
531
532// Load/store access multiple (not modeled precisely)
533def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
534
535//===----------------------------------------------------------------------===//
536// Program mask and addressing mode
537//===----------------------------------------------------------------------===//
538
539// Insert Program Mask
540def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
541
542// Set Program Mask
543def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
544
545// Branch and link
546def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
547
548// Test addressing mode
549def : InstRW<[FXU], (instregex "TAM$")>;
550
551// Set addressing mode
552def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
553
554// Branch (and save) and set mode.
555def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
556def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
557
558//===----------------------------------------------------------------------===//
559// Miscellaneous Instructions.
560//===----------------------------------------------------------------------===//
561
562// Find leftmost one
563def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
564
565// Population count
566def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
567
568// Extend
569def : InstRW<[FXU], (instregex "AEXT128_64$")>;
570def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
571
572// String instructions
573def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
574
575// Move with key
576def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
577
578// Extract CPU Time
579def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
580
581// Execute
582def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
583
584// Program return
585def : InstRW<[FXU, Lat30], (instregex "PR$")>;
586
587// Inline assembly
588def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>;
589def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>;
590def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>;
591def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
592def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
593
594// Store real address
595def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
596
597//===----------------------------------------------------------------------===//
598// .insn directive instructions
599//===----------------------------------------------------------------------===//
600
601// An "empty" sched-class will be assigned instead of the "invalid sched-class".
602// getNumDecoderSlots() will then return 1 instead of 0.
603def : InstRW<[], (instregex "Insn.*")>;
604
605
606// ----------------------------- Floating point ----------------------------- //
607
608//===----------------------------------------------------------------------===//
609// FP: Select instructions
610//===----------------------------------------------------------------------===//
611
612def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
613def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
614def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
615
616//===----------------------------------------------------------------------===//
617// FP: Move instructions
618//===----------------------------------------------------------------------===//
619
620// Load zero
621def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
622def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
623
624// Load
625def : InstRW<[FXU], (instregex "LER$")>;
626def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
627def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
628def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
629
630// Load and Test
631def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
632def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
633def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
634def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
635def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
636             (instregex "LTXBRCompare(_VecPseudo)?$")>;
637
638// Copy sign
639def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
640def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
641
642//===----------------------------------------------------------------------===//
643// FP: Load instructions
644//===----------------------------------------------------------------------===//
645
646def : InstRW<[LSU], (instregex "LE(Y)?$")>;
647def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
648def : InstRW<[LSU], (instregex "LX$")>;
649
650//===----------------------------------------------------------------------===//
651// FP: Store instructions
652//===----------------------------------------------------------------------===//
653
654def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
655def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
656def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
657
658//===----------------------------------------------------------------------===//
659// FP: Conversion instructions
660//===----------------------------------------------------------------------===//
661
662// Load rounded
663def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
664def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
665def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
666
667// Load lengthened
668def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
669def : InstRW<[FPU], (instregex "LDEBR$")>;
670def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
671def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
672
673// Convert from fixed / logical
674def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A)?$")>;
675def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A)?$")>;
676def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
677def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
678def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
679def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
680
681// Convert to fixed / logical
682def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A)?$")>;
683def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A)?$")>;
684def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A)?$")>;
685def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
686def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
687def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
688
689//===----------------------------------------------------------------------===//
690// FP: Unary arithmetic
691//===----------------------------------------------------------------------===//
692
693// Load Complement / Negative / Positive
694def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
695def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
696def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
697def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
698def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
699def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
700
701// Square root
702def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
703def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
704def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
705
706// Load FP integer
707def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
708def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
709def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
710
711//===----------------------------------------------------------------------===//
712// FP: Binary arithmetic
713//===----------------------------------------------------------------------===//
714
715// Addition
716def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
717def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
718def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
719
720// Subtraction
721def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
722def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
723def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
724
725// Multiply
726def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
727def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
728def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
729def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
730def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
731
732// Multiply and add / subtract
733def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
734def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
735def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
736def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
737
738// Division
739def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
740def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
741def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
742
743//===----------------------------------------------------------------------===//
744// FP: Comparisons
745//===----------------------------------------------------------------------===//
746
747// Compare
748def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
749def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
750def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
751
752// Test Data Class
753def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
754def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
755
756//===----------------------------------------------------------------------===//
757// FP: Floating-point control register instructions
758//===----------------------------------------------------------------------===//
759
760def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
761def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
762def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
763def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
764def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
765def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
766def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;
767
768}
769
770