1//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Scheduler resources
11
12// These resources are used to express decoder grouping rules.  The number of
13// decoder slots needed by an instructions is normally one, but there are
14// exceptions.
15def NormalGr   : SchedWrite;
16def Cracked    : SchedWrite;
17def GroupAlone : SchedWrite;
18def BeginGroup : SchedWrite;
19def EndGroup   : SchedWrite;
20
21// A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
22def LSULatency : SchedWrite;
23
24// Operand WriteLatencies.
25def WLat1 : SchedWrite;
26def WLat2 : SchedWrite;
27def WLat3 : SchedWrite;
28def WLat4 : SchedWrite;
29def WLat5 : SchedWrite;
30def WLat6 : SchedWrite;
31def WLat7 : SchedWrite;
32def WLat8 : SchedWrite;
33def WLat9 : SchedWrite;
34def WLat10 : SchedWrite;
35def WLat11 : SchedWrite;
36def WLat12 : SchedWrite;
37def WLat15 : SchedWrite;
38def WLat16 : SchedWrite;
39def WLat20 : SchedWrite;
40def WLat26 : SchedWrite;
41def WLat30 : SchedWrite;
42
43def WLat1LSU : WriteSequence<[WLat1, LSULatency]>;
44def WLat2LSU : WriteSequence<[WLat2, LSULatency]>;
45def WLat3LSU : WriteSequence<[WLat3, LSULatency]>;
46def WLat4LSU : WriteSequence<[WLat4, LSULatency]>;
47def WLat6LSU : WriteSequence<[WLat6, LSULatency]>;
48def WLat5LSU : WriteSequence<[WLat5, LSULatency]>;
49def WLat7LSU : WriteSequence<[WLat7, LSULatency]>;
50def WLat8LSU : WriteSequence<[WLat8, LSULatency]>;
51def WLat11LSU : WriteSequence<[WLat11, LSULatency]>;
52def WLat16LSU : WriteSequence<[WLat16, LSULatency]>;
53
54// ReadAdvances, used for the register operand next to a memory operand,
55// modelling that the register operand is needed later than the address
56// operands.
57def RegReadAdv : SchedRead;
58
59// Fixed-point units
60def FXa         : SchedWrite;
61def FXa2        : SchedWrite;
62def FXa3        : SchedWrite;
63def FXa4        : SchedWrite;
64def FXb         : SchedWrite;
65def FXb2        : SchedWrite;
66def FXb3        : SchedWrite;
67def FXb4        : SchedWrite;
68def FXb5        : SchedWrite;
69def FXU         : SchedWrite;
70def FXU2        : SchedWrite;
71def FXU3        : SchedWrite;
72def FXU4        : SchedWrite;
73def FXU5        : SchedWrite;
74def FXU6        : SchedWrite;
75
76// Load/store unit
77def LSU         : SchedWrite;
78def LSU2        : SchedWrite;
79def LSU3        : SchedWrite;
80def LSU4        : SchedWrite;
81def LSU5        : SchedWrite;
82
83// Floating point unit (zEC12 and earlier)
84def FPU  : SchedWrite;
85def FPU2 : SchedWrite;
86def FPU4 : SchedWrite;
87def DFU  : SchedWrite;
88def DFU2 : SchedWrite;
89def DFU4 : SchedWrite;
90
91// Vector sub units (z13 and later)
92def VecBF     : SchedWrite;
93def VecBF2    : SchedWrite;
94def VecBF4    : SchedWrite;
95def VecDF     : SchedWrite;
96def VecDF2    : SchedWrite;
97def VecDF4    : SchedWrite;
98def VecDFX    : SchedWrite;
99def VecDFX2   : SchedWrite;
100def VecDFX4   : SchedWrite;
101def VecFPd    : SchedWrite; // Blocking BFP div/sqrt unit.
102def VecMul    : SchedWrite;
103def VecStr    : SchedWrite;
104def VecXsPm   : SchedWrite;
105def VecXsPm2  : SchedWrite;
106
107// Virtual branching unit
108def VBU       : SchedWrite;
109
110// Millicode
111def MCD       : SchedWrite;
112
113include "SystemZScheduleZ14.td"
114include "SystemZScheduleZ13.td"
115include "SystemZScheduleZEC12.td"
116include "SystemZScheduleZ196.td"
117
118