1//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Class definitions.
12//===----------------------------------------------------------------------===//
13
14class SystemZReg<string n> : Register<n> {
15  let Namespace = "SystemZ";
16}
17
18class SystemZRegWithSubregs<string n, list<Register> subregs>
19  : RegisterWithSubRegs<n, subregs> {
20  let Namespace = "SystemZ";
21}
22
23let Namespace = "SystemZ" in {
24def subreg_l32   : SubRegIndex<32, 0>;  // Also acts as subreg_ll32.
25def subreg_h32   : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26def subreg_l64   : SubRegIndex<64, 0>;
27def subreg_h64   : SubRegIndex<64, 64>;
28def subreg_hh32  : ComposedSubRegIndex<subreg_h64, subreg_h32>;
29def subreg_hl32  : ComposedSubRegIndex<subreg_h64, subreg_l32>;
30}
31
32// Define a register class that contains values of type TYPE and an
33// associated operand called NAME.  SIZE is the size and alignment
34// of the registers and REGLIST is the list of individual registers.
35multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> {
36  def AsmOperand : AsmOperandClass {
37    let Name = name;
38    let ParserMethod = "parse"##name;
39    let RenderMethod = "addRegOperands";
40  }
41  def Bit : RegisterClass<"SystemZ", [type], size, regList> {
42    let Size = size;
43  }
44  def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
45    let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
46  }
47}
48
49//===----------------------------------------------------------------------===//
50// General-purpose registers
51//===----------------------------------------------------------------------===//
52
53// Lower 32 bits of one of the 16 64-bit general-purpose registers
54class GPR32<bits<16> num, string n> : SystemZReg<n> {
55  let HWEncoding = num;
56}
57
58// One of the 16 64-bit general-purpose registers.
59class GPR64<bits<16> num, string n, GPR32 low>
60 : SystemZRegWithSubregs<n, [low]> {
61  let HWEncoding = num;
62  let SubRegIndices = [subreg_l32];
63}
64
65// 8 even-odd pairs of GPR64s.
66class GPR128<bits<16> num, string n, GPR64 high, GPR64 low>
67 : SystemZRegWithSubregs<n, [high, low]> {
68  let HWEncoding = num;
69  let SubRegIndices = [subreg_l64, subreg_h64];
70}
71
72// General-purpose registers
73foreach I = 0-15 in {
74  def R#I#L : GPR32<I, "r"#I>;
75  def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L")>, DwarfRegNum<[I]>;
76}
77
78foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
79  def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
80                     !cast<GPR64>("R"#I#"D")>;
81}
82
83/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
84/// together with R14 and R15 in one prolog instruction.
85defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL",  0, 5),
86                                                  (sequence "R%uL", 15, 6))>;
87defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD",  0, 5),
88                                                  (sequence "R%uD", 15, 6))>;
89
90// The architecture doesn't really have any i128 support, so model the
91// register pairs as untyped instead.
92defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q,
93                                                         R12Q, R10Q, R8Q, R6Q,
94                                                         R14Q)>;
95
96// Base and index registers.  Everything except R0, which in an address
97// context evaluates as 0.
98defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0L)>;
99defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>;
100
101// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
102// of a GR128.
103defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>;
104
105//===----------------------------------------------------------------------===//
106// Floating-point registers
107//===----------------------------------------------------------------------===//
108
109// Lower 32 bits of one of the 16 64-bit floating-point registers
110class FPR32<bits<16> num, string n> : SystemZReg<n> {
111  let HWEncoding = num;
112}
113
114// One of the 16 64-bit floating-point registers
115class FPR64<bits<16> num, string n, FPR32 low>
116 : SystemZRegWithSubregs<n, [low]> {
117  let HWEncoding = num;
118  let SubRegIndices = [subreg_h32];
119}
120
121// 8 pairs of FPR64s, with a one-register gap inbetween.
122class FPR128<bits<16> num, string n, FPR64 high, FPR64 low>
123 : SystemZRegWithSubregs<n, [high, low]> {
124  let HWEncoding = num;
125  let SubRegIndices = [subreg_l64, subreg_h64];
126}
127
128// Floating-point registers
129foreach I = 0-15 in {
130  def F#I#S : FPR32<I, "f"#I>;
131  def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
132              DwarfRegNum<[!add(I, 16)]>;
133}
134
135foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
136  def F#I#Q  : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
137                     !cast<FPR64>("F"#I#"D")>;
138}
139
140// There's no store-multiple instruction for FPRs, so we're not fussy
141// about the order in which call-saved registers are allocated.
142defm FP32  : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>;
143defm FP64  : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>;
144defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q,
145                                                      F8Q, F9Q, F12Q, F13Q)>;
146
147//===----------------------------------------------------------------------===//
148// Other registers
149//===----------------------------------------------------------------------===//
150
151// The 2-bit condition code field of the PSW.  Every register named in an
152// inline asm needs a class associated with it.
153def CC : SystemZReg<"cc">;
154def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
155