1//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Class definitions.
12//===----------------------------------------------------------------------===//
13
14class SystemZReg<string n> : Register<n> {
15  let Namespace = "SystemZ";
16}
17
18class SystemZRegWithSubregs<string n, list<Register> subregs>
19  : RegisterWithSubRegs<n, subregs> {
20  let Namespace = "SystemZ";
21}
22
23let Namespace = "SystemZ" in {
24def subreg_32bit  : SubRegIndex; // could also be known as "subreg_high32"
25def subreg_high   : SubRegIndex;
26def subreg_low    : SubRegIndex;
27def subreg_low32  : SubRegIndex<[subreg_low, subreg_32bit]>;
28}
29
30// Define a register class that contains values of type TYPE and an
31// associated operand called NAME.  SIZE is the size and alignment
32// of the registers and REGLIST is the list of individual registers.
33multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> {
34  def AsmOperand : AsmOperandClass {
35    let Name = name;
36    let ParserMethod = "parse"##name;
37    let RenderMethod = "addRegOperands";
38  }
39  def Bit : RegisterClass<"SystemZ", [type], size, regList> {
40    let Size = size;
41  }
42  def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
43    let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
44  }
45}
46
47//===----------------------------------------------------------------------===//
48// General-purpose registers
49//===----------------------------------------------------------------------===//
50
51// Lower 32 bits of one of the 16 64-bit general-purpose registers
52class GPR32<bits<16> num, string n> : SystemZReg<n> {
53  let HWEncoding = num;
54}
55
56// One of the 16 64-bit general-purpose registers.
57class GPR64<bits<16> num, string n, GPR32 low>
58 : SystemZRegWithSubregs<n, [low]> {
59  let HWEncoding = num;
60  let SubRegIndices = [subreg_32bit];
61}
62
63// 8 even-odd pairs of GPR64s.
64class GPR128<bits<16> num, string n, GPR64 high, GPR64 low>
65 : SystemZRegWithSubregs<n, [high, low]> {
66  let HWEncoding = num;
67  let SubRegIndices = [subreg_high, subreg_low];
68}
69
70// General-purpose registers
71foreach I = 0-15 in {
72  def R#I#W : GPR32<I, "r"#I>;
73  def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"W")>, DwarfRegNum<[I]>;
74}
75
76foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
77  def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#I#"D"),
78                     !cast<GPR64>("R"#!add(I, 1)#"D")>;
79}
80
81/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
82/// together with R14 and R15 in one prolog instruction.
83defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uW",  0, 5),
84                                                  (sequence "R%uW", 15, 6))>;
85defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD",  0, 5),
86                                                  (sequence "R%uD", 15, 6))>;
87
88// The architecture doesn't really have any i128 support, so model the
89// register pairs as untyped instead.
90defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q,
91                                                         R12Q, R10Q, R8Q, R6Q,
92                                                         R14Q)>;
93
94// Base and index registers.  Everything except R0, which in an address
95// context evaluates as 0.
96defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0W)>;
97defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>;
98
99// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
100// of a GR128.
101defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>;
102
103//===----------------------------------------------------------------------===//
104// Floating-point registers
105//===----------------------------------------------------------------------===//
106
107// Lower 32 bits of one of the 16 64-bit floating-point registers
108class FPR32<bits<16> num, string n> : SystemZReg<n> {
109  let HWEncoding = num;
110}
111
112// One of the 16 64-bit floating-point registers
113class FPR64<bits<16> num, string n, FPR32 low>
114 : SystemZRegWithSubregs<n, [low]> {
115  let HWEncoding = num;
116  let SubRegIndices = [subreg_32bit];
117}
118
119// 8 pairs of FPR64s, with a one-register gap inbetween.
120class FPR128<bits<16> num, string n, FPR64 high, FPR64 low>
121 : SystemZRegWithSubregs<n, [high, low]> {
122  let HWEncoding = num;
123  let SubRegIndices = [subreg_high, subreg_low];
124}
125
126// Floating-point registers
127foreach I = 0-15 in {
128  def F#I#S : FPR32<I, "f"#I>;
129  def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
130              DwarfRegNum<[!add(I, 16)]>;
131}
132
133foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
134  def F#I#Q  : FPR128<I, "f"#I, !cast<FPR64>("F"#I#"D"),
135                     !cast<FPR64>("F"#!add(I, 2)#"D")>;
136}
137
138// There's no store-multiple instruction for FPRs, so we're not fussy
139// about the order in which call-saved registers are allocated.
140defm FP32  : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>;
141defm FP64  : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>;
142defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q,
143                                                      F8Q, F9Q, F12Q, F13Q)>;
144
145//===----------------------------------------------------------------------===//
146// Other registers
147//===----------------------------------------------------------------------===//
148
149// Status register
150def PSW : SystemZReg<"psw">;
151