1//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Class definitions.
12//===----------------------------------------------------------------------===//
13
14class SystemZReg<string n> : Register<n> {
15  let Namespace = "SystemZ";
16}
17
18class SystemZRegWithSubregs<string n, list<Register> subregs>
19  : RegisterWithSubRegs<n, subregs> {
20  let Namespace = "SystemZ";
21}
22
23let Namespace = "SystemZ" in {
24def subreg_l32   : SubRegIndex<32, 0>;  // Also acts as subreg_ll32.
25def subreg_h32   : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26def subreg_l64   : SubRegIndex<64, 0>;
27def subreg_h64   : SubRegIndex<64, 64>;
28def subreg_r32   : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29def subreg_hh32  : ComposedSubRegIndex<subreg_h64, subreg_h32>;
30def subreg_hl32  : ComposedSubRegIndex<subreg_h64, subreg_l32>;
31def subreg_hr32  : ComposedSubRegIndex<subreg_h64, subreg_r32>;
32}
33
34// Define a register class that contains values of type TYPE and an
35// associated operand called NAME.  SIZE is the size and alignment
36// of the registers and REGLIST is the list of individual registers.
37multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> {
38  def AsmOperand : AsmOperandClass {
39    let Name = name;
40    let ParserMethod = "parse"##name;
41    let RenderMethod = "addRegOperands";
42  }
43  def Bit : RegisterClass<"SystemZ", [type], size, regList> {
44    let Size = size;
45  }
46  def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
47    let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
48  }
49}
50
51//===----------------------------------------------------------------------===//
52// General-purpose registers
53//===----------------------------------------------------------------------===//
54
55// Lower 32 bits of one of the 16 64-bit general-purpose registers
56class GPR32<bits<16> num, string n> : SystemZReg<n> {
57  let HWEncoding = num;
58}
59
60// One of the 16 64-bit general-purpose registers.
61class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
62 : SystemZRegWithSubregs<n, [low, high]> {
63  let HWEncoding = num;
64  let SubRegIndices = [subreg_l32, subreg_h32];
65}
66
67// 8 even-odd pairs of GPR64s.
68class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
69 : SystemZRegWithSubregs<n, [low, high]> {
70  let HWEncoding = num;
71  let SubRegIndices = [subreg_l64, subreg_h64];
72}
73
74// General-purpose registers
75foreach I = 0-15 in {
76  def R#I#L : GPR32<I, "r"#I>;
77  def R#I#H : GPR32<I, "r"#I>;
78  def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
79                    DwarfRegNum<[I]>;
80}
81
82foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
83  def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
84                     !cast<GPR64>("R"#I#"D")>;
85}
86
87/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
88/// together with R14 and R15 in one prolog instruction.
89defm GR32  : SystemZRegClass<"GR32",  i32, 32, (add (sequence "R%uL",  0, 5),
90                                                    (sequence "R%uL", 15, 6))>;
91defm GRH32 : SystemZRegClass<"GRH32", i32, 32, (add (sequence "R%uH",  0, 5),
92                                                    (sequence "R%uH", 15, 6))>;
93defm GR64  : SystemZRegClass<"GR64",  i64, 64, (add (sequence "R%uD",  0, 5),
94                                                    (sequence "R%uD", 15, 6))>;
95
96// Combine the low and high GR32s into a single class.  This can only be
97// used for virtual registers if the high-word facility is available.
98defm GRX32 : SystemZRegClass<"GRX32", i32, 32,
99                             (add (sequence "R%uL",  0, 5),
100                                  (sequence "R%uH",  0, 5),
101                                  R15L, R15H, R14L, R14H, R13L, R13H,
102                                  R12L, R12H, R11L, R11H, R10L, R10H,
103                                  R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>;
104
105// The architecture doesn't really have any i128 support, so model the
106// register pairs as untyped instead.
107defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q,
108                                                         R12Q, R10Q, R8Q, R6Q,
109                                                         R14Q)>;
110
111// Base and index registers.  Everything except R0, which in an address
112// context evaluates as 0.
113defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0L)>;
114defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>;
115
116// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
117// of a GR128.
118defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>;
119
120//===----------------------------------------------------------------------===//
121// Floating-point registers
122//===----------------------------------------------------------------------===//
123
124// Maps FPR register numbers to their DWARF encoding.
125class DwarfMapping<int id> { int Id = id; }
126
127def F0Dwarf  : DwarfMapping<16>;
128def F2Dwarf  : DwarfMapping<17>;
129def F4Dwarf  : DwarfMapping<18>;
130def F6Dwarf  : DwarfMapping<19>;
131
132def F1Dwarf  : DwarfMapping<20>;
133def F3Dwarf  : DwarfMapping<21>;
134def F5Dwarf  : DwarfMapping<22>;
135def F7Dwarf  : DwarfMapping<23>;
136
137def F8Dwarf  : DwarfMapping<24>;
138def F10Dwarf : DwarfMapping<25>;
139def F12Dwarf : DwarfMapping<26>;
140def F14Dwarf : DwarfMapping<27>;
141
142def F9Dwarf  : DwarfMapping<28>;
143def F11Dwarf : DwarfMapping<29>;
144def F13Dwarf : DwarfMapping<30>;
145def F15Dwarf : DwarfMapping<31>;
146
147// Lower 32 bits of one of the 16 64-bit floating-point registers
148class FPR32<bits<16> num, string n> : SystemZReg<n> {
149  let HWEncoding = num;
150}
151
152// One of the 16 64-bit floating-point registers
153class FPR64<bits<16> num, string n, FPR32 low>
154 : SystemZRegWithSubregs<n, [low]> {
155  let HWEncoding = num;
156  let SubRegIndices = [subreg_r32];
157}
158
159// 8 pairs of FPR64s, with a one-register gap inbetween.
160class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
161 : SystemZRegWithSubregs<n, [low, high]> {
162  let HWEncoding = num;
163  let SubRegIndices = [subreg_l64, subreg_h64];
164}
165
166// Floating-point registers
167foreach I = 0-15 in {
168  def F#I#S : FPR32<I, "f"#I>;
169  def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
170              DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
171}
172
173foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
174  def F#I#Q  : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
175                     !cast<FPR64>("F"#I#"D")>;
176}
177
178// There's no store-multiple instruction for FPRs, so we're not fussy
179// about the order in which call-saved registers are allocated.
180defm FP32  : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>;
181defm FP64  : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>;
182defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q,
183                                                      F8Q, F9Q, F12Q, F13Q)>;
184
185//===----------------------------------------------------------------------===//
186// Other registers
187//===----------------------------------------------------------------------===//
188
189// The 2-bit condition code field of the PSW.  Every register named in an
190// inline asm needs a class associated with it.
191def CC : SystemZReg<"cc">;
192def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
193