1 //===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
12 
13 #include "SystemZ.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
15 
16 #define GET_REGINFO_HEADER
17 #include "SystemZGenRegisterInfo.inc"
18 
19 namespace llvm {
20 
21 class LiveIntervals;
22 
23 namespace SystemZ {
24 // Return the subreg to use for referring to the even and odd registers
25 // in a GR128 pair.  Is32Bit says whether we want a GR32 or GR64.
26 inline unsigned even128(bool Is32bit) {
27   return Is32bit ? subreg_hl32 : subreg_h64;
28 }
29 inline unsigned odd128(bool Is32bit) {
30   return Is32bit ? subreg_l32 : subreg_l64;
31 }
32 } // end namespace SystemZ
33 
34 struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
35 public:
36   SystemZRegisterInfo();
37 
38   /// getPointerRegClass - Return the register class to use to hold pointers.
39   /// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
40   /// register, hence ADDR64.
41   const TargetRegisterClass *
42   getPointerRegClass(const MachineFunction &MF,
43                      unsigned Kind=0) const override {
44     return &SystemZ::ADDR64BitRegClass;
45   }
46 
47   bool getRegAllocationHints(unsigned VirtReg,
48                              ArrayRef<MCPhysReg> Order,
49                              SmallVectorImpl<MCPhysReg> &Hints,
50                              const MachineFunction &MF,
51                              const VirtRegMap *VRM,
52                              const LiveRegMatrix *Matrix) const override;
53 
54   // Override TargetRegisterInfo.h.
55   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
56     return true;
57   }
58   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
59     return true;
60   }
61   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
62     return true;
63   }
64   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
65   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
66                                        CallingConv::ID CC) const override;
67   BitVector getReservedRegs(const MachineFunction &MF) const override;
68   void eliminateFrameIndex(MachineBasicBlock::iterator MI,
69                            int SPAdj, unsigned FIOperandNum,
70                            RegScavenger *RS) const override;
71 
72   /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
73  bool shouldCoalesce(MachineInstr *MI,
74                       const TargetRegisterClass *SrcRC,
75                       unsigned SubReg,
76                       const TargetRegisterClass *DstRC,
77                       unsigned DstSubReg,
78                       const TargetRegisterClass *NewRC,
79                       LiveIntervals &LIS) const override;
80 
81   unsigned getFrameRegister(const MachineFunction &MF) const override;
82 };
83 
84 } // end namespace llvm
85 
86 #endif
87