1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZRegisterInfo.h"
11 #include "SystemZInstrInfo.h"
12 #include "SystemZSubtarget.h"
13 #include "llvm/CodeGen/LiveIntervals.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/CodeGen/TargetFrameLowering.h"
18 #include "llvm/CodeGen/VirtRegMap.h"
19 
20 using namespace llvm;
21 
22 #define GET_REGINFO_TARGET_DESC
23 #include "SystemZGenRegisterInfo.inc"
24 
25 SystemZRegisterInfo::SystemZRegisterInfo()
26     : SystemZGenRegisterInfo(SystemZ::R14D) {}
27 
28 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
29 // somehow belongs in it. Otherwise, return GRX32.
30 static const TargetRegisterClass *getRC32(MachineOperand &MO,
31                                           const VirtRegMap *VRM,
32                                           const MachineRegisterInfo *MRI) {
33   const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
34 
35   if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
36       MO.getSubReg() == SystemZ::subreg_l32 ||
37       MO.getSubReg() == SystemZ::subreg_hl32)
38     return &SystemZ::GR32BitRegClass;
39   if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
40       MO.getSubReg() == SystemZ::subreg_h32 ||
41       MO.getSubReg() == SystemZ::subreg_hh32)
42     return &SystemZ::GRH32BitRegClass;
43 
44   if (VRM && VRM->hasPhys(MO.getReg())) {
45     unsigned PhysReg = VRM->getPhys(MO.getReg());
46     if (SystemZ::GR32BitRegClass.contains(PhysReg))
47       return &SystemZ::GR32BitRegClass;
48     assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
49             "Phys reg not in GR32 or GRH32?");
50     return &SystemZ::GRH32BitRegClass;
51   }
52 
53   assert (RC == &SystemZ::GRX32BitRegClass);
54   return RC;
55 }
56 
57 bool
58 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
59                                            ArrayRef<MCPhysReg> Order,
60                                            SmallVectorImpl<MCPhysReg> &Hints,
61                                            const MachineFunction &MF,
62                                            const VirtRegMap *VRM,
63                                            const LiveRegMatrix *Matrix) const {
64   const MachineRegisterInfo *MRI = &MF.getRegInfo();
65   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
66   if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
67     SmallVector<unsigned, 8> Worklist;
68     SmallSet<unsigned, 4> DoneRegs;
69     Worklist.push_back(VirtReg);
70     while (Worklist.size()) {
71       unsigned Reg = Worklist.pop_back_val();
72       if (!DoneRegs.insert(Reg).second)
73         continue;
74 
75       for (auto &Use : MRI->use_instructions(Reg))
76         // For LOCRMux, see if the other operand is already a high or low
77         // register, and in that case give the correpsonding hints for
78         // VirtReg. LOCR instructions need both operands in either high or
79         // low parts.
80         if (Use.getOpcode() == SystemZ::LOCRMux) {
81           MachineOperand &TrueMO = Use.getOperand(1);
82           MachineOperand &FalseMO = Use.getOperand(2);
83           const TargetRegisterClass *RC =
84             TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
85                                    getRC32(TrueMO, VRM, MRI));
86           if (RC && RC != &SystemZ::GRX32BitRegClass) {
87             for (MCPhysReg Reg : Order)
88               if (RC->contains(Reg) && !MRI->isReserved(Reg))
89                 Hints.push_back(Reg);
90             // Return true to make these hints the only regs available to
91             // RA. This may mean extra spilling but since the alternative is
92             // a jump sequence expansion of the LOCRMux, it is preferred.
93             return true;
94           }
95 
96           // Add the other operand of the LOCRMux to the worklist.
97           unsigned OtherReg =
98             (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
99           if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
100             Worklist.push_back(OtherReg);
101         }
102     }
103   }
104 
105   return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
106                                                    VRM, Matrix);
107 }
108 
109 const MCPhysReg *
110 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
111   if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
112       MF->getFunction().getAttributes().hasAttrSomewhere(
113           Attribute::SwiftError))
114     return CSR_SystemZ_SwiftError_SaveList;
115   return CSR_SystemZ_SaveList;
116 }
117 
118 const uint32_t *
119 SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
120                                           CallingConv::ID CC) const {
121   if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
122       MF.getFunction().getAttributes().hasAttrSomewhere(
123           Attribute::SwiftError))
124     return CSR_SystemZ_SwiftError_RegMask;
125   return CSR_SystemZ_RegMask;
126 }
127 
128 BitVector
129 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
130   BitVector Reserved(getNumRegs());
131   const SystemZFrameLowering *TFI = getFrameLowering(MF);
132 
133   if (TFI->hasFP(MF)) {
134     // R11D is the frame pointer.  Reserve all aliases.
135     Reserved.set(SystemZ::R11D);
136     Reserved.set(SystemZ::R11L);
137     Reserved.set(SystemZ::R11H);
138     Reserved.set(SystemZ::R10Q);
139   }
140 
141   // R15D is the stack pointer.  Reserve all aliases.
142   Reserved.set(SystemZ::R15D);
143   Reserved.set(SystemZ::R15L);
144   Reserved.set(SystemZ::R15H);
145   Reserved.set(SystemZ::R14Q);
146 
147   // A0 and A1 hold the thread pointer.
148   Reserved.set(SystemZ::A0);
149   Reserved.set(SystemZ::A1);
150 
151   return Reserved;
152 }
153 
154 void
155 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
156                                          int SPAdj, unsigned FIOperandNum,
157                                          RegScavenger *RS) const {
158   assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
159 
160   MachineBasicBlock &MBB = *MI->getParent();
161   MachineFunction &MF = *MBB.getParent();
162   auto *TII =
163       static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
164   const SystemZFrameLowering *TFI = getFrameLowering(MF);
165   DebugLoc DL = MI->getDebugLoc();
166 
167   // Decompose the frame index into a base and offset.
168   int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
169   unsigned BasePtr;
170   int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
171                     MI->getOperand(FIOperandNum + 1).getImm());
172 
173   // Special handling of dbg_value instructions.
174   if (MI->isDebugValue()) {
175     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
176     MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
177     return;
178   }
179 
180   // See if the offset is in range, or if an equivalent instruction that
181   // accepts the offset exists.
182   unsigned Opcode = MI->getOpcode();
183   unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
184   if (OpcodeForOffset) {
185     if (OpcodeForOffset == SystemZ::LE &&
186         MF.getSubtarget<SystemZSubtarget>().hasVector()) {
187       // If LE is ok for offset, use LDE instead on z13.
188       OpcodeForOffset = SystemZ::LDE32;
189     }
190     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
191   }
192   else {
193     // Create an anchor point that is in range.  Start at 0xffff so that
194     // can use LLILH to load the immediate.
195     int64_t OldOffset = Offset;
196     int64_t Mask = 0xffff;
197     do {
198       Offset = OldOffset & Mask;
199       OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
200       Mask >>= 1;
201       assert(Mask && "One offset must be OK");
202     } while (!OpcodeForOffset);
203 
204     unsigned ScratchReg =
205       MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
206     int64_t HighOffset = OldOffset - Offset;
207 
208     if (MI->getDesc().TSFlags & SystemZII::HasIndex
209         && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
210       // Load the offset into the scratch register and use it as an index.
211       // The scratch register then dies here.
212       TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
213       MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
214       MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
215                                                         false, false, true);
216     } else {
217       // Load the anchor address into a scratch register.
218       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
219       if (LAOpcode)
220         BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
221           .addReg(BasePtr).addImm(HighOffset).addReg(0);
222       else {
223         // Load the high offset into the scratch register and use it as
224         // an index.
225         TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
226         BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
227           .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
228       }
229 
230       // Use the scratch register as the base.  It then dies here.
231       MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
232                                                     false, false, true);
233     }
234   }
235   MI->setDesc(TII->get(OpcodeForOffset));
236   MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
237 }
238 
239 bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
240                                   const TargetRegisterClass *SrcRC,
241                                   unsigned SubReg,
242                                   const TargetRegisterClass *DstRC,
243                                   unsigned DstSubReg,
244                                   const TargetRegisterClass *NewRC,
245                                   LiveIntervals &LIS) const {
246   assert (MI->isCopy() && "Only expecting COPY instructions");
247 
248   // Coalesce anything which is not a COPY involving a subreg to/from GR128.
249   if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
250         (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
251     return true;
252 
253   // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
254   // and local to one MBB with not too much interferring registers. Otherwise
255   // regalloc may run out of registers.
256 
257   unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
258   unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
259   unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
260   LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
261   LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
262 
263   // Check that the two virtual registers are local to MBB.
264   MachineBasicBlock *MBB = MI->getParent();
265   if (LIS.isLiveInToMBB(IntGR128, MBB) || LIS.isLiveOutOfMBB(IntGR128, MBB) ||
266       LIS.isLiveInToMBB(IntGRNar, MBB) || LIS.isLiveOutOfMBB(IntGRNar, MBB))
267     return false;
268 
269   // Find the first and last MIs of the registers.
270   MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
271   if (WideOpNo == 1) {
272     FirstMI = LIS.getInstructionFromIndex(IntGR128.beginIndex());
273     LastMI  = LIS.getInstructionFromIndex(IntGRNar.endIndex());
274   } else {
275     FirstMI = LIS.getInstructionFromIndex(IntGRNar.beginIndex());
276     LastMI  = LIS.getInstructionFromIndex(IntGR128.endIndex());
277   }
278   assert (FirstMI && LastMI && "No instruction from index?");
279 
280   // Check if coalescing seems safe by finding the set of clobbered physreg
281   // pairs in the region.
282   BitVector PhysClobbered(getNumRegs());
283   MachineBasicBlock::iterator MII = FirstMI, MEE = LastMI;
284   MEE++;
285   for (; MII != MEE; ++MII) {
286     for (const MachineOperand &MO : MII->operands())
287       if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
288         for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
289              SI.isValid(); ++SI)
290           if (NewRC->contains(*SI)) {
291             PhysClobbered.set(*SI);
292             break;
293           }
294       }
295   }
296 
297   // Demand an arbitrary margin of free regs.
298   unsigned const DemandedFreeGR128 = 3;
299   if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
300     return false;
301 
302   return true;
303 }
304 
305 unsigned
306 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
307   const SystemZFrameLowering *TFI = getFrameLowering(MF);
308   return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
309 }
310