1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZRegisterInfo.h"
11 #include "SystemZInstrInfo.h"
12 #include "SystemZSubtarget.h"
13 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/TargetFrameLowering.h"
17 
18 using namespace llvm;
19 
20 #define GET_REGINFO_TARGET_DESC
21 #include "SystemZGenRegisterInfo.inc"
22 
23 SystemZRegisterInfo::SystemZRegisterInfo()
24     : SystemZGenRegisterInfo(SystemZ::R14D) {}
25 
26 const MCPhysReg *
27 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
28   if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
29       MF->getFunction()->getAttributes().hasAttrSomewhere(
30           Attribute::SwiftError))
31     return CSR_SystemZ_SwiftError_SaveList;
32   return CSR_SystemZ_SaveList;
33 }
34 
35 const uint32_t *
36 SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
37                                           CallingConv::ID CC) const {
38   if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
39       MF.getFunction()->getAttributes().hasAttrSomewhere(
40           Attribute::SwiftError))
41     return CSR_SystemZ_SwiftError_RegMask;
42   return CSR_SystemZ_RegMask;
43 }
44 
45 BitVector
46 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
47   BitVector Reserved(getNumRegs());
48   const SystemZFrameLowering *TFI = getFrameLowering(MF);
49 
50   if (TFI->hasFP(MF)) {
51     // R11D is the frame pointer.  Reserve all aliases.
52     Reserved.set(SystemZ::R11D);
53     Reserved.set(SystemZ::R11L);
54     Reserved.set(SystemZ::R11H);
55     Reserved.set(SystemZ::R10Q);
56   }
57 
58   // R15D is the stack pointer.  Reserve all aliases.
59   Reserved.set(SystemZ::R15D);
60   Reserved.set(SystemZ::R15L);
61   Reserved.set(SystemZ::R15H);
62   Reserved.set(SystemZ::R14Q);
63 
64   // A0 and A1 hold the thread pointer.
65   Reserved.set(SystemZ::A0);
66   Reserved.set(SystemZ::A1);
67 
68   return Reserved;
69 }
70 
71 void
72 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
73                                          int SPAdj, unsigned FIOperandNum,
74                                          RegScavenger *RS) const {
75   assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
76 
77   MachineBasicBlock &MBB = *MI->getParent();
78   MachineFunction &MF = *MBB.getParent();
79   auto *TII =
80       static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
81   const SystemZFrameLowering *TFI = getFrameLowering(MF);
82   DebugLoc DL = MI->getDebugLoc();
83 
84   // Decompose the frame index into a base and offset.
85   int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
86   unsigned BasePtr;
87   int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
88                     MI->getOperand(FIOperandNum + 1).getImm());
89 
90   // Special handling of dbg_value instructions.
91   if (MI->isDebugValue()) {
92     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
93     MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
94     return;
95   }
96 
97   // See if the offset is in range, or if an equivalent instruction that
98   // accepts the offset exists.
99   unsigned Opcode = MI->getOpcode();
100   unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
101   if (OpcodeForOffset) {
102     if (OpcodeForOffset == SystemZ::LE &&
103         MF.getSubtarget<SystemZSubtarget>().hasVector()) {
104       // If LE is ok for offset, use LDE instead on z13.
105       OpcodeForOffset = SystemZ::LDE32;
106     }
107     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
108   }
109   else {
110     // Create an anchor point that is in range.  Start at 0xffff so that
111     // can use LLILH to load the immediate.
112     int64_t OldOffset = Offset;
113     int64_t Mask = 0xffff;
114     do {
115       Offset = OldOffset & Mask;
116       OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
117       Mask >>= 1;
118       assert(Mask && "One offset must be OK");
119     } while (!OpcodeForOffset);
120 
121     unsigned ScratchReg =
122       MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
123     int64_t HighOffset = OldOffset - Offset;
124 
125     if (MI->getDesc().TSFlags & SystemZII::HasIndex
126         && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
127       // Load the offset into the scratch register and use it as an index.
128       // The scratch register then dies here.
129       TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
130       MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
131       MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
132                                                         false, false, true);
133     } else {
134       // Load the anchor address into a scratch register.
135       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
136       if (LAOpcode)
137         BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
138           .addReg(BasePtr).addImm(HighOffset).addReg(0);
139       else {
140         // Load the high offset into the scratch register and use it as
141         // an index.
142         TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
143         BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
144           .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
145       }
146 
147       // Use the scratch register as the base.  It then dies here.
148       MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
149                                                     false, false, true);
150     }
151   }
152   MI->setDesc(TII->get(OpcodeForOffset));
153   MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
154 }
155 
156 bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
157                                   const TargetRegisterClass *SrcRC,
158                                   unsigned SubReg,
159                                   const TargetRegisterClass *DstRC,
160                                   unsigned DstSubReg,
161                                   const TargetRegisterClass *NewRC,
162                                   LiveIntervals &LIS) const {
163   assert (MI->isCopy() && "Only expecting COPY instructions");
164 
165   // Coalesce anything which is not a COPY involving a subreg to/from GR128.
166   if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
167         (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
168     return true;
169 
170   // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
171   // and local to one MBB with not too much interferring registers. Otherwise
172   // regalloc may run out of registers.
173 
174   unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
175   unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
176   unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
177   LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
178   LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
179 
180   // Check that the two virtual registers are local to MBB.
181   MachineBasicBlock *MBB = MI->getParent();
182   if (LIS.isLiveInToMBB(IntGR128, MBB) || LIS.isLiveOutOfMBB(IntGR128, MBB) ||
183       LIS.isLiveInToMBB(IntGRNar, MBB) || LIS.isLiveOutOfMBB(IntGRNar, MBB))
184     return false;
185 
186   // Find the first and last MIs of the registers.
187   MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
188   if (WideOpNo == 1) {
189     FirstMI = LIS.getInstructionFromIndex(IntGR128.beginIndex());
190     LastMI  = LIS.getInstructionFromIndex(IntGRNar.endIndex());
191   } else {
192     FirstMI = LIS.getInstructionFromIndex(IntGRNar.beginIndex());
193     LastMI  = LIS.getInstructionFromIndex(IntGR128.endIndex());
194   }
195   assert (FirstMI && LastMI && "No instruction from index?");
196 
197   // Check if coalescing seems safe by finding the set of clobbered physreg
198   // pairs in the region.
199   BitVector PhysClobbered(getNumRegs());
200   MachineBasicBlock::iterator MII = FirstMI, MEE = LastMI;
201   MEE++;
202   for (; MII != MEE; ++MII) {
203     for (const MachineOperand &MO : MII->operands())
204       if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
205         for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
206              SI.isValid(); ++SI)
207           if (NewRC->contains(*SI)) {
208             PhysClobbered.set(*SI);
209             break;
210           }
211       }
212   }
213 
214   // Demand an arbitrary margin of free regs.
215   unsigned const DemandedFreeGR128 = 3;
216   if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
217     return false;
218 
219   return true;
220 }
221 
222 unsigned
223 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
224   const SystemZFrameLowering *TFI = getFrameLowering(MF);
225   return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
226 }
227