1 //===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZ.h"
15 #include "SystemZInstrInfo.h"
16 #include "SystemZMachineFunctionInfo.h"
17 #include "SystemZRegisterInfo.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/BitVector.h"
28 
29 #define GET_REGINFO_MC_DESC
30 #define GET_REGINFO_TARGET_DESC
31 #include "SystemZGenRegisterInfo.inc"
32 
33 using namespace llvm;
34 
35 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
36                                          const SystemZInstrInfo &tii)
37   : SystemZGenRegisterInfo(), TM(tm), TII(tii) {
38 }
39 
40 const unsigned*
41 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
42   static const unsigned CalleeSavedRegs[] = {
43     SystemZ::R6D,  SystemZ::R7D,  SystemZ::R8D,  SystemZ::R9D,
44     SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
45     SystemZ::R14D, SystemZ::R15D,
46     SystemZ::F8L,  SystemZ::F9L,  SystemZ::F10L, SystemZ::F11L,
47     SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
48     0
49   };
50 
51   return CalleeSavedRegs;
52 }
53 
54 BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
55   BitVector Reserved(getNumRegs());
56   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
57 
58   if (TFI->hasFP(MF)) {
59     // R11D is the frame pointer. Reserve all aliases.
60     Reserved.set(SystemZ::R11D);
61     Reserved.set(SystemZ::R11W);
62     Reserved.set(SystemZ::R10P);
63     Reserved.set(SystemZ::R10Q);
64   }
65 
66   Reserved.set(SystemZ::R14D);
67   Reserved.set(SystemZ::R15D);
68   Reserved.set(SystemZ::R14W);
69   Reserved.set(SystemZ::R15W);
70   Reserved.set(SystemZ::R14P);
71   Reserved.set(SystemZ::R14Q);
72   return Reserved;
73 }
74 
75 const TargetRegisterClass*
76 SystemZRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
77                                               const TargetRegisterClass *B,
78                                               unsigned Idx) const {
79   switch(Idx) {
80   // Exact sub-classes don't exist for the other sub-register indexes.
81   default: return 0;
82   case SystemZ::subreg_32bit:
83     if (B == SystemZ::ADDR32RegisterClass)
84       return A->getSize() == 8 ? SystemZ::ADDR64RegisterClass : 0;
85     return A;
86   }
87 }
88 
89 void SystemZRegisterInfo::
90 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
91                               MachineBasicBlock::iterator I) const {
92   MBB.erase(I);
93 }
94 
95 void
96 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
97                                          int SPAdj, RegScavenger *RS) const {
98   assert(SPAdj == 0 && "Unxpected");
99 
100   unsigned i = 0;
101   MachineInstr &MI = *II;
102   MachineFunction &MF = *MI.getParent()->getParent();
103   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
104 
105   while (!MI.getOperand(i).isFI()) {
106     ++i;
107     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
108   }
109 
110   int FrameIndex = MI.getOperand(i).getIndex();
111 
112   unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
113 
114   // This must be part of a rri or ri operand memory reference.  Replace the
115   // FrameIndex with base register with BasePtr.  Add an offset to the
116   // displacement field.
117   MI.getOperand(i).ChangeToRegister(BasePtr, false);
118 
119   // Offset is a either 12-bit unsigned or 20-bit signed integer.
120   // FIXME: handle "too long" displacements.
121   int Offset =
122     TFI->getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
123 
124   // Check whether displacement is too long to fit into 12 bit zext field.
125   MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
126 
127   MI.getOperand(i+1).ChangeToImmediate(Offset);
128 }
129 
130 unsigned SystemZRegisterInfo::getRARegister() const {
131   assert(0 && "What is the return address register");
132   return 0;
133 }
134 
135 unsigned
136 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
137   assert(0 && "What is the frame register");
138   return 0;
139 }
140 
141 unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
142   assert(0 && "What is the exception register");
143   return 0;
144 }
145 
146 unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
147   assert(0 && "What is the exception handler register");
148   return 0;
149 }
150 
151 int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
152   assert(0 && "What is the dwarf register number");
153   return -1;
154 }
155 
156 int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
157   assert(0 && "What is the dwarf register number");
158   return -1;
159 }
160