1 //===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZ.h"
15 #include "SystemZInstrInfo.h"
16 #include "SystemZMachineFunctionInfo.h"
17 #include "SystemZRegisterInfo.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/BitVector.h"
28 using namespace llvm;
29 
30 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
31                                          const SystemZInstrInfo &tii)
32   : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
33     TM(tm), TII(tii) {
34 }
35 
36 const unsigned*
37 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
38   static const unsigned CalleeSavedRegs[] = {
39     SystemZ::R6D,  SystemZ::R7D,  SystemZ::R8D,  SystemZ::R9D,
40     SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
41     SystemZ::R14D, SystemZ::R15D,
42     SystemZ::F8L,  SystemZ::F9L,  SystemZ::F10L, SystemZ::F11L,
43     SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
44     0
45   };
46 
47   return CalleeSavedRegs;
48 }
49 
50 BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
51   BitVector Reserved(getNumRegs());
52   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
53 
54   if (TFI->hasFP(MF))
55     Reserved.set(SystemZ::R11D);
56   Reserved.set(SystemZ::R14D);
57   Reserved.set(SystemZ::R15D);
58   return Reserved;
59 }
60 
61 const TargetRegisterClass*
62 SystemZRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
63                                               const TargetRegisterClass *B,
64                                               unsigned Idx) const {
65   switch(Idx) {
66   // Exact sub-classes don't exist for the other sub-register indexes.
67   default: return 0;
68   case SystemZ::subreg_32bit:
69     if (B == SystemZ::ADDR32RegisterClass)
70       return A->getSize() == 8 ? SystemZ::ADDR64RegisterClass : 0;
71     return A;
72   }
73 }
74 
75 void SystemZRegisterInfo::
76 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
77                               MachineBasicBlock::iterator I) const {
78   MBB.erase(I);
79 }
80 
81 void
82 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
83                                          int SPAdj, RegScavenger *RS) const {
84   assert(SPAdj == 0 && "Unxpected");
85 
86   unsigned i = 0;
87   MachineInstr &MI = *II;
88   MachineFunction &MF = *MI.getParent()->getParent();
89   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90 
91   while (!MI.getOperand(i).isFI()) {
92     ++i;
93     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
94   }
95 
96   int FrameIndex = MI.getOperand(i).getIndex();
97 
98   unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
99 
100   // This must be part of a rri or ri operand memory reference.  Replace the
101   // FrameIndex with base register with BasePtr.  Add an offset to the
102   // displacement field.
103   MI.getOperand(i).ChangeToRegister(BasePtr, false);
104 
105   // Offset is a either 12-bit unsigned or 20-bit signed integer.
106   // FIXME: handle "too long" displacements.
107   int Offset =
108     TFI->getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
109 
110   // Check whether displacement is too long to fit into 12 bit zext field.
111   MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
112 
113   MI.getOperand(i+1).ChangeToImmediate(Offset);
114 }
115 
116 unsigned SystemZRegisterInfo::getRARegister() const {
117   assert(0 && "What is the return address register");
118   return 0;
119 }
120 
121 unsigned
122 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
123   assert(0 && "What is the frame register");
124   return 0;
125 }
126 
127 unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
128   assert(0 && "What is the exception register");
129   return 0;
130 }
131 
132 unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
133   assert(0 && "What is the exception handler register");
134   return 0;
135 }
136 
137 int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
138   assert(0 && "What is the dwarf register number");
139   return -1;
140 }
141 
142 int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
143   assert(0 && "What is the dwarf register number");
144   return -1;
145 }
146 
147 
148 #include "SystemZGenRegisterInfo.inc"
149